; -------------------------------------------------------------------------------- ; @Title: MSPM0 On-Chip Peripherals ; @Props: Released ; @Author: NEJ ; @Changelog: 2025-02-21 NEJ ; @Manufacturer: TI - Texas Instruments ; @Doc: Generated (TRACE32, build: 177130.), based on: ; MSPM0C110X.svd (Preliminary), MSPM0G110X.svd (Preliminary), ; MSPM0G150X.svd (Preliminary), MSPM0G151X.svd (Preliminary), ; MSPM0G310X.svd (Preliminary), MSPM0G350x.svd (Preliminary), ; MSPM0G351X.svd (Preliminary), MSPM0L110X.svd (Preliminary), ; MSPM0L111X.svd (Preliminary), MSPM0L122X.svd (Preliminary), ; MSPM0L134X.svd (Preliminary), MSPM0L130x.svd (Preliminary), ; MSPM0L222X.svd (Preliminary) ; @Core: Cortex-M0+ ; @Chip: MSPM0C1103, MSPM0C1104, MSPM0G1105, MSPM0G1106, ; MSPM0G1107, MSPM0G1505, MSPM0G1506, MSPM0G1507, ; MSPM0G3105, MSPM0G3105Q1, MSPM0G3106, MSPM0G3106Q1, ; MSPM0G3107, MSPM0G3107Q1, MSPM0G3505, MSPM0G3505Q1, ; MSPM0G3506, MSPM0G3506Q1, MSPM0G3507, MSPM0G3507Q1, ; MSPM0L1105, MSPM0L1106, MSPM0L1116, MSPM0L1117, ; MSPM0L1227, MSPM0L1228, MSPM0L1303, MSPM0L1304, ; MSPM0L1304Q1, MSPM0L1305, MSPM0L1305Q1, MSPM0L1306, ; MSPM0L1306Q1, MSPM0L1343, MSPM0L1344, MSPM0L1345, ; MSPM0L1346, MSPM0L2227, MSPM0L2228, MSPS003F3, ; MSPS003F4 ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; ; Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; ; Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the ; distribution. ; ; Neither the name of Texas Instruments Incorporated nor the names of ; its contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; -------------------------------------------------------------------------------- ; $Id: permspm0.per 19105 2025-02-25 10:19:07Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif if (CORENAME()=="CORTEXM1") rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" textline " " bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF" textline " " abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" elif (CORENAME()=="CORTEXM0+") rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" textline " " bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF" textline " " abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" else rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" textline " " bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF" textline " " abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" endif group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0x0 sif (cpuis("MSPM0G150*")) tree "ADC0" base ad:0x40000000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_GPRCM[%s]" base ad:0x40000800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40001020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40001050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40001080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40000000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G151*")) tree "ADC0" base ad:0x40000000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_CPU_INT[%s]" base ad:0x40001020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_CPU_INT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_DMA_TRIG[%s]" base ad:0x40001080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_DMA_TRIG_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_DMA_TRIG_IMASK,Interrupt mask extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_DMA_TRIG_RIS,Raw interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_DMA_TRIG_MIS,Masked interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_DMA_TRIG_ISET,Interrupt set extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_DMA_TRIG_ICLR,Interrupt clear extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end tree "ADC0_GEN_EVENT[%s]" base ad:0x40001050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_GEN_EVENT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_GPRCM[%s]" base ad:0x40000800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40000000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 4. "RSTSAMPCAPEN,0: Sample and hold capacitor is not explicitly discharged at the end of conversion." "0: Sample and hold capacitor is not explicitly..,1: Sample and hold capacitor is discharged at the.." newline bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--10. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,3: VDDA and VREFM connected to VREF+ and VREF- of ADC,4: INTREF and VREFM connected to VREF+ and VREF- of..,?,?,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G310*")) tree "ADC0" base ad:0x40000000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_GPRCM[%s]" base ad:0x40000800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40001020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40001050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40001080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40000000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G350*")) tree "ADC0" base ad:0x40000000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_GPRCM[%s]" base ad:0x40000800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40001020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40001050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40001080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40000000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G351*")) tree "ADC0" base ad:0x40000000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_CPU_INT[%s]" base ad:0x40001020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_CPU_INT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_DMA_TRIG[%s]" base ad:0x40001080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_DMA_TRIG_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_DMA_TRIG_IMASK,Interrupt mask extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_DMA_TRIG_RIS,Raw interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_DMA_TRIG_MIS,Masked interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_DMA_TRIG_ISET,Interrupt set extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_DMA_TRIG_ICLR,Interrupt clear extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end tree "ADC0_GEN_EVENT[%s]" base ad:0x40001050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_GEN_EVENT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_GPRCM[%s]" base ad:0x40000800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40000000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 4. "RSTSAMPCAPEN,0: Sample and hold capacitor is not explicitly discharged at the end of conversion." "0: Sample and hold capacitor is not explicitly..,1: Sample and hold capacitor is discharged at the.." newline bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--10. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,3: VDDA and VREFM connected to VREF+ and VREF- of ADC,4: INTREF and VREFM connected to VREF+ and VREF- of..,?,?,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G110*")) tree "ADC1" base ad:0x40002000 group.long 0x400++0x3 line.long 0x0 "ADC1_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC1_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC1_GPRCM[%s]" base ad:0x40002800 group.long 0x0++0x3 line.long 0x0 "ADC1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC1_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC1_INT_EVENT0[%s]" base ad:0x40003020 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT1[%s]" base ad:0x40003050 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT2[%s]" base ad:0x40003080 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40002000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC1_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC1_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC1_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC1_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC1_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC1_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC1_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC1_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC1_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC1_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G150*")) tree "ADC1" base ad:0x40002000 group.long 0x400++0x3 line.long 0x0 "ADC1_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC1_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC1_GPRCM[%s]" base ad:0x40002800 group.long 0x0++0x3 line.long 0x0 "ADC1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC1_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC1_INT_EVENT0[%s]" base ad:0x40003020 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT1[%s]" base ad:0x40003050 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT2[%s]" base ad:0x40003080 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40002000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC1_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC1_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC1_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC1_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC1_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC1_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC1_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC1_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC1_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC1_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G151*")) tree "ADC1" base ad:0x40002000 group.long 0x400++0x3 line.long 0x0 "ADC1_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC1_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC1_CPU_INT[%s]" base ad:0x40003020 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_CPU_INT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_DMA_TRIG[%s]" base ad:0x40003080 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_DMA_TRIG_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_DMA_TRIG_IMASK,Interrupt mask extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_DMA_TRIG_RIS,Raw interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_DMA_TRIG_MIS,Masked interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_DMA_TRIG_ISET,Interrupt set extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_DMA_TRIG_ICLR,Interrupt clear extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end tree "ADC1_GEN_EVENT[%s]" base ad:0x40003050 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_GEN_EVENT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_GPRCM[%s]" base ad:0x40002800 group.long 0x0++0x3 line.long 0x0 "ADC1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC1_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40002000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC1_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC1_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC1_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 4. "RSTSAMPCAPEN,0: Sample and hold capacitor is not explicitly discharged at the end of conversion." "0: Sample and hold capacitor is not explicitly..,1: Sample and hold capacitor is discharged at the.." newline bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC1_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC1_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC1_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC1_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC1_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC1_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--10. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,3: VDDA and VREFM connected to VREF+ and VREF- of ADC,4: INTREF and VREFM connected to VREF+ and VREF- of..,?,?,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC1_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G310*")) tree "ADC1" base ad:0x40002000 group.long 0x400++0x3 line.long 0x0 "ADC1_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC1_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC1_GPRCM[%s]" base ad:0x40002800 group.long 0x0++0x3 line.long 0x0 "ADC1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC1_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC1_INT_EVENT0[%s]" base ad:0x40003020 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT1[%s]" base ad:0x40003050 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT2[%s]" base ad:0x40003080 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40002000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC1_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC1_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC1_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC1_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC1_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC1_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC1_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC1_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC1_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC1_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G350*")) tree "ADC1" base ad:0x40002000 group.long 0x400++0x3 line.long 0x0 "ADC1_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC1_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC1_GPRCM[%s]" base ad:0x40002800 group.long 0x0++0x3 line.long 0x0 "ADC1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC1_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC1_INT_EVENT0[%s]" base ad:0x40003020 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT1[%s]" base ad:0x40003050 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_INT_EVENT2[%s]" base ad:0x40003080 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40002000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC1_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC1_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC1_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC1_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC1_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC1_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC1_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC1_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC1_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC1_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G351*")) tree "ADC1" base ad:0x40002000 group.long 0x400++0x3 line.long 0x0 "ADC1_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC1_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC1_CPU_INT[%s]" base ad:0x40003020 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_CPU_INT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_DMA_TRIG[%s]" base ad:0x40003080 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_DMA_TRIG_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_DMA_TRIG_IMASK,Interrupt mask extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_DMA_TRIG_RIS,Raw interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_DMA_TRIG_MIS,Masked interrupt status extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_DMA_TRIG_ISET,Interrupt set extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_DMA_TRIG_ICLR,Interrupt clear extension" bitfld.long 0x0 31. "MEMRESIFG23,Raw interrupt status for MEMRES23." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 30. "MEMRESIFG22,Raw interrupt status for MEMRES22." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 29. "MEMRESIFG21,Raw interrupt status for MEMRES21." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 28. "MEMRESIFG20,Raw interrupt status for MEMRES20." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 27. "MEMRESIFG19,Raw interrupt status for MEMRES19." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 26. "MEMRESIFG18,Raw interrupt status for MEMRES18." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 25. "MEMRESIFG17,Raw interrupt status for MEMRES17." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 24. "MEMRESIFG16,Raw interrupt status for MEMRES16." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 23. "MEMRESIFG15,Raw interrupt status for MEMRES15." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 22. "MEMRESIFG14,Raw interrupt status for MEMRES14." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 21. "MEMRESIFG13,Raw interrupt status for MEMRES13." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 20. "MEMRESIFG12,Raw interrupt status for MEMRES12." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end tree "ADC1_GEN_EVENT[%s]" base ad:0x40003050 rgroup.long 0x0++0x3 line.long 0x0 "ADC1_GEN_EVENT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC1_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC1_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC1_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC1_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC1_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC1_GPRCM[%s]" base ad:0x40002800 group.long 0x0++0x3 line.long 0x0 "ADC1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC1_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40002000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC1_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC1_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC1_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 4. "RSTSAMPCAPEN,0: Sample and hold capacitor is not explicitly discharged at the end of conversion." "0: Sample and hold capacitor is not explicitly..,1: Sample and hold capacitor is discharged at the.." newline bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC1_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC1_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC1_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC1_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC1_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC1_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--10. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,3: VDDA and VREFM connected to VREF+ and VREF- of ADC,4: INTREF and VREFM connected to VREF+ and VREF- of..,?,?,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC1_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) base ad:0x40004000 elif (cpuis("MSPM0G110*")) base ad:0x40000000 endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "ADC0" group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G110*")) tree "ADC0_INT_EVENT0[%s]" base ad:0x40001020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end endif sif (cpuis("MSPM0G110*")) tree "ADC0_INT_EVENT1[%s]" base ad:0x40001050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end endif sif (cpuis("MSPM0G110*")) tree "ADC0_INT_EVENT2[%s]" base ad:0x40001080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) base ad:0x40004800 elif (cpuis("MSPM0G110*")) base ad:0x40000800 endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "ADC0_GPRCM[%s]" group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" endif rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) tree "ADC0_CPU_INT[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_CPU_INT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_GEN_EVENT[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_GEN_EVENT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_DMA_TRIG[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_DMA_TRIG_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_DMA_TRIG_IMASK,Interrupt mask extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_DMA_TRIG_RIS,Raw interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_DMA_TRIG_MIS,Masked interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_DMA_TRIG_ISET,Interrupt set extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_DMA_TRIG_ICLR,Interrupt clear extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end newline repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end endif rgroup.long 0x10E0++0x3 line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." sif (cpuis("MSPM0G110*")) repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end endif tree.end endif sif (cpuis("MSPM0L110*")) tree "ADC0" base ad:0x40004000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "ADC0_GPRCM[%s]" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40004000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0L111*")) tree "ADC0" base ad:0x40004000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." tree "ADC0_CPU_INT[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_CPU_INT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_DMA_TRIG[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_DMA_TRIG_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_DMA_TRIG_IMASK,Interrupt mask extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_DMA_TRIG_RIS,Raw interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_DMA_TRIG_MIS,Masked interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_DMA_TRIG_ISET,Interrupt set extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_DMA_TRIG_ICLR,Interrupt clear extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end tree "ADC0_GEN_EVENT[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_GEN_EVENT_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_GPRCM[%s]" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40004000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--10. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,3: VDDA and VREFM connected to VREF+ and VREF- of ADC,4: INTREF and VREFM connected to VREF+ and VREF- of..,?,?,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0L122*")) tree "ADC0" base ad:0x40004000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_GPRCM[%s]" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40004000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0L130*")) tree "ADC0" base ad:0x40004000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "ADC0_GPRCM[%s]" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40004000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0L134*")) tree "ADC0" base ad:0x40004000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "ADC0_GPRCM[%s]" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: SYSOSC is the source of ADC sample clock.,1: ULPCLK is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40004000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0L222*")) tree "ADC0" base ad:0x40004000 group.long 0x400++0x3 line.long 0x0 "ADC0_FSUB_0,Subscriber Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "ADC0_FPUB_1,Publisher Configuration Register." hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "ADC0_GPRCM[%s]" base ad:0x40004800 group.long 0x0++0x3 line.long 0x0 "ADC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "ADC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "ADC0_CLKCFG,ADC clock configuration Register" bitfld.long 0x0 5. "CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." bitfld.long 0x0 4. "CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: ADC conversion clock source is not kept..,1: ADC conversion clock source kept continuously on.." newline bitfld.long 0x0 0.--1. "SAMPCLK,ADC sample clock source selection." "0: ULPCLK is the source of ADC sample clock.,1: SYSOSC is the source of ADC sample clock.,2: HFCLK clock is the source of ADC sample clock.,?" rgroup.long 0x14++0x3 line.long 0x0 "ADC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end tree "ADC0_INT_EVENT0[%s]" base ad:0x40005020 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 6. "UVIFG,Raw interrupt flag for MEMRESx underflow." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 5. "DMADONE,Raw interrupt flag for DMADONE." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 1. "TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 0. "OVIFG,Raw interrupt flag for MEMRESx overflow." "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT1[%s]" base ad:0x40005050 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 4. "INIFG,Mask INIFG in MIS_EX register." "0: Interrupt is not pending.,1: Interrupt is pending." bitfld.long 0x0 3. "LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: Interrupt is not pending.,1: Interrupt is pending." newline bitfld.long 0x0 2. "HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: Interrupt is not pending.,1: Interrupt is pending." tree.end tree "ADC0_INT_EVENT2[%s]" base ad:0x40005080 rgroup.long 0x0++0x3 line.long 0x0 "ADC0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.word 0x0 0.--9. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "ADC0_INT_EVENT2_IMASK,Interrupt mask extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x10++0x3 line.long 0x0 "ADC0_INT_EVENT2_RIS,Raw interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." rgroup.long 0x18++0x3 line.long 0x0 "ADC0_INT_EVENT2_MIS,Masked interrupt status extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x20++0x3 line.long 0x0 "ADC0_INT_EVENT2_ISET,Interrupt set extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." wgroup.long 0x28++0x3 line.long 0x0 "ADC0_INT_EVENT2_ICLR,Interrupt clear extension" bitfld.long 0x0 19. "MEMRESIFG11,Raw interrupt status for MEMRES11." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 18. "MEMRESIFG10,Raw interrupt status for MEMRES10." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 17. "MEMRESIFG9,Raw interrupt status for MEMRES9." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 16. "MEMRESIFG8,Raw interrupt status for MEMRES8." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 15. "MEMRESIFG7,Raw interrupt status for MEMRES7." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 14. "MEMRESIFG6,Raw interrupt status for MEMRES6." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 13. "MEMRESIFG5,Raw interrupt status for MEMRES5." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 12. "MEMRESIFG4,Raw interrupt status for MEMRES4." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 11. "MEMRESIFG3,Raw interrupt status for MEMRES3." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 10. "MEMRESIFG2,Raw interrupt status for MEMRES2." "0: No new data ready.,1: A new data is ready to be read." newline bitfld.long 0x0 9. "MEMRESIFG1,Raw interrupt status for MEMRES1." "0: No new data ready.,1: A new data is ready to be read." bitfld.long 0x0 8. "MEMRESIFG0,Raw interrupt status for MEMRES0." "0: No new data ready.,1: A new data is ready to be read." tree.end base ad:0x40004000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "ADC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "ADC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "ADC0_CTL0,Control Register 0" bitfld.long 0x0 24.--26. "SCLKDIV,Sample clock divider" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 4,3: Divide clock source by 8,4: Divide clock source by 16,5: Divide clock source by 24,6: Divide clock source by 32,7: Divide clock source by 48" bitfld.long 0x0 16. "PWRDN,Power down policy" "0: ADC is powered down on completion of a..,1: ADC remains powered on as long as it is enabled.." newline bitfld.long 0x0 0. "ENC,Enable conversion" "0: Conversion disabled. ENC change from ON to OFF..,1: Conversion enabled. ADC sequencer waits for.." line.long 0x4 "ADC0_CTL1,Control Register 1" bitfld.long 0x4 28.--30. "AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: No shift,1: 1 bit shift,2: 2 bit shift,3: 3 bit shift,4: 4 bit shift,5: 5 bit shift,6: 6 bit shift,7: 7 bit shift" bitfld.long 0x4 24.--26. "AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: Disables averager,1: Averages 2 conversions before storing in MEMRESx..,2: Averages 4 conversions before storing in MEMRESx..,3: Averages 8 conversions before storing in MEMRESx..,4: Averages 16 conversions before storing in..,5: Averages 32 conversions before storing in..,6: Averages 64 conversions before storing in..,7: Averages 128 conversions before storing in.." newline bitfld.long 0x4 20. "SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: Sample timer high phase is used as sample signal,1: Software trigger is used as sample signal" bitfld.long 0x4 16.--17. "CONSEQ,Conversion sequence mode" "0: ADC channel in MEMCTLx pointed by STARTADD will..,1: ADC channel sequence pointed by STARTADD and..,2: ADC channel in MEMCTLx pointed by STARTADD will..,3: ADC channel sequence pointed by STARTADD and.." newline bitfld.long 0x4 8. "SC,Start of conversion" "0: When SAMPMODE is set to MANUAL clearing this bit..,1: When SAMPMODE is set to MANUAL setting this bit.." bitfld.long 0x4 0. "TRIGSRC,Sample trigger source" "0: Software trigger,1: Hardware event trigger" line.long 0x8 "ADC0_CTL2,Control Register 2" hexmask.long.byte 0x8 24.--28. 1. "ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode." hexmask.long.byte 0x8 16.--20. 1. "STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode." newline hexmask.long.byte 0x8 11.--15. 1. "SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger" bitfld.long 0x8 10. "FIFOEN,Enable FIFO based operation" "0: Disable,1: Enable" newline bitfld.long 0x8 8. "DMAEN,Enable DMA trigger for data transfer." "0: DMA trigger not enabled,1: DMA trigger enabled" bitfld.long 0x8 1.--2. "RES,Resolution. These bits define the resolution of ADC conversion result." "0: 12-bits resolution,1: 10-bits resolution,2: 8-bits resolution,?" newline bitfld.long 0x8 0. "DF,Data read-back format. Data is always stored in binary unsigned format." "0: Digital result reads as Binary Unsigned.,1: Digital result reads Signed Binary. (2s.." group.long 0x1110++0xB line.long 0x0 "ADC0_CLKFREQ,Sample Clock Frequency Range Register" bitfld.long 0x0 0.--2. "FRANGE,Frequency Range." "0: 1 to 4 MHz,1: >4 to 8 MHz,2: >8 to 16 MHz,3: >16 to 20 MHz,4: >20 to 24 MHz,5: >24 to 32 MHz,6: >32 to 40 MHz,7: >40 to 48 MHz" line.long 0x4 "ADC0_SCOMP0,Sample Time Compare 0 Register" hexmask.long.word 0x4 0.--9. 1. "VAL,Specifies the number of sample clocks." line.long 0x8 "ADC0_SCOMP1,Sample Time Compare 1 Register" hexmask.long.word 0x8 0.--9. 1. "VAL,Specifies the number of sample clocks." group.long 0x1148++0x3 line.long 0x0 "ADC0_WCLOW,Window Comparator Low Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." group.long 0x1150++0x3 line.long 0x0 "ADC0_WCHIGH,Window Comparator High Threshold Register" hexmask.long.word 0x0 0.--15. 1. "DATA,If DF = 0 unsigned binary format has to be used." repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1180)++0x3 line.long 0x0 "ADC0_MEMCTL[$1],Conversion Memory Control Register" bitfld.long 0x0 28. "WINCOMP,Enable window comparator." "0: Disable,1: Enable" bitfld.long 0x0 24. "TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: Next conversion is automatic,1: Next conversion requires a trigger" newline bitfld.long 0x0 20. "BCSEN,Enable burn out current source." "0: Disable,1: Enable" bitfld.long 0x0 16. "AVGEN,Enable hardware averaging." "0: Averaging disabled.,1: Averaging enabled." newline bitfld.long 0x0 12. "STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: Select SCOMP0,1: Select SCOMP1" bitfld.long 0x0 8.--9. "VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA reference,1: External reference from pin,2: Internal reference,?" newline hexmask.long.byte 0x0 0.--4. 1. "CHANSEL,Input channel select." repeat.end rgroup.long 0x1340++0x3 line.long 0x0 "ADC0_STATUS,Status Register" bitfld.long 0x0 1. "REFBUFRDY,Indicates reference buffer is powered up and ready." "0: Not ready,1: Ready" rbitfld.long 0x0 0. "BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: No ADC sampling or conversion in progress.,1: ADC sampling or conversion is in progress." tree.end endif sif (cpuis("MSPM0G150*")) tree "ADC0_SVT" base ad:0x40556000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G151*")) tree "ADC0_SVT" base ad:0x40556000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G310*")) tree "ADC0_SVT" base ad:0x40556000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G350*")) tree "ADC0_SVT" base ad:0x40556000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G351*")) tree "ADC0_SVT" base ad:0x40556000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G110*")) tree "ADC1_SVT" base ad:0x40558000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC1_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC1_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G150*")) tree "ADC1_SVT" base ad:0x40558000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC1_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC1_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G151*")) tree "ADC1_SVT" base ad:0x40558000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC1_SVT_FIFODATA,FIFO Data Register" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC1_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G310*")) tree "ADC1_SVT" base ad:0x40558000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC1_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC1_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G350*")) tree "ADC1_SVT" base ad:0x40558000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC1_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC1_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0G351*")) tree "ADC1_SVT" base ad:0x40558000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC1_SVT_FIFODATA,FIFO Data Register" repeat 24. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC1_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) base ad:0x4055A000 elif (cpuis("MSPM0G110*")) base ad:0x40556000 endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "ADC0_SVT" rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end endif sif (cpuis("MSPM0G110*")) repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end endif tree.end endif sif (cpuis("MSPM0L110*")) tree "ADC0_SVT" base ad:0x4055A000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0L111*")) tree "ADC0_SVT" base ad:0x4055A000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0L122*")) tree "ADC0_SVT" base ad:0x4055A000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0L130*")) tree "ADC0_SVT" base ad:0x4055A000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0L134*")) tree "ADC0_SVT" base ad:0x4055A000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif sif (cpuis("MSPM0L222*")) tree "ADC0_SVT" base ad:0x4055A000 rgroup.long 0x556160++0x3 line.long 0x0 "ADC0_SVT_FIFODATA,FIFO Data Register" repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x556280)++0x3 line.long 0x0 "ADC0_SVT_MEMRES[$1],Memory Result Register" hexmask.long.word 0x0 0.--15. 1. "DATA,MEMRES result register." repeat.end tree.end endif tree.end sif (cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "AES (Advanced Encryption Standard Accelerator)" base ad:0x40442000 tree "AES_GPRCM[%s]" base ad:0x40442800 group.long 0x0++0x3 line.long 0x0 "AES_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "AES_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "AES_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40442000 newline group.long 0x1018++0x3 newline line.long 0x0 "AES_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "AES_INT_EVENT0[%s]" base ad:0x40443020 rgroup.long 0x0++0x3 line.long 0x0 "AES_INT_EVENT0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AES_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 3. "DMA2,DMA2 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "DMA1,DMA1 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "DMA0,DMA0 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AES_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 3. "DMA2,DMA2 event" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 2. "DMA1,DMA1 event" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "DMA0,DMA0 event" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AES_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 3. "DMA2,DMA2 event" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 2. "DMA1,DMA1 event" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "DMA0,DMA0 event" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AES_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 3. "DMA2,DMA2" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "DMA1,DMA1" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "DMA0,DMA0" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AES_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 3. "DMA2,DMA2" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "DMA1,DMA1" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "DMA0,DMA0" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "AES_INT_EVENT1[%s]" base ad:0x40443050 rgroup.long 0x0++0x3 line.long 0x0 "AES_INT_EVENT1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AES_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 1. "DMA0,DMA0 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AES_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 1. "DMA0,DMA0 event" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AES_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 1. "DMA0,DMA0 event" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AES_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 1. "DMA0,DMA0" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AES_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 1. "DMA0,DMA0 event" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "AES_INT_EVENT2[%s]" base ad:0x40443080 rgroup.long 0x0++0x3 line.long 0x0 "AES_INT_EVENT2_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AES_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 2. "DMA1,DMA1 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AES_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 2. "DMA1,DMA1 event" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AES_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 2. "DMA1,DMA1 event" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AES_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 2. "DMA1,DMA1 event" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AES_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 2. "DMA1,DMA1 event" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "AES_INT_EVENT3[%s]" base ad:0x404430B0 rgroup.long 0x0++0x3 line.long 0x0 "AES_INT_EVENT3_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AES_INT_EVENT3_IMASK,Interrupt mask" bitfld.long 0x0 3. "DMA2,DMA2 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AES_INT_EVENT3_RIS,Raw interrupt status" bitfld.long 0x0 3. "DMA2,DMA2 event" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AES_INT_EVENT3_MIS,Masked interrupt status" bitfld.long 0x0 3. "DMA2,DMA2 event" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AES_INT_EVENT3_ISET,Interrupt set" bitfld.long 0x0 3. "DMA2,DMA2 event" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AES_INT_EVENT3_ICLR,Interrupt clear" bitfld.long 0x0 3. "DMA2,DMA2 event" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40442000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "AES_EVT_MODE,Event Mode" bitfld.long 0x0 6.--7. "EVT3_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" group.long 0x1100++0xB line.long 0x0 "AES_AESACTL0,AES accelerator control register 0" bitfld.long 0x0 15. "CMEN,AESCMEN enables the support of the cipher modes ECB CBC OFB and CFB together with the DMA. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0." "0: No DMA triggers are generated,1: DMA cipher mode support operation is enabled and.." bitfld.long 0x0 11. "ERRFG,AES error flag." "0: No error,1: Error occurred" newline bitfld.long 0x0 7. "SWRST,AES software reset." "0: No reset.,1: Reset AES accelerator module." bitfld.long 0x0 5.--6. "CMx,AES cipher mode select. These bits are ignored for AESCMEN = 0. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0." "0: ECB,1: CBC,2: OFB,3: CFB" newline bitfld.long 0x0 2.--3. "KLx,AES key length." "0: The key size is 128 bit.,?,2: The key size is 256 bit.,?" bitfld.long 0x0 0.--1. "OPx,AES operation." "0: Encryption,1: Decryption. The provided key is the same key..,2: Generate first round key required for decryption.,3: Decryption. The provided key is the first round.." line.long 0x4 "AES_AESACTL1,AES accelerator control register 1" hexmask.long.byte 0x4 0.--7. 1. "BLKCNTx,Cipher Block Counter. Number of blocks to be encrypted or decrypted with block cipher modes enabled (AESCMEN = 1). Ignored if AESCMEN = 0. The block counter decrements with each performed encryption or decryption. Writes are ignored when AESCMEN.." line.long 0x8 "AES_AESASTAT,aes accelerator status register" hexmask.long.byte 0x8 12.--15. 1. "DOUTCNTx,Bytes read from AESADOUT. Reset when AESDOUTRD is reset. If AESDOUTCNTx = 0 and AESDOUTRD = 0 no bytes were read. If AESDOUTCNTx = 0 and AESDOUTRD = 1 all bytes were read." hexmask.long.byte 0x8 8.--11. 1. "DINCNTx,Bytes written to AESADIN AESAXDIN or AESAXIN. Reset when AESDINWR is reset. If AESDINCNTx = 0 and AESDINWR = 0 no bytes were written. If AESDINCNTx = 0 and AESDINWR = 1 all bytes were written." newline hexmask.long.byte 0x8 4.--7. 1. "KEYCNTx,Bytes written to AESAKEY when AESKLx = 00 half-words written to AESAKEY if AESKLx = b10. Reset when AESKEYWR is reset. If AESKEYCNTx = 0 and AESKEYWR = 0 no bytes were written. If AESKEYCNTx = 0 and AESKEYWR = 1 all bytes were written." rbitfld.long 0x8 3. "DOUTRD,All 16 bytes read from AESADOUT. AESDOUTRD is reset by PUC AESSWRST an error condition changing AESOPx changing AESKLx when the AES accelerator is busy and when the output data is read again." "0: Not all bytes read,1: All bytes read" newline bitfld.long 0x8 2. "DINWR,All 16 bytes written to AESADIN AESAXDIN or AESAXIN. Changing its state by software also resets the AESDINCNTx bits. AESDINWR is reset by PUC AESSWRST an error condition changing AESOPx changing AESKLx the start to (over)write the data and.." "0: Not all bytes written,1: All bytes written" bitfld.long 0x8 1. "KEYWR,All bytes written to AESAKEY. This bit can be modified by software but it must not be reset by software (10) if AESCMEN=1. Changing its state by software also resets the AESKEYCNTx bits. AESKEYWR is reset by PUC AESSWRST an error condition .." "0: Not all bytes written,1: All bytes written" newline rbitfld.long 0x8 0. "BUSY,AES accelerator module busy; encryption decryption or key generation in progress." "0: Not busy,1: Busy" wgroup.long 0x110C++0x7 line.long 0x0 "AES_AESAKEY,aes accelerator key register" hexmask.long.byte 0x0 24.--31. 1. "KEY3x,AES key byte n+3 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1." hexmask.long.byte 0x0 16.--23. 1. "KEY2x,AES key byte n+2 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1." newline hexmask.long.byte 0x0 8.--15. 1. "KEY1x,AES key byte n+1 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1." hexmask.long.byte 0x0 0.--7. 1. "KEY0x,AES key byte n when AESAKEY is written as word. AES next key byte when AESAKEY is written as byte. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1." line.long 0x4 "AES_AESADIN,aes accelerator data in register" hexmask.long.byte 0x4 24.--31. 1. "DIN3x,AES data in byte n+3 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." hexmask.long.byte 0x4 16.--23. 1. "DIN2x,AES data in byte n+2 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." newline hexmask.long.byte 0x4 8.--15. 1. "DIN1x,AES data in byte n+1 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." hexmask.long.byte 0x4 0.--7. 1. "DIN0x,AES data in byte n when AESADIN is written as word. AES next data in byte when AESADIN is written as byte. Do not mix word and byte access. Always reads as zero." rgroup.long 0x1114++0x3 line.long 0x0 "AES_AESADOUT,aes accelerator data out register" hexmask.long.byte 0x0 24.--31. 1. "DOUT3x,AES data out byte n+3 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access." hexmask.long.byte 0x0 16.--23. 1. "DOUT2x,AES data out byte n+2 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access." newline hexmask.long.byte 0x0 8.--15. 1. "DOUT1x,AES data out byte n+1 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access." hexmask.long.byte 0x0 0.--7. 1. "DOUT0x,AES data out byte n when AESADOUT is read as word. AES next data out byte when AESADOUT is read as byte. Do not mix word and byte access." wgroup.long 0x1118++0x7 line.long 0x0 "AES_AESAXDIN,aes accelerator xored data in register" hexmask.long.byte 0x0 24.--31. 1. "XDIN3x,AES data in byte n+3 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." hexmask.long.byte 0x0 16.--23. 1. "XDIN2x,AES data in byte n+2 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." newline hexmask.long.byte 0x0 8.--15. 1. "XDIN1x,AES data in byte n+1 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." hexmask.long.byte 0x0 0.--7. 1. "XDIN0x,AES data in byte n when AESAXDIN is written as word. AES next data in byte when AESAXDIN is written as byte. Do not mix word and byte access. Always reads as zero." line.long 0x4 "AES_AESAXIN,aes accelerator xored data in register (no trigger)" hexmask.long.byte 0x4 24.--31. 1. "XIN3x,AES data in byte n+3 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." hexmask.long.byte 0x4 16.--23. 1. "XIN2x,AES data in byte n+2 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." newline hexmask.long.byte 0x4 8.--15. 1. "XIN1x,AES data in byte n+1 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero." hexmask.long.byte 0x4 0.--7. 1. "XIN0x,AES data in byte n when AESAXIN is written as word. AES next data in byte when AESAXIN is written as byte. Do not mix word and byte access. Always reads as zero." tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "AESADV (Acelerator Module)" base ad:0x40442000 tree "AESADV_GPRCM[%s]" base ad:0x40442800 group.long 0x0++0x3 line.long 0x0 "AESADV_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "AESADV_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "AESADV_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40442000 newline rgroup.long 0x1018++0x3 newline line.long 0x0 "AESADV_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "?,1: The peripheral ignores the state of the Core.." tree "AESADV_INT_EVENT0[%s]" base ad:0x40443020 rgroup.long 0x0++0x3 line.long 0x0 "AESADV_INT_EVENT0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AESADV_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 3. "CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AESADV_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 3. "CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AESADV_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 3. "CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AESADV_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 3. "CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INPUTRDY,This indicates that the engine can take new input.This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AESADV_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 3. "CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the context_ready bit." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "AESADV_INT_EVENT1[%s]" base ad:0x40443050 rgroup.long 0x0++0x3 line.long 0x0 "AESADV_INT_EVENT1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AESADV_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 0. "TRIG0,TRIG0 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AESADV_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 0. "TRIG0,TRIG0 event" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AESADV_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 0. "TRIG0,TRIG0 event" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AESADV_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 0. "TRIG0,TRIG0" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AESADV_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 0. "TRIG0,TRIG0 event" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "AESADV_INT_EVENT2[%s]" base ad:0x40443080 rgroup.long 0x0++0x3 line.long 0x0 "AESADV_INT_EVENT2_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "AESADV_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 0. "TRIG1,TRIG1 event mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "AESADV_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 0. "TRIG1,TRIG1 event" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "AESADV_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 0. "TRIG1,TRIG1 event" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "AESADV_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 0. "TRIG1,TRIG1 event" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "AESADV_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 0. "TRIG1,TRIG1 event" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40442000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "AESADV_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x1100++0x3F line.long 0x0 "AESADV_GCMCCM_TAG0,CBC-MAC third key (LSW) / GCM & CCM Intermediate TAG (LSW)" line.long 0x4 "AESADV_GCMCCM_TAG1,CBC-MAC third key / GCM & CCM Intermediate TAG" line.long 0x8 "AESADV_GCMCCM_TAG2,CBC-MAC third key / GCM & CCM Intermediate TAG" line.long 0xC "AESADV_GCMCCM_TAG3,CBC-MAC third key (MSW) / GCM & CCM Intermediate TAG (MSW)" line.long 0x10 "AESADV_GHASH_H0,CCM & CBC-MAC second key (LSW) / GCM Hash Key input (LSW)" line.long 0x14 "AESADV_GHASH_H1,CCM & CBC-MAC second key / GCM Hash Key input" line.long 0x18 "AESADV_GHASH_H2,CCM & CBC-MAC second key / GCM Hash Key input" line.long 0x1C "AESADV_GHASH_H3,CCM & CBC-MAC second key (MSW) / GCM Hash Key input (MSW)" line.long 0x20 "AESADV_KEY0,KEY (LSW)" line.long 0x24 "AESADV_KEY1,KEY" line.long 0x28 "AESADV_KEY2,KEY" line.long 0x2C "AESADV_KEY3,KEY" line.long 0x30 "AESADV_KEY4,KEY" line.long 0x34 "AESADV_KEY5,KEY" line.long 0x38 "AESADV_KEY6,KEY" line.long 0x3C "AESADV_KEY7,KEY (MSW)" group.long 0x1140++0x13 line.long 0x0 "AESADV_IV0,IV (LSW)" line.long 0x4 "AESADV_IV1,IV" line.long 0x8 "AESADV_IV2,IV" line.long 0xC "AESADV_IV3,IV" line.long 0x10 "AESADV_CTRL,Input/Output Buffer Control and Mode selection" rbitfld.long 0x10 31. "CNTXT_RDY,If 1b this read-only status bit indicates that the context data registers can be overwritten and the CPU is permitted to write the next context." "0: Not ready,1: Ready" newline rbitfld.long 0x10 30. "SAVED_CNTXT_RDY,If 1b this read-only status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the.." "0: Not ready,1: Ready" newline bitfld.long 0x10 29. "SAVE_CNTXT,This bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set context output DMA and/or interrupt will be asserted if the operation is finished and related signals are enabled." "0: No effect,1: Enable" newline bitfld.long 0x10 28. "GCM_CONT,Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase." "0: No effect,1: Enable" newline bitfld.long 0x10 27. "GET_DIGEST,Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation." "0: No effect,1: Enable" newline bitfld.long 0x10 26. "OFB_GCM_CCM_CONT,This bit has a dual use depending on the selection of CCM/GCM see bits [18:16]." "?,1: Continue GCM/CCM processing in AAD phase" newline bitfld.long 0x10 22.--24. "CCMM,Defines M that indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-39 always returns a 128-bit authentication field of which the M least.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 19.--21. "CCML,Defines L that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 18. "CCM,If set to 1b AES-CCM is selected this is a combined mode using AES for both authentication and encryption. In addition to the CCM bit the CTR mode bit must be set such that AES-CTR is enabled. Other combinations with CCM are invalid." "0: Disable CBC mode,1: Select CBC mode" newline bitfld.long 0x10 16.--17. "GCM,If not set to 00b AES-GCM mode is selected this is a combined mode using the Galois field multiplier GF(2128) for authentication and AES-CTR mode for encryption the bits specify the GCM mode: 01b = GHASH with H loaded and Y0-encrypted forced to.." "?,1: GHASH with H loaded and Y0-encrypted forced to 0.,2: GHASH with H loaded and Y0-encrypted calculated..,3: Autonomous GHASH (both H and Y0-encrypted.." newline bitfld.long 0x10 15. "CBCMAC,If set to 1b AES-CBC MAC is selected the Direction bit must be set to 1 for this mode." "0: Disable CBC mode,1: Select CBC mode" newline bitfld.long 0x10 10. "CFB,If set to 1b AES cipher feedback mode CFB is selected. Use the ctr_width field to specify the feedback width." "0: Disable CBC mode,1: Select CBC mode" newline bitfld.long 0x10 9. "ICM,When the CFB bit is set specifies the CFB mode feedback width:" "0: Disable CBC mode,1: Select CBC mode" newline bitfld.long 0x10 7.--8. "CTR_WIDTH,When the CTR bit is set specifies the counter width for AES-CTR mode." "0: CFB-128 mode,1: 64-bit counter,2: 96-bit counter,3: 128-bit counter" newline bitfld.long 0x10 6. "CTR,If set to 1b AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM when encryption/decryption is required." "0: Disable CBC mode,1: Select CBC mode" newline bitfld.long 0x10 5. "CBC,If set to 1b cipher-block-chaining (CBC) mode is selected." "0: Disable CBC mode,1: Select CBC mode" newline bitfld.long 0x10 3.--4. "KEYSIZE,Specifies the encryption strength / key width" "?,1: 128-bit key,?,3: 256-bit key" newline bitfld.long 0x10 2. "DIR,Direction. If set to 1b an encrypt operation is performed. If set to 0b a decrypt operation is performed. Note: This bit must be written with a 1b when CBC-MAC is selected." "0: Decryption,1: Encryption" newline rbitfld.long 0x10 1. "INPUT_RDY,Ready for input. If 1b this read-only status bit indicates that the 16-byte input buffer is empty and the CPU is permitted to write the next block of data. After reset this bit is 0. After writing a context this bit will become 1b." "0: Not Ready,1: Ready" newline rbitfld.long 0x10 0. "OUTPUT_RDY,Output Ready. If 1b this read-only status bit indicates that an AES output block is available for the CPU to retrieve." "0: Not Ready,1: Ready" wgroup.long 0x1154++0xB line.long 0x0 "AESADV_C_LENGTH_0,Crypto data length (LSW)" line.long 0x4 "AESADV_C_LENGTH_1,Crypto data length (MSW)" hexmask.long 0x4 0.--28. 1. "DATA,Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (261-1) bytes are allowed." line.long 0x8 "AESADV_AAD_LENGTH,AAD Data Length" group.long 0x1160++0xF line.long 0x0 "AESADV_DATA0,Data input (LSW) / Data output (LSW)" line.long 0x4 "AESADV_DATA1,Data input / Data output" line.long 0x8 "AESADV_DATA2,Data input / Data output" line.long 0xC "AESADV_DATA3,Data input (LSW) / Data output (MSW)" rgroup.long 0x1170++0x13 line.long 0x0 "AESADV_TAG0,Hash result (LSW)" line.long 0x4 "AESADV_TAG1,Hash result" line.long 0x8 "AESADV_TAG2,Hash result" line.long 0xC "AESADV_TAG3,Hash result (MSW)" line.long 0x10 "AESADV_STATUS,Status" bitfld.long 0x10 0. "KEYWR,Key write status. 0 - user write to KEY register is allowed. 1 - user write to KEY register is ignored." "0: User write to KEY MMR is allowed,1: User write to KEY MMR is disabled. Writing has.." wgroup.long 0x1184++0x3 line.long 0x0 "AESADV_DATA_IN,Data in alias register" rgroup.long 0x1188++0x3 line.long 0x0 "AESADV_DATA_OUT,Data out alias register" wgroup.long 0x11D0++0x3 line.long 0x0 "AESADV_FORCE_IN_AV,Data control register for input data" group.long 0x11D4++0xB line.long 0x0 "AESADV_CCM_ALN_WRD,AES-CCM AAD alignment data word" line.long 0x4 "AESADV_BLK_CNT0,Internal block counter (LSW)" line.long 0x8 "AESADV_BLK_CNT1,Internal block counter (MSW)" hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Internal block counter for AES GCM and CCM operations." group.long 0x11F4++0x3 line.long 0x0 "AESADV_DMA_HS,Control register for DMA handshaking" bitfld.long 0x0 0. "DMA_DATA_ACK,When this bit is 0b input and output data acknowledge is I/O register based as specified in the description of the AES_DATA_IN_n / AES_DATA_OUT_n registers." "0: Disable DMA based data handshake,1: Enables DMA based handshake" tree.end endif sif (cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")) tree "CANFD (FD Controler Area Network)" base ad:0x0 tree "CANFD0 (PERIPHERALREGION)" base ad:0x40508000 group.long 0x6800++0x3 line.long 0x0 "CANFD0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x6804++0x3 line.long 0x0 "CANFD0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x6814++0x3 line.long 0x0 "CANFD0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree "CANFD0_MCAN[%s]" base ad:0x4050F000 rgroup.long 0x0++0x7 line.long 0x0 "CANFD0_MCAN_CREL,MCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release. One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release. One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release. One digit BCD-coded." hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year. One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month. Two digits BCD-coded." newline hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day. Two digits BCD-coded." line.long 0x4 "CANFD0_MCAN_ENDN,MCAN Endian Register" group.long 0xC++0x23 line.long 0x0 "CANFD0_MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual.." hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CANFD0_MCAN_TEST,MCAN Test Register" sif (cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) rbitfld.long 0x4 7. "RX,Receive Pin. Monitors the actual value of the CAN receive pin." "0,1" bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1" endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 7. "RX,Receive Pin. Monitors the actual value of the CAN receive pin." "0: The CAN bus is dominant (CAN RX pin = '0'),1: The CAN bus is recessive (CAN RX pin = '1')" endif bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" line.long 0x8 "CANFD0_MCAN_RWD,MCAN RAM Watchdog" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value. Acutal Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled." line.long 0xC "CANFD0_MCAN_CCCR,MCAN CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation. If this bit is set the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause. If this bit is set the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame." "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1" newline bitfld.long 0xC 8. "FDOE,Flexible Datarate Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time." "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time." "0,1" bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "CANFD0_MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." line.long 0x14 "CANFD0_MCAN_TSCC,MCAN Timestamp Counter Configuration" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here.." bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "CANFD0_MCAN_TSCV,MCAN Timestamp Counter Value" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01" the Timestamp Counter is incremented in multiples of CAN bit times (1...16) depending on the.." line.long 0x1C "CANFD0_MCAN_TOCC,MCAN Timeout Counter Configuration" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period." bitfld.long 0x1C 1.--2. "TOS,Timeout Select. When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO presets the counter to.." "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "CANFD0_MCAN_TOCV,MCAN Timeout Counter Value" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times (1...16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and.." rgroup.long 0x40++0x7 line.long 0x0 "CANFD0_MCAN_ECR,MCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of.." bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter. Actual state of the Receive Error Counter values between 0 and 127." hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter. Actual state of the Transmit Error Counter values between 0 and 255." line.long 0x4 "CANFD0_MCAN_PSR,MCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value. Position of the secondary sample point defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is in the data phase the number of.." bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message. This bit is set independent of acceptance filtering." "0,1" bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF independent of acceptance filtering." "0,1" bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF independent of acceptance filtering." "0,1" newline bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Node Activity. Monitors the module's CAN communication state." "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "CANFD0_MCAN_TDCR,MCAN Transmitter Delay Compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq." hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature.." group.long 0x50++0xF line.long 0x0 "CANFD0_MCAN_IR,MCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" newline bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected. Message RAM bit error detected uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to.." "0,1" bitfld.long 0x0 19. "DRX,Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0,1" newline bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure. The flag is set when the Rx Handler:" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" newline bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CANFD0_MCAN_IE,MCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" newline bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Enable" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Enable" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Enable" "0,1" newline bitfld.long 0x4 19. "DRXE,Message Stored to Dedicated Rx Buffer Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Enable" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Enable" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Enable" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Enable" "0,1" bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Enable" "0,1" newline bitfld.long 0x4 9. "TCE,Transmission Completed Enable" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message Enable" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Enable" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Enable" "0,1" bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Enable" "0,1" newline bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Enable" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Enable" "0,1" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Enable" "0,1" line.long 0x8 "CANFD0_MCAN_ILS,MCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Line" "0,1" newline bitfld.long 0x8 24. "EWL,Warning Status Line" "0,1" bitfld.long 0x8 23. "EPL,Error Passive Line" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Line" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Line" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Line" "0,1" newline bitfld.long 0x8 19. "DRXL,Message Stored to Dedicated Rx Buffer Line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Line" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Line" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Line" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Line" "0,1" bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Line" "0,1" newline bitfld.long 0x8 9. "TCL,Transmission Completed Line" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Line" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Line" "0,1" bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Line" "0,1" newline bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Line" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Line" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Line" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Line" "0,1" line.long 0xC "CANFD0_MCAN_ILE,MCAN Interrupt Line Enable" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "CANFD0_MCAN_GFC,MCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated." "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated." "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0,1" line.long 0x4 "CANFD0_MCAN_SIDFC,MCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address)." line.long 0x8 "CANFD0_MCAN_XIDFC,MCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--22. 1. "LSE,Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address)." hexmask.long.word 0x8 2.--15. 1. "FLESA,List Size Extended" group.long 0x90++0x3 line.long 0x0 "CANFD0_MCAN_XIDAM,MCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "CANFD0_MCAN_HPMS,MCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List. Indicates the filter list of the matching filter element." "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1." bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'." group.long 0x98++0xB line.long 0x0 "CANFD0_MCAN_NDAT1,MCAN New Data 1" bitfld.long 0x0 31. "ND31,New Data RX Buffer 31" "0,1" bitfld.long 0x0 30. "ND30,New Data RX Buffer 30" "0,1" bitfld.long 0x0 29. "ND29,New Data RX Buffer 29" "0,1" bitfld.long 0x0 28. "ND28,New Data RX Buffer 28" "0,1" bitfld.long 0x0 27. "ND27,New Data RX Buffer 27" "0,1" newline bitfld.long 0x0 26. "ND26,New Data RX Buffer 26" "0,1" bitfld.long 0x0 25. "ND25,New Data RX Buffer 25" "0,1" bitfld.long 0x0 24. "ND24,New Data RX Buffer 24" "0,1" bitfld.long 0x0 23. "ND23,New Data RX Buffer 23" "0,1" bitfld.long 0x0 22. "ND22,New Data RX Buffer 22" "0,1" newline bitfld.long 0x0 21. "ND21,New Data RX Buffer 21" "0,1" bitfld.long 0x0 20. "ND20,New Data RX Buffer 20" "0,1" bitfld.long 0x0 19. "ND19,New Data RX Buffer 19" "0,1" bitfld.long 0x0 18. "ND18,New Data RX Buffer 18" "0,1" bitfld.long 0x0 17. "ND17,New Data RX Buffer 17" "0,1" newline bitfld.long 0x0 16. "ND16,New Data RX Buffer 16" "0,1" bitfld.long 0x0 15. "ND15,New Data RX Buffer 15" "0,1" bitfld.long 0x0 14. "ND14,New Data RX Buffer 14" "0,1" bitfld.long 0x0 13. "ND13,New Data RX Buffer 13" "0,1" bitfld.long 0x0 12. "ND12,New Data RX Buffer 12" "0,1" newline bitfld.long 0x0 11. "ND11,New Data RX Buffer 11" "0,1" bitfld.long 0x0 10. "ND10,New Data RX Buffer 10" "0,1" bitfld.long 0x0 9. "ND9,New Data RX Buffer 9" "0,1" bitfld.long 0x0 8. "ND8,New Data RX Buffer 8" "0,1" bitfld.long 0x0 7. "ND7,New Data RX Buffer 7" "0,1" newline bitfld.long 0x0 6. "ND6,New Data RX Buffer 6" "0,1" bitfld.long 0x0 5. "ND5,New Data RX Buffer 5" "0,1" bitfld.long 0x0 4. "ND4,New Data RX Buffer 4" "0,1" bitfld.long 0x0 3. "ND3,New Data RX Buffer 3" "0,1" bitfld.long 0x0 2. "ND2,New Data RX Buffer 2" "0,1" newline bitfld.long 0x0 1. "ND1,New Data RX Buffer 1" "0,1" bitfld.long 0x0 0. "ND0,New Data RX Buffer 0" "0,1" line.long 0x4 "CANFD0_MCAN_NDAT2,MCAN New Data 2" bitfld.long 0x4 31. "ND63,New Data RX Buffer 63" "0,1" bitfld.long 0x4 30. "ND62,New Data RX Buffer 62" "0,1" bitfld.long 0x4 29. "ND61,New Data RX Buffer 61" "0,1" bitfld.long 0x4 28. "ND60,New Data RX Buffer 60" "0,1" bitfld.long 0x4 27. "ND59,New Data RX Buffer 59" "0,1" newline bitfld.long 0x4 26. "ND58,New Data RX Buffer 58" "0,1" bitfld.long 0x4 25. "ND57,New Data RX Buffer 57" "0,1" bitfld.long 0x4 24. "ND56,New Data RX Buffer 56" "0,1" bitfld.long 0x4 23. "ND55,New Data RX Buffer 55" "0,1" bitfld.long 0x4 22. "ND54,New Data RX Buffer 54" "0,1" newline bitfld.long 0x4 21. "ND53,New Data RX Buffer 53" "0,1" bitfld.long 0x4 20. "ND52,New Data RX Buffer 52" "0,1" bitfld.long 0x4 19. "ND51,New Data RX Buffer 51" "0,1" bitfld.long 0x4 18. "ND50,New Data RX Buffer 50" "0,1" bitfld.long 0x4 17. "ND49,New Data RX Buffer 49" "0,1" newline bitfld.long 0x4 16. "ND48,New Data RX Buffer 48" "0,1" bitfld.long 0x4 15. "ND47,New Data RX Buffer 47" "0,1" bitfld.long 0x4 14. "ND46,New Data RX Buffer 46" "0,1" bitfld.long 0x4 13. "ND45,New Data RX Buffer 45" "0,1" bitfld.long 0x4 12. "ND44,New Data RX Buffer 44" "0,1" newline bitfld.long 0x4 11. "ND43,New Data RX Buffer 43" "0,1" bitfld.long 0x4 10. "ND42,New Data RX Buffer 42" "0,1" bitfld.long 0x4 9. "ND41,New Data RX Buffer 41" "0,1" bitfld.long 0x4 8. "ND40,New Data RX Buffer 40" "0,1" bitfld.long 0x4 7. "ND39,New Data RX Buffer 39" "0,1" newline bitfld.long 0x4 6. "ND38,New Data RX Buffer 38" "0,1" bitfld.long 0x4 5. "ND37,New Data RX Buffer 37" "0,1" bitfld.long 0x4 4. "ND36,New Data RX Buffer 36" "0,1" bitfld.long 0x4 3. "ND35,New Data RX Buffer 35" "0,1" bitfld.long 0x4 2. "ND34,New Data RX Buffer 34" "0,1" newline bitfld.long 0x4 1. "ND33,New Data RX Buffer 33" "0,1" bitfld.long 0x4 0. "ND32,New Data RX Buffer 32" "0,1" line.long 0x8 "CANFD0_MCAN_RXF0C,MCAN Rx FIFO 0 Configuration" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode." "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1." hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address)." rgroup.long 0xA4++0x3 line.long 0x0 "CANFD0_MCAN_RXF0S,MCAN Rx FIFO 0 Status" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset this bit is also reset." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer range 0 to 63." hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer range 0 to 63." hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "CANFD0_MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1.." line.long 0x4 "CANFD0_MCAN_RXBC,MCAN Rx Buffer Configuration" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address)." line.long 0x8 "CANFD0_MCAN_RXF1C,MCAN Rx FIFO 1 Configuration" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode." "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1." hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)." rgroup.long 0xB4++0x3 line.long 0x0 "CANFD0_MCAN_RXF1S,MCAN Rx FIFO 1 Status" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset this bit is also reset." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer range 0 to 63." hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer range 0 to 63." newline hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "CANFD0_MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1.." line.long 0x4 "CANFD0_MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "CANFD0_MCAN_TXBC,MCAN Tx Buffer Configuration" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address)." rgroup.long 0xC4++0x3 line.long 0x0 "CANFD0_MCAN_TXFQS,MCAN Tx FIFO / Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer range 0 to 31." hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index. Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1')." hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1')." group.long 0xC8++0x3 line.long 0x0 "CANFD0_MCAN_TXESC,MCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "CANFD0_MCAN_TXBRP,MCAN Tx Buffer Request Pending" bitfld.long 0x0 31. "TRP31,Transmission Request Pending 31. See description for bit 0." "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 30. See description for bit 0." "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 29. See description for bit 0." "0,1" bitfld.long 0x0 28. "TRP28,Transmission Request Pending 28. See description for bit 0." "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 27. See description for bit 0." "0,1" newline bitfld.long 0x0 26. "TRP26,Transmission Request Pending 26. See description for bit 0." "0,1" bitfld.long 0x0 25. "TRP25,Transmission Request Pending 25. See description for bit 0." "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending 24. See description for bit 0." "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 23. See description for bit 0." "0,1" bitfld.long 0x0 22. "TRP22,Transmission Request Pending 22. See description for bit 0." "0,1" newline bitfld.long 0x0 21. "TRP21,Transmission Request Pending 21. See description for bit 0." "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 20. See description for bit 0." "0,1" bitfld.long 0x0 19. "TRP19,Transmission Request Pending 19. See description for bit 0." "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 18. See description for bit 0." "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending 17. See description for bit 0." "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending 16. See description for bit 0." "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 15. See description for bit 0." "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 14. See description for bit 0." "0,1" bitfld.long 0x0 13. "TRP13,Transmission Request Pending 13. See description for bit 0." "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 12. See description for bit 0." "0,1" newline bitfld.long 0x0 11. "TRP11,Transmission Request Pending 11. See description for bit 0." "0,1" bitfld.long 0x0 10. "TRP10,Transmission Request Pending 10. See description for bit 0." "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 9. See description for bit 0." "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 8. See description for bit 0." "0,1" bitfld.long 0x0 7. "TRP7,Transmission Request Pending 7. See description for bit 0." "0,1" newline bitfld.long 0x0 6. "TRP6,Transmission Request Pending 6. See description for bit 0." "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 5. See description for bit 0." "0,1" bitfld.long 0x0 4. "TRP4,Transmission Request Pending 4. See description for bit 0." "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending 3. See description for bit 0." "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 2. See description for bit 0." "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending 1. See description for bit 0." "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0." "0,1" group.long 0xD0++0x7 line.long 0x0 "CANFD0_MCAN_TXBAR,MCAN Tx Buffer Add Request" bitfld.long 0x0 31. "AR31,Add Request 31. See description for bit 0." "0,1" bitfld.long 0x0 30. "AR30,Add Request 30. See description for bit 0." "0,1" bitfld.long 0x0 29. "AR29,Add Request 29. See description for bit 0." "0,1" bitfld.long 0x0 28. "AR28,Add Request 28. See description for bit 0." "0,1" bitfld.long 0x0 27. "AR27,Add Request 27. See description for bit 0." "0,1" newline bitfld.long 0x0 26. "AR26,Add Request 26. See description for bit 0." "0,1" bitfld.long 0x0 25. "AR25,Add Request 25. See description for bit 0." "0,1" bitfld.long 0x0 24. "AR24,Add Request 24. See description for bit 0." "0,1" bitfld.long 0x0 23. "AR23,Add Request 23. See description for bit 0." "0,1" bitfld.long 0x0 22. "AR22,Add Request 22. See description for bit 0." "0,1" newline bitfld.long 0x0 21. "AR21,Add Request 21. See description for bit 0." "0,1" bitfld.long 0x0 20. "AR20,Add Request 20. See description for bit 0." "0,1" bitfld.long 0x0 19. "AR19,Add Request 19. See description for bit 0." "0,1" bitfld.long 0x0 18. "AR18,Add Request 18. See description for bit 0." "0,1" bitfld.long 0x0 17. "AR17,Add Request 17. See description for bit 0." "0,1" newline bitfld.long 0x0 16. "AR16,Add Request 16. See description for bit 0." "0,1" bitfld.long 0x0 15. "AR15,Add Request 15. See description for bit 0." "0,1" bitfld.long 0x0 14. "AR14,Add Request 14. See description for bit 0." "0,1" bitfld.long 0x0 13. "AR13,Add Request 13. See description for bit 0." "0,1" bitfld.long 0x0 12. "AR12,Add Request 12. See description for bit 0." "0,1" newline bitfld.long 0x0 11. "AR11,Add Request 11. See description for bit 0." "0,1" bitfld.long 0x0 10. "AR10,Add Request 10. See description for bit 0." "0,1" bitfld.long 0x0 9. "AR9,Add Request 9. See description for bit 0." "0,1" bitfld.long 0x0 8. "AR8,Add Request 8. See description for bit 0." "0,1" bitfld.long 0x0 7. "AR7,Add Request 7. See description for bit 0." "0,1" newline bitfld.long 0x0 6. "AR6,Add Request 6. See description for bit 0." "0,1" bitfld.long 0x0 5. "AR5,Add Request 5. See description for bit 0." "0,1" bitfld.long 0x0 4. "AR4,Add Request 4. See description for bit 0." "0,1" bitfld.long 0x0 3. "AR3,Add Request 3. See description for bit 0." "0,1" bitfld.long 0x0 2. "AR2,Add Request 2. See description for bit 0." "0,1" newline bitfld.long 0x0 1. "AR1,Add Request 1. See description for bit 0." "0,1" bitfld.long 0x0 0. "AR0,Add Request 0." "0,1" line.long 0x4 "CANFD0_MCAN_TXBCR,MCAN Tx Buffer Cancellation Request" bitfld.long 0x4 31. "CR31,Cancellation Request 31. See description for bit 0." "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 30. See description for bit 0." "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 29. See description for bit 0." "0,1" bitfld.long 0x4 28. "CR28,Cancellation Request 28. See description for bit 0." "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 27. See description for bit 0." "0,1" newline bitfld.long 0x4 26. "CR26,Cancellation Request 26. See description for bit 0." "0,1" bitfld.long 0x4 25. "CR25,Cancellation Request 25. See description for bit 0." "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request 24. See description for bit 0." "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 23. See description for bit 0." "0,1" bitfld.long 0x4 22. "CR22,Cancellation Request 22. See description for bit 0." "0,1" newline bitfld.long 0x4 21. "CR21,Cancellation Request 21. See description for bit 0." "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 20. See description for bit 0." "0,1" bitfld.long 0x4 19. "CR19,Cancellation Request 19. See description for bit 0." "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 18. See description for bit 0." "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request 17. See description for bit 0." "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request 16. See description for bit 0." "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 15. See description for bit 0." "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 14. See description for bit 0." "0,1" bitfld.long 0x4 13. "CR13,Cancellation Request 13. See description for bit 0." "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 12. See description for bit 0." "0,1" newline bitfld.long 0x4 11. "CR11,Cancellation Request 11. See description for bit 0." "0,1" bitfld.long 0x4 10. "CR10,Cancellation Request 10. See description for bit 0." "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 9. See description for bit 0." "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 8. See description for bit 0." "0,1" bitfld.long 0x4 7. "CR7,Cancellation Request 7. See description for bit 0." "0,1" newline bitfld.long 0x4 6. "CR6,Cancellation Request 6. See description for bit 0." "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 5. See description for bit 0." "0,1" bitfld.long 0x4 4. "CR4,Cancellation Request 4. See description for bit 0." "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request 3. See description for bit 0." "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 2. See description for bit 0." "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request 1. See description for bit 0." "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0." "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "CANFD0_MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred" bitfld.long 0x0 31. "TO31,Transmission Occurred 31. See description for bit 0." "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 30. See description for bit 0." "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 29. See description for bit 0." "0,1" bitfld.long 0x0 28. "TO28,Transmission Occurred 28. See description for bit 0." "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 27. See description for bit 0." "0,1" newline bitfld.long 0x0 26. "TO26,Transmission Occurred 26. See description for bit 0." "0,1" bitfld.long 0x0 25. "TO25,Transmission Occurred 25. See description for bit 0." "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred 24. See description for bit 0." "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 23. See description for bit 0." "0,1" bitfld.long 0x0 22. "TO22,Transmission Occurred 22. See description for bit 0." "0,1" newline bitfld.long 0x0 21. "TO21,Transmission Occurred 21. See description for bit 0." "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 20. See description for bit 0." "0,1" bitfld.long 0x0 19. "TO19,Transmission Occurred 19. See description for bit 0." "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 18. See description for bit 0." "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred 17. See description for bit 0." "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred 16. See description for bit 0." "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 15. See description for bit 0." "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 14. See description for bit 0." "0,1" bitfld.long 0x0 13. "TO13,Transmission Occurred 13. See description for bit 0." "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 12. See description for bit 0." "0,1" newline bitfld.long 0x0 11. "TO11,Transmission Occurred 11. See description for bit 0." "0,1" bitfld.long 0x0 10. "TO10,Transmission Occurred 10. See description for bit 0." "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 9. See description for bit 0." "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 8. See description for bit 0." "0,1" bitfld.long 0x0 7. "TO7,Transmission Occurred 7. See description for bit 0." "0,1" newline bitfld.long 0x0 6. "TO6,Transmission Occurred 6. See description for bit 0." "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 5. See description for bit 0." "0,1" bitfld.long 0x0 4. "TO4,Transmission Occurred 4. See description for bit 0." "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred 3. See description for bit 0." "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 2. See description for bit 0." "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred 1. See description for bit 0." "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0." "0,1" line.long 0x4 "CANFD0_MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 31. "CF31,Cancellation Finished 31. See description for bit 0." "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 30. See description for bit 0." "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 29. See description for bit 0." "0,1" bitfld.long 0x4 28. "CF28,Cancellation Finished 28. See description for bit 0." "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 27. See description for bit 0." "0,1" newline bitfld.long 0x4 26. "CF26,Cancellation Finished 26. See description for bit 0." "0,1" bitfld.long 0x4 25. "CF25,Cancellation Finished 25. See description for bit 0." "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished 24. See description for bit 0." "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 23. See description for bit 0." "0,1" bitfld.long 0x4 22. "CF22,Cancellation Finished 22. See description for bit 0." "0,1" newline bitfld.long 0x4 21. "CF21,Cancellation Finished 21. See description for bit 0." "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 20. See description for bit 0." "0,1" bitfld.long 0x4 19. "CF19,Cancellation Finished 19. See description for bit 0." "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 18. See description for bit 0." "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished 17. See description for bit 0." "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished 16. See description for bit 0." "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 15. See description for bit 0." "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 14. See description for bit 0." "0,1" bitfld.long 0x4 13. "CF13,Cancellation Finished 13. See description for bit 0." "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 12. See description for bit 0." "0,1" newline bitfld.long 0x4 11. "CF11,Cancellation Finished 11. See description for bit 0." "0,1" bitfld.long 0x4 10. "CF10,Cancellation Finished 10. See description for bit 0." "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 9. See description for bit 0." "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 8. See description for bit 0." "0,1" bitfld.long 0x4 7. "CF7,Cancellation Finished 7. See description for bit 0." "0,1" newline bitfld.long 0x4 6. "CF6,Cancellation Finished 6. See description for bit 0." "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 5. See description for bit 0." "0,1" bitfld.long 0x4 4. "CF4,Cancellation Finished 4. See description for bit 0." "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished 3. See description for bit 0." "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 2. See description for bit 0." "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished 1. See description for bit 0." "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0." "0,1" group.long 0xE0++0x7 line.long 0x0 "CANFD0_MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" line.long 0x4 "CANFD0_MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" group.long 0xF0++0x3 line.long 0x0 "CANFD0_MCAN_TXEFC,MCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1." hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address)." rgroup.long 0xF4++0x3 line.long 0x0 "CANFD0_MCAN_TXEFS,MCAN Tx Event FIFO Status" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset this bit is also reset." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index.Tx Event FIFO write index pointer range 0 to 31." hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index. Tx Event FIFO read index pointer range 0 to 31." hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level. Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "CANFD0_MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to.." tree.end tree "CANFD0_TI_WRAPPER[%s]" base ad:0x4050F200 tree "CANFD0_MSP[%s]" base ad:0x4050F800 sif (cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "CANFD0_INT_EVENT0[%s]" base ad:0x4050F820 rgroup.long 0x0++0x3 line.long 0x0 "CANFD0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "CANFD0_IMASK,Interrupt mask" bitfld.long 0x0 5. "WAKEUP,Clock Stop Wake Up interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "DED,Massage RAM DED interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "SEC,Message RAM SEC interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INTL1,MCAN Interrupt Line 1 mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "INTL0,MCAN Interrupt Line 0 mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "CANFD0_RIS,Raw interrupt status" bitfld.long 0x0 5. "WAKEUP,Clock Stop Wake Up interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "DED,Message RAM DED interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "SEC,Message RAM SEC interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "INTL1,MCAN Interrupt Line 1." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "INTL0,MCAN Interrupt Line 0." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "CANFD0_MIS,Masked interrupt status" bitfld.long 0x0 5. "WAKEUP,Masked Clock Stop Wake Up interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Masked External Timestamp Counter Overflow interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "DED,Masked Message RAM DED interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "SEC,Masked Message RAM SEC interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "INTL1,Masked MCAN Interrupt Line 1." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "INTL0,Masked MCAN Interrupt Line 0." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "CANFD0_ISET,Interrupt set" bitfld.long 0x0 5. "WAKEUP,Set Clock Stop Wake Up interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Set External Timestamp Counter Overflow interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "DED,Set Message RAM DED interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "SEC,Set Message RAM SEC interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "INTL1,Set MCAN Interrupt Line 1." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "INTL0,Set MCAN Interrupt Line 0." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "CANFD0_ICLR,Interrupt clear" bitfld.long 0x0 5. "WAKEUP,Clear Clock Stop Wake Up interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Clear External Timestamp Counter Overflow interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "DED,Clear Message RAM DED interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "SEC,Clear Message RAM SEC interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "INTL1,Clear MCAN Interrupt Line 1." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "INTL0,Clear MCAN Interrupt Line 0." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end endif rgroup.long 0xE0++0x3 line.long 0x0 "CANFD0_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0xFC++0x3 line.long 0x0 "CANFD0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x100++0xB line.long 0x0 "CANFD0_MCANSS_CLKEN,MCAN module clock enable" bitfld.long 0x0 0. "CLK_REQEN,MCAN functional and MCAN/MCANSS MMR clock request enable bit" "0: MCAN module functional clock and Vbusp is not..,1: Setting this bit requests MCAN module functional.." line.long 0x4 "CANFD0_MCANSS_CLKDIV,Clock divider" sif (cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) bitfld.long 0x4 0.--1. "RATIO,Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS." "0: Divides input clock by 1,1: Divides input clock by 2,2: Divides input clock by 4,?" endif line.long 0x8 "CANFD0_MCANSS_CLKCTL,MCAN-SS clock stop control register" bitfld.long 0x8 8. "WKUP_GLTFLT_EN,Setting this bit enables the glitch filter on MCAN RXD input which wakes up the MCAN controller to exit clock gating." "0: Disable glitch filter enable on RXD input when..,1: Enable glitch filter enable on RXD input when.." newline bitfld.long 0x8 4. "WAKEUP_INT_EN,This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity)" "0: Disable MCAN IP clock stop wakeup interrupt,1: Enable MCAN IP clock stop wakeup interrupt" newline bitfld.long 0x8 0. "STOPREQ,This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request." "0: Disable MCAN-SS clock stop request,1: Enable MCAN-SS clock stop request" rgroup.long 0x10C++0x3 line.long 0x0 "CANFD0_MCANSS_CLKSTS,MCANSS clock stop status register" bitfld.long 0x0 8. "CCLKDONE,This bit indicates the status of MCAN contoller clock request from GPRCM." "0: MCAN controller clock is not available to the..,1: MCAN controller clock is enabled and available.." newline bitfld.long 0x0 4. "STOPREQ_HW_OVR,MCANSS clock stop HW override status bit." "0: MCANSS_CLKCTL.STOPREQ bit has not been cleared..,1: MCANSS_CLKCTL.STOPREQ bit has been cleared by HW." newline bitfld.long 0x0 0. "CLKSTOP_ACKSTS,Clock stop acknowledge status from MCAN IP" "0: No clock stop acknowledged.,1: MCAN-SS may be clock gated by stopping both the.." sif (cpuis("MSPM0G351*")) tree "CANFD0_CPU_INT[%s]" base ad:0x4050F820 rgroup.long 0x0++0x3 line.long 0x0 "CANFD0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "CANFD0_IMASK,Interrupt mask" bitfld.long 0x0 5. "WAKEUP,Clock Stop Wake Up interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "DED,Massage RAM DED interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "SEC,Message RAM SEC interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INTL1,MCAN Interrupt Line 1 mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "INTL0,MCAN Interrupt Line 0 mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "CANFD0_RIS,Raw interrupt status" bitfld.long 0x0 5. "WAKEUP,Clock Stop Wake Up interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "DED,Message RAM DED interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "SEC,Message RAM SEC interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "INTL1,MCAN Interrupt Line 1." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "INTL0,MCAN Interrupt Line 0." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "CANFD0_MIS,Masked interrupt status" bitfld.long 0x0 5. "WAKEUP,Masked Clock Stop Wake Up interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Masked External Timestamp Counter Overflow interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "DED,Masked Message RAM DED interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "SEC,Masked Message RAM SEC interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "INTL1,Masked MCAN Interrupt Line 1." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "INTL0,Masked MCAN Interrupt Line 0." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "CANFD0_ISET,Interrupt set" bitfld.long 0x0 5. "WAKEUP,Set Clock Stop Wake Up interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Set External Timestamp Counter Overflow interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "DED,Set Message RAM DED interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "SEC,Set Message RAM SEC interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "INTL1,Set MCAN Interrupt Line 1." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "INTL0,Set MCAN Interrupt Line 0." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "CANFD0_ICLR,Interrupt clear" bitfld.long 0x0 5. "WAKEUP,Clear Clock Stop Wake Up interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Clear External Timestamp Counter Overflow interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "DED,Clear Message RAM DED interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "SEC,Clear Message RAM SEC interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "INTL1,Clear MCAN Interrupt Line 1." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "INTL0,Clear MCAN Interrupt Line 0." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end endif tree.end base ad:0x4050F200 tree "CANFD0_PROCESSORS[%s]" tree "CANFD0_MCAN_ECC_REGS[%s]" base ad:0x4050F400 rgroup.long 0x0++0x3 line.long 0x0 "CANFD0_MCANERR_REV,MCAN Error Aggregator Revision Register" bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number" bitfld.long 0x0 8.--10. "REVMAJ,Major Revision of the Error Aggregator" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision of the Error Aggregator" group.long 0x8++0x3 line.long 0x0 "CANFD0_MCANERR_VECTOR,MCAN ECC Vector Register" rbitfld.long 0x0 24. "RD_SVBUS_DONE,Read Completion Flag" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address Offset" bitfld.long 0x0 15. "RD_SVBUS,Read Trigger" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator.." rgroup.long 0xC++0x7 line.long 0x0 "CANFD0_MCANERR_STAT,MCAN Error Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs. Number of ECC RAMs serviced by the aggregator." line.long 0x4 "CANFD0_MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register" bitfld.long 0x4 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module Identification Number" bitfld.long 0x4 8.--10. "REVMAJ,Major Revision of the Error Aggregator" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor Revision of the Error Aggregator" group.long 0x14++0xF line.long 0x0 "CANFD0_MCANERR_CTRL,MCAN ECC Control" bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,Enables Serial VBUS timeout mechanism" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled this error will be cleared the cycle following the read.." "0,1" bitfld.long 0x0 5. "FORCE_N_ROW,Enable single/double-bit error on the next RAM read regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode this applies to writes as well as reads." "0,1" bitfld.long 0x0 4. "FORCE_DED,Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit." "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to.." "0,1" bitfld.long 0x0 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1" bitfld.long 0x0 1. "ECC_CHECK,Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'." "0,1" bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC Generation" "0,1" line.long 0x4 "CANFD0_MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register" line.long 0x8 "CANFD0_MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Second column/data bit that needs to be flipped when FORCE_DED is set" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set" line.long 0xC "CANFD0_MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register" hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error." bitfld.long 0xC 15. "CLR_CTRL_REG_ERROR,Writing a '1' clears the CTRL_REG_ERROR bit" "0,1" bitfld.long 0xC 12. "CLR_ECC_OTHER,Writing a '1' clears the ECC_OTHER bit." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided." "0,1,2,3" newline bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided." "0,1,2,3" bitfld.long 0xC 7. "CTRL_REG_ERROR,Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to.." "0,1" bitfld.long 0xC 4. "ECC_OTHER,SEC While Writeback Error Status" "0,1" bitfld.long 0xC 2.--3. "ECC_DED,Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared." "0,1,2,3" newline bitfld.long 0xC 0.--1. "ECC_SEC,Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "CANFD0_MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register" group.long 0x28++0x3 line.long 0x0 "CANFD0_MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register" bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT,Write 1 to clear the Serial VBUS Timeout Flag" "0,1" bitfld.long 0x0 1. "SVBUS_TIMEOUT,Serial VBUS Timeout Flag. Write 1 to set." "0,1" rbitfld.long 0x0 0. "WB_PEND,Delayed Write Back Pending Status" "0,1" group.long 0x3C++0x3 line.long 0x0 "CANFD0_MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register" bitfld.long 0x0 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "CANFD0_MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register" bitfld.long 0x0 0. "MSGMEM_PEND,Message RAM SEC Interrupt Pending" "0,1" group.long 0x80++0x3 line.long 0x0 "CANFD0_MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0xC0++0x3 line.long 0x0 "CANFD0_MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0x13C++0x3 line.long 0x0 "CANFD0_MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register" bitfld.long 0x0 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "CANFD0_MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register" bitfld.long 0x0 0. "MSGMEM_PEND,Message RAM DED Interrupt Pending" "0,1" group.long 0x180++0x3 line.long 0x0 "CANFD0_MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0x1C0++0x3 line.long 0x0 "CANFD0_MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0x200++0xF line.long 0x0 "CANFD0_MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register" bitfld.long 0x0 1. "ENABLE_TIMEOUT_SET,Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value." "0,1" bitfld.long 0x0 0. "ENABLE_PARITY_SET,Write 1 to enable parity errors. Reads return the corresponding enable bit's current value." "0,1" line.long 0x4 "CANFD0_MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register" bitfld.long 0x4 1. "ENABLE_TIMEOUT_CLR,Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value." "0,1" bitfld.long 0x4 0. "ENABLE_PARITY_CLR,Write 1 to disable parity errors. Reads return the corresponding enable bit's current value." "0,1" line.long 0x8 "CANFD0_MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register" bitfld.long 0x8 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3" bitfld.long 0x8 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3" line.long 0xC "CANFD0_MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register" bitfld.long 0xC 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3" bitfld.long 0xC 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3" tree.end base ad:0x4050F200 tree "CANFD0_MCANSS_REGS[%s]" rgroup.long 0x0++0x3 line.long 0x0 "CANFD0_MCANSS_PID,MCAN Subsystem Revision Register" bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number" bitfld.long 0x0 8.--10. "MAJOR,Major Revision of the MCAN Subsystem" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision of the MCAN Subsystem" group.long 0x4++0x3 line.long 0x0 "CANFD0_MCANSS_CTRL,MCAN Subsystem Control Register" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable." "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit fully waking the MCAN up on an enabled wakeup request." "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity." "0,1" bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend Free Bit. Enables debug suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CANFD0_MCANSS_STAT,MCAN Subsystem Status Register" bitfld.long 0x0 2. "ENABLE_FDOE,Flexible Datarate Operation Enable. Determines whether CAN FD operation may be enabled via the MCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the MCAN." "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization Done." "0,1" bitfld.long 0x0 0. "RESET,Soft Reset Status." "0,1" group.long 0xC++0xF line.long 0x0 "CANFD0_MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0." "0,1" line.long 0x4 "CANFD0_MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit." "0,1" line.long 0x8 "CANFD0_MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0." "0,1" line.long 0xC "CANFD0_MCANSS_IE,MCAN Subsystem Interrupt Enable Register" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CANFD0_MCANSS_IES,MCAN Subsystem Interrupt Enable Status" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Status. To set use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit." "0,1" group.long 0x20++0x7 line.long 0x0 "CANFD0_MCANSS_EOI,MCAN Subsystem End of Interrupt" hexmask.long.byte 0x0 0.--7. 1. "EOI,End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1 another interrupt is generated." line.long 0x4 "CANFD0_MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001." rgroup.long 0x28++0x3 line.long 0x0 "CANFD0_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1 an MCANSS_EOI write of '1' to bit 0 will issue another interrupt." tree.end tree.end tree.end tree.end sif (cpuis("MSPM0G351*")) tree "CANFD1 (PERIPHERALREGION)" base ad:0x40510000 group.long 0x6800++0x3 line.long 0x0 "CANFD1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x6804++0x3 line.long 0x0 "CANFD1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x6814++0x3 line.long 0x0 "CANFD1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree "CANFD1_MCAN[%s]" base ad:0x40517000 rgroup.long 0x0++0x7 line.long 0x0 "CANFD1_MCAN_CREL,MCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release. One digit BCD-coded." hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release. One digit BCD-coded." hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release. One digit BCD-coded." newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year. One digit BCD-coded." hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month. Two digits BCD-coded." hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day. Two digits BCD-coded." line.long 0x4 "CANFD1_MCAN_ENDN,MCAN Endian Register" group.long 0xC++0x23 line.long 0x0 "CANFD1_MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual.." hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." line.long 0x4 "CANFD1_MCAN_TEST,MCAN Test Register" rbitfld.long 0x4 7. "RX,Receive Pin. Monitors the actual value of the CAN receive pin." "0: The CAN bus is dominant (CAN RX pin = '0'),1: The CAN bus is recessive (CAN RX pin = '1')" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back Mode. Qualified Write is possible only with CCCR.CCE='1' and CCCR.INIT='1'." "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled" line.long 0x8 "CANFD1_MCAN_RWD,MCAN RAM Watchdog" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value. Acutal Message RAM Watchdog Counter Value." hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled." line.long 0xC "CANFD1_MCAN_CCCR,MCAN CC Control Register" bitfld.long 0xC 15. "NISO,Non ISO Operation. If this bit is set the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0." "0,1" bitfld.long 0xC 14. "TXP,Transmit Pause. If this bit is set the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame." "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0,1" newline bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1" bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0xC 8. "FDOE,Flexible Datarate Operation Enable" "0,1" newline bitfld.long 0xC 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time." "0,1" newline bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time." "0,1" newline bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1" bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "CANFD1_MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual.." hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used." line.long 0x14 "CANFD1_MCAN_TSCC,MCAN Timestamp Counter Configuration" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here.." bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "CANFD1_MCAN_TSCV,MCAN Timestamp Counter Value" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01" the Timestamp Counter is incremented in multiples of CAN bit times (1...16) depending on the.." line.long 0x1C "CANFD1_MCAN_TOCC,MCAN Timeout Counter Configuration" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period." bitfld.long 0x1C 1.--2. "TOS,Timeout Select. When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO presets the counter to.." "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "CANFD1_MCAN_TOCV,MCAN Timeout Counter Value" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times (1...16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and.." rgroup.long 0x40++0x7 line.long 0x0 "CANFD1_MCAN_ECR,MCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of.." bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter. Actual state of the Receive Error Counter values between 0 and 127." newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter. Actual state of the Transmit Error Counter values between 0 and 255." line.long 0x4 "CANFD1_MCAN_PSR,MCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value. Position of the secondary sample point defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is in the data phase the number of.." bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Received a CAN FD Message. This bit is set independent of acceptance filtering." "0,1" newline bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF independent of acceptance filtering." "0,1" bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF independent of acceptance filtering." "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Node Activity. Monitors the module's CAN communication state." "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error." "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x0 "CANFD1_MCAN_TDCR,MCAN Transmitter Delay Compensation Register" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq." hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature.." group.long 0x50++0xF line.long 0x0 "CANFD1_MCAN_IR,MCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0,1" newline bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x0 21. "BEU,Bit Error Uncorrected. Message RAM bit error detected uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is done to.." "0,1" newline bitfld.long 0x0 19. "DRX,Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure. The flag is set when the Rx Handler:" "0,1" newline bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1" newline bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "CANFD1_MCAN_IE,MCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1" newline bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" newline bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow Enable" "0,1" bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Enable" "0,1" newline bitfld.long 0x4 20. "BECE,Bit Error Corrected Enable" "0,1" bitfld.long 0x4 19. "DRXE,Message Stored to Dedicated Rx Buffer Enable" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" newline bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Enable" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Enable" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost Enable" "0,1" newline bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Enable" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Enable" "0,1" newline bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Enable" "0,1" bitfld.long 0x4 9. "TCE,Transmission Completed Enable" "0,1" newline bitfld.long 0x4 8. "HPME,High Priority Message Enable" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Enable" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Enable" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Enable" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Enable" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Enable" "0,1" newline bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Enable" "0,1" line.long 0x8 "CANFD1_MCAN_ILS,MCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1" newline bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status Line" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Line" "0,1" newline bitfld.long 0x8 23. "EPL,Error Passive Line" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Line" "0,1" bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Line" "0,1" newline bitfld.long 0x8 20. "BECL,Bit Error Corrected Line" "0,1" bitfld.long 0x8 19. "DRXL,Message Stored to Dedicated Rx Buffer Line" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Line" "0,1" newline bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Line" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Line" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Line" "0,1" newline bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Line" "0,1" bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Line" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Line" "0,1" newline bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Line" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Line" "0,1" bitfld.long 0x8 9. "TCL,Transmission Completed Line" "0,1" newline bitfld.long 0x8 8. "HPML,High Priority Message Line" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Line" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Line" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Line" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Line" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Line" "0,1" newline bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Line" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Line" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Line" "0,1" line.long 0xC "CANFD1_MCAN_ILE,MCAN Interrupt Line Enable" bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "CANFD1_MCAN_GFC,MCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated." "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated." "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0,1" newline bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0,1" line.long 0x4 "CANFD1_MCAN_SIDFC,MCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address)." line.long 0x8 "CANFD1_MCAN_XIDFC,MCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--22. 1. "LSE,Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address)." hexmask.long.word 0x8 2.--15. 1. "FLESA,List Size Extended" group.long 0x90++0x3 line.long 0x0 "CANFD1_MCAN_XIDAM,MCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not.." rgroup.long 0x94++0x3 line.long 0x0 "CANFD1_MCAN_HPMS,MCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List. Indicates the filter list of the matching filter element." "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1." bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'." group.long 0x98++0xB line.long 0x0 "CANFD1_MCAN_NDAT1,MCAN New Data 1" bitfld.long 0x0 31. "ND31,New Data RX Buffer 31" "0,1" bitfld.long 0x0 30. "ND30,New Data RX Buffer 30" "0,1" bitfld.long 0x0 29. "ND29,New Data RX Buffer 29" "0,1" newline bitfld.long 0x0 28. "ND28,New Data RX Buffer 28" "0,1" bitfld.long 0x0 27. "ND27,New Data RX Buffer 27" "0,1" bitfld.long 0x0 26. "ND26,New Data RX Buffer 26" "0,1" newline bitfld.long 0x0 25. "ND25,New Data RX Buffer 25" "0,1" bitfld.long 0x0 24. "ND24,New Data RX Buffer 24" "0,1" bitfld.long 0x0 23. "ND23,New Data RX Buffer 23" "0,1" newline bitfld.long 0x0 22. "ND22,New Data RX Buffer 22" "0,1" bitfld.long 0x0 21. "ND21,New Data RX Buffer 21" "0,1" bitfld.long 0x0 20. "ND20,New Data RX Buffer 20" "0,1" newline bitfld.long 0x0 19. "ND19,New Data RX Buffer 19" "0,1" bitfld.long 0x0 18. "ND18,New Data RX Buffer 18" "0,1" bitfld.long 0x0 17. "ND17,New Data RX Buffer 17" "0,1" newline bitfld.long 0x0 16. "ND16,New Data RX Buffer 16" "0,1" bitfld.long 0x0 15. "ND15,New Data RX Buffer 15" "0,1" bitfld.long 0x0 14. "ND14,New Data RX Buffer 14" "0,1" newline bitfld.long 0x0 13. "ND13,New Data RX Buffer 13" "0,1" bitfld.long 0x0 12. "ND12,New Data RX Buffer 12" "0,1" bitfld.long 0x0 11. "ND11,New Data RX Buffer 11" "0,1" newline bitfld.long 0x0 10. "ND10,New Data RX Buffer 10" "0,1" bitfld.long 0x0 9. "ND9,New Data RX Buffer 9" "0,1" bitfld.long 0x0 8. "ND8,New Data RX Buffer 8" "0,1" newline bitfld.long 0x0 7. "ND7,New Data RX Buffer 7" "0,1" bitfld.long 0x0 6. "ND6,New Data RX Buffer 6" "0,1" bitfld.long 0x0 5. "ND5,New Data RX Buffer 5" "0,1" newline bitfld.long 0x0 4. "ND4,New Data RX Buffer 4" "0,1" bitfld.long 0x0 3. "ND3,New Data RX Buffer 3" "0,1" bitfld.long 0x0 2. "ND2,New Data RX Buffer 2" "0,1" newline bitfld.long 0x0 1. "ND1,New Data RX Buffer 1" "0,1" bitfld.long 0x0 0. "ND0,New Data RX Buffer 0" "0,1" line.long 0x4 "CANFD1_MCAN_NDAT2,MCAN New Data 2" bitfld.long 0x4 31. "ND63,New Data RX Buffer 63" "0,1" bitfld.long 0x4 30. "ND62,New Data RX Buffer 62" "0,1" bitfld.long 0x4 29. "ND61,New Data RX Buffer 61" "0,1" newline bitfld.long 0x4 28. "ND60,New Data RX Buffer 60" "0,1" bitfld.long 0x4 27. "ND59,New Data RX Buffer 59" "0,1" bitfld.long 0x4 26. "ND58,New Data RX Buffer 58" "0,1" newline bitfld.long 0x4 25. "ND57,New Data RX Buffer 57" "0,1" bitfld.long 0x4 24. "ND56,New Data RX Buffer 56" "0,1" bitfld.long 0x4 23. "ND55,New Data RX Buffer 55" "0,1" newline bitfld.long 0x4 22. "ND54,New Data RX Buffer 54" "0,1" bitfld.long 0x4 21. "ND53,New Data RX Buffer 53" "0,1" bitfld.long 0x4 20. "ND52,New Data RX Buffer 52" "0,1" newline bitfld.long 0x4 19. "ND51,New Data RX Buffer 51" "0,1" bitfld.long 0x4 18. "ND50,New Data RX Buffer 50" "0,1" bitfld.long 0x4 17. "ND49,New Data RX Buffer 49" "0,1" newline bitfld.long 0x4 16. "ND48,New Data RX Buffer 48" "0,1" bitfld.long 0x4 15. "ND47,New Data RX Buffer 47" "0,1" bitfld.long 0x4 14. "ND46,New Data RX Buffer 46" "0,1" newline bitfld.long 0x4 13. "ND45,New Data RX Buffer 45" "0,1" bitfld.long 0x4 12. "ND44,New Data RX Buffer 44" "0,1" bitfld.long 0x4 11. "ND43,New Data RX Buffer 43" "0,1" newline bitfld.long 0x4 10. "ND42,New Data RX Buffer 42" "0,1" bitfld.long 0x4 9. "ND41,New Data RX Buffer 41" "0,1" bitfld.long 0x4 8. "ND40,New Data RX Buffer 40" "0,1" newline bitfld.long 0x4 7. "ND39,New Data RX Buffer 39" "0,1" bitfld.long 0x4 6. "ND38,New Data RX Buffer 38" "0,1" bitfld.long 0x4 5. "ND37,New Data RX Buffer 37" "0,1" newline bitfld.long 0x4 4. "ND36,New Data RX Buffer 36" "0,1" bitfld.long 0x4 3. "ND35,New Data RX Buffer 35" "0,1" bitfld.long 0x4 2. "ND34,New Data RX Buffer 34" "0,1" newline bitfld.long 0x4 1. "ND33,New Data RX Buffer 33" "0,1" bitfld.long 0x4 0. "ND32,New Data RX Buffer 32" "0,1" line.long 0x8 "CANFD1_MCAN_RXF0C,MCAN Rx FIFO 0 Configuration" bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode." "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1." newline hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address)." rgroup.long 0xA4++0x3 line.long 0x0 "CANFD1_MCAN_RXF0S,MCAN Rx FIFO 0 Status" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset this bit is also reset." "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer range 0 to 63." newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer range 0 to 63." hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0 range 0 to 64." group.long 0xA8++0xB line.long 0x0 "CANFD1_MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1.." line.long 0x4 "CANFD1_MCAN_RXBC,MCAN Rx Buffer Configuration" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address)." line.long 0x8 "CANFD1_MCAN_RXF1C,MCAN Rx FIFO 1 Configuration" bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode." "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1." newline hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)." rgroup.long 0xB4++0x3 line.long 0x0 "CANFD1_MCAN_RXF1S,MCAN Rx FIFO 1 Status" bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset this bit is also reset." "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer range 0 to 63." hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer range 0 to 63." hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1 range 0 to 64." group.long 0xB8++0xB line.long 0x0 "CANFD1_MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1.." line.long 0x4 "CANFD1_MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" line.long 0x8 "CANFD1_MCAN_TXBC,MCAN Tx Buffer Configuration" bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address)." rgroup.long 0xC4++0x3 line.long 0x0 "CANFD1_MCAN_TXFQS,MCAN Tx FIFO / Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQP,Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer range 0 to 31." hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index. Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1')." newline hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1')." group.long 0xC8++0x3 line.long 0x0 "CANFD1_MCAN_TXESC,MCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "CANFD1_MCAN_TXBRP,MCAN Tx Buffer Request Pending" bitfld.long 0x0 31. "TRP31,Transmission Request Pending 31. See description for bit 0." "0,1" bitfld.long 0x0 30. "TRP30,Transmission Request Pending 30. See description for bit 0." "0,1" bitfld.long 0x0 29. "TRP29,Transmission Request Pending 29. See description for bit 0." "0,1" newline bitfld.long 0x0 28. "TRP28,Transmission Request Pending 28. See description for bit 0." "0,1" bitfld.long 0x0 27. "TRP27,Transmission Request Pending 27. See description for bit 0." "0,1" bitfld.long 0x0 26. "TRP26,Transmission Request Pending 26. See description for bit 0." "0,1" newline bitfld.long 0x0 25. "TRP25,Transmission Request Pending 25. See description for bit 0." "0,1" bitfld.long 0x0 24. "TRP24,Transmission Request Pending 24. See description for bit 0." "0,1" bitfld.long 0x0 23. "TRP23,Transmission Request Pending 23. See description for bit 0." "0,1" newline bitfld.long 0x0 22. "TRP22,Transmission Request Pending 22. See description for bit 0." "0,1" bitfld.long 0x0 21. "TRP21,Transmission Request Pending 21. See description for bit 0." "0,1" bitfld.long 0x0 20. "TRP20,Transmission Request Pending 20. See description for bit 0." "0,1" newline bitfld.long 0x0 19. "TRP19,Transmission Request Pending 19. See description for bit 0." "0,1" bitfld.long 0x0 18. "TRP18,Transmission Request Pending 18. See description for bit 0." "0,1" bitfld.long 0x0 17. "TRP17,Transmission Request Pending 17. See description for bit 0." "0,1" newline bitfld.long 0x0 16. "TRP16,Transmission Request Pending 16. See description for bit 0." "0,1" bitfld.long 0x0 15. "TRP15,Transmission Request Pending 15. See description for bit 0." "0,1" bitfld.long 0x0 14. "TRP14,Transmission Request Pending 14. See description for bit 0." "0,1" newline bitfld.long 0x0 13. "TRP13,Transmission Request Pending 13. See description for bit 0." "0,1" bitfld.long 0x0 12. "TRP12,Transmission Request Pending 12. See description for bit 0." "0,1" bitfld.long 0x0 11. "TRP11,Transmission Request Pending 11. See description for bit 0." "0,1" newline bitfld.long 0x0 10. "TRP10,Transmission Request Pending 10. See description for bit 0." "0,1" bitfld.long 0x0 9. "TRP9,Transmission Request Pending 9. See description for bit 0." "0,1" bitfld.long 0x0 8. "TRP8,Transmission Request Pending 8. See description for bit 0." "0,1" newline bitfld.long 0x0 7. "TRP7,Transmission Request Pending 7. See description for bit 0." "0,1" bitfld.long 0x0 6. "TRP6,Transmission Request Pending 6. See description for bit 0." "0,1" bitfld.long 0x0 5. "TRP5,Transmission Request Pending 5. See description for bit 0." "0,1" newline bitfld.long 0x0 4. "TRP4,Transmission Request Pending 4. See description for bit 0." "0,1" bitfld.long 0x0 3. "TRP3,Transmission Request Pending 3. See description for bit 0." "0,1" bitfld.long 0x0 2. "TRP2,Transmission Request Pending 2. See description for bit 0." "0,1" newline bitfld.long 0x0 1. "TRP1,Transmission Request Pending 1. See description for bit 0." "0,1" bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0." "0,1" group.long 0xD0++0x7 line.long 0x0 "CANFD1_MCAN_TXBAR,MCAN Tx Buffer Add Request" bitfld.long 0x0 31. "AR31,Add Request 31. See description for bit 0." "0,1" bitfld.long 0x0 30. "AR30,Add Request 30. See description for bit 0." "0,1" bitfld.long 0x0 29. "AR29,Add Request 29. See description for bit 0." "0,1" newline bitfld.long 0x0 28. "AR28,Add Request 28. See description for bit 0." "0,1" bitfld.long 0x0 27. "AR27,Add Request 27. See description for bit 0." "0,1" bitfld.long 0x0 26. "AR26,Add Request 26. See description for bit 0." "0,1" newline bitfld.long 0x0 25. "AR25,Add Request 25. See description for bit 0." "0,1" bitfld.long 0x0 24. "AR24,Add Request 24. See description for bit 0." "0,1" bitfld.long 0x0 23. "AR23,Add Request 23. See description for bit 0." "0,1" newline bitfld.long 0x0 22. "AR22,Add Request 22. See description for bit 0." "0,1" bitfld.long 0x0 21. "AR21,Add Request 21. See description for bit 0." "0,1" bitfld.long 0x0 20. "AR20,Add Request 20. See description for bit 0." "0,1" newline bitfld.long 0x0 19. "AR19,Add Request 19. See description for bit 0." "0,1" bitfld.long 0x0 18. "AR18,Add Request 18. See description for bit 0." "0,1" bitfld.long 0x0 17. "AR17,Add Request 17. See description for bit 0." "0,1" newline bitfld.long 0x0 16. "AR16,Add Request 16. See description for bit 0." "0,1" bitfld.long 0x0 15. "AR15,Add Request 15. See description for bit 0." "0,1" bitfld.long 0x0 14. "AR14,Add Request 14. See description for bit 0." "0,1" newline bitfld.long 0x0 13. "AR13,Add Request 13. See description for bit 0." "0,1" bitfld.long 0x0 12. "AR12,Add Request 12. See description for bit 0." "0,1" bitfld.long 0x0 11. "AR11,Add Request 11. See description for bit 0." "0,1" newline bitfld.long 0x0 10. "AR10,Add Request 10. See description for bit 0." "0,1" bitfld.long 0x0 9. "AR9,Add Request 9. See description for bit 0." "0,1" bitfld.long 0x0 8. "AR8,Add Request 8. See description for bit 0." "0,1" newline bitfld.long 0x0 7. "AR7,Add Request 7. See description for bit 0." "0,1" bitfld.long 0x0 6. "AR6,Add Request 6. See description for bit 0." "0,1" bitfld.long 0x0 5. "AR5,Add Request 5. See description for bit 0." "0,1" newline bitfld.long 0x0 4. "AR4,Add Request 4. See description for bit 0." "0,1" bitfld.long 0x0 3. "AR3,Add Request 3. See description for bit 0." "0,1" bitfld.long 0x0 2. "AR2,Add Request 2. See description for bit 0." "0,1" newline bitfld.long 0x0 1. "AR1,Add Request 1. See description for bit 0." "0,1" bitfld.long 0x0 0. "AR0,Add Request 0." "0,1" line.long 0x4 "CANFD1_MCAN_TXBCR,MCAN Tx Buffer Cancellation Request" bitfld.long 0x4 31. "CR31,Cancellation Request 31. See description for bit 0." "0,1" bitfld.long 0x4 30. "CR30,Cancellation Request 30. See description for bit 0." "0,1" bitfld.long 0x4 29. "CR29,Cancellation Request 29. See description for bit 0." "0,1" newline bitfld.long 0x4 28. "CR28,Cancellation Request 28. See description for bit 0." "0,1" bitfld.long 0x4 27. "CR27,Cancellation Request 27. See description for bit 0." "0,1" bitfld.long 0x4 26. "CR26,Cancellation Request 26. See description for bit 0." "0,1" newline bitfld.long 0x4 25. "CR25,Cancellation Request 25. See description for bit 0." "0,1" bitfld.long 0x4 24. "CR24,Cancellation Request 24. See description for bit 0." "0,1" bitfld.long 0x4 23. "CR23,Cancellation Request 23. See description for bit 0." "0,1" newline bitfld.long 0x4 22. "CR22,Cancellation Request 22. See description for bit 0." "0,1" bitfld.long 0x4 21. "CR21,Cancellation Request 21. See description for bit 0." "0,1" bitfld.long 0x4 20. "CR20,Cancellation Request 20. See description for bit 0." "0,1" newline bitfld.long 0x4 19. "CR19,Cancellation Request 19. See description for bit 0." "0,1" bitfld.long 0x4 18. "CR18,Cancellation Request 18. See description for bit 0." "0,1" bitfld.long 0x4 17. "CR17,Cancellation Request 17. See description for bit 0." "0,1" newline bitfld.long 0x4 16. "CR16,Cancellation Request 16. See description for bit 0." "0,1" bitfld.long 0x4 15. "CR15,Cancellation Request 15. See description for bit 0." "0,1" bitfld.long 0x4 14. "CR14,Cancellation Request 14. See description for bit 0." "0,1" newline bitfld.long 0x4 13. "CR13,Cancellation Request 13. See description for bit 0." "0,1" bitfld.long 0x4 12. "CR12,Cancellation Request 12. See description for bit 0." "0,1" bitfld.long 0x4 11. "CR11,Cancellation Request 11. See description for bit 0." "0,1" newline bitfld.long 0x4 10. "CR10,Cancellation Request 10. See description for bit 0." "0,1" bitfld.long 0x4 9. "CR9,Cancellation Request 9. See description for bit 0." "0,1" bitfld.long 0x4 8. "CR8,Cancellation Request 8. See description for bit 0." "0,1" newline bitfld.long 0x4 7. "CR7,Cancellation Request 7. See description for bit 0." "0,1" bitfld.long 0x4 6. "CR6,Cancellation Request 6. See description for bit 0." "0,1" bitfld.long 0x4 5. "CR5,Cancellation Request 5. See description for bit 0." "0,1" newline bitfld.long 0x4 4. "CR4,Cancellation Request 4. See description for bit 0." "0,1" bitfld.long 0x4 3. "CR3,Cancellation Request 3. See description for bit 0." "0,1" bitfld.long 0x4 2. "CR2,Cancellation Request 2. See description for bit 0." "0,1" newline bitfld.long 0x4 1. "CR1,Cancellation Request 1. See description for bit 0." "0,1" bitfld.long 0x4 0. "CR0,Cancellation Request 0." "0,1" rgroup.long 0xD8++0x7 line.long 0x0 "CANFD1_MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred" bitfld.long 0x0 31. "TO31,Transmission Occurred 31. See description for bit 0." "0,1" bitfld.long 0x0 30. "TO30,Transmission Occurred 30. See description for bit 0." "0,1" bitfld.long 0x0 29. "TO29,Transmission Occurred 29. See description for bit 0." "0,1" newline bitfld.long 0x0 28. "TO28,Transmission Occurred 28. See description for bit 0." "0,1" bitfld.long 0x0 27. "TO27,Transmission Occurred 27. See description for bit 0." "0,1" bitfld.long 0x0 26. "TO26,Transmission Occurred 26. See description for bit 0." "0,1" newline bitfld.long 0x0 25. "TO25,Transmission Occurred 25. See description for bit 0." "0,1" bitfld.long 0x0 24. "TO24,Transmission Occurred 24. See description for bit 0." "0,1" bitfld.long 0x0 23. "TO23,Transmission Occurred 23. See description for bit 0." "0,1" newline bitfld.long 0x0 22. "TO22,Transmission Occurred 22. See description for bit 0." "0,1" bitfld.long 0x0 21. "TO21,Transmission Occurred 21. See description for bit 0." "0,1" bitfld.long 0x0 20. "TO20,Transmission Occurred 20. See description for bit 0." "0,1" newline bitfld.long 0x0 19. "TO19,Transmission Occurred 19. See description for bit 0." "0,1" bitfld.long 0x0 18. "TO18,Transmission Occurred 18. See description for bit 0." "0,1" bitfld.long 0x0 17. "TO17,Transmission Occurred 17. See description for bit 0." "0,1" newline bitfld.long 0x0 16. "TO16,Transmission Occurred 16. See description for bit 0." "0,1" bitfld.long 0x0 15. "TO15,Transmission Occurred 15. See description for bit 0." "0,1" bitfld.long 0x0 14. "TO14,Transmission Occurred 14. See description for bit 0." "0,1" newline bitfld.long 0x0 13. "TO13,Transmission Occurred 13. See description for bit 0." "0,1" bitfld.long 0x0 12. "TO12,Transmission Occurred 12. See description for bit 0." "0,1" bitfld.long 0x0 11. "TO11,Transmission Occurred 11. See description for bit 0." "0,1" newline bitfld.long 0x0 10. "TO10,Transmission Occurred 10. See description for bit 0." "0,1" bitfld.long 0x0 9. "TO9,Transmission Occurred 9. See description for bit 0." "0,1" bitfld.long 0x0 8. "TO8,Transmission Occurred 8. See description for bit 0." "0,1" newline bitfld.long 0x0 7. "TO7,Transmission Occurred 7. See description for bit 0." "0,1" bitfld.long 0x0 6. "TO6,Transmission Occurred 6. See description for bit 0." "0,1" bitfld.long 0x0 5. "TO5,Transmission Occurred 5. See description for bit 0." "0,1" newline bitfld.long 0x0 4. "TO4,Transmission Occurred 4. See description for bit 0." "0,1" bitfld.long 0x0 3. "TO3,Transmission Occurred 3. See description for bit 0." "0,1" bitfld.long 0x0 2. "TO2,Transmission Occurred 2. See description for bit 0." "0,1" newline bitfld.long 0x0 1. "TO1,Transmission Occurred 1. See description for bit 0." "0,1" bitfld.long 0x0 0. "TO0,Transmission Occurred 0." "0,1" line.long 0x4 "CANFD1_MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished" bitfld.long 0x4 31. "CF31,Cancellation Finished 31. See description for bit 0." "0,1" bitfld.long 0x4 30. "CF30,Cancellation Finished 30. See description for bit 0." "0,1" bitfld.long 0x4 29. "CF29,Cancellation Finished 29. See description for bit 0." "0,1" newline bitfld.long 0x4 28. "CF28,Cancellation Finished 28. See description for bit 0." "0,1" bitfld.long 0x4 27. "CF27,Cancellation Finished 27. See description for bit 0." "0,1" bitfld.long 0x4 26. "CF26,Cancellation Finished 26. See description for bit 0." "0,1" newline bitfld.long 0x4 25. "CF25,Cancellation Finished 25. See description for bit 0." "0,1" bitfld.long 0x4 24. "CF24,Cancellation Finished 24. See description for bit 0." "0,1" bitfld.long 0x4 23. "CF23,Cancellation Finished 23. See description for bit 0." "0,1" newline bitfld.long 0x4 22. "CF22,Cancellation Finished 22. See description for bit 0." "0,1" bitfld.long 0x4 21. "CF21,Cancellation Finished 21. See description for bit 0." "0,1" bitfld.long 0x4 20. "CF20,Cancellation Finished 20. See description for bit 0." "0,1" newline bitfld.long 0x4 19. "CF19,Cancellation Finished 19. See description for bit 0." "0,1" bitfld.long 0x4 18. "CF18,Cancellation Finished 18. See description for bit 0." "0,1" bitfld.long 0x4 17. "CF17,Cancellation Finished 17. See description for bit 0." "0,1" newline bitfld.long 0x4 16. "CF16,Cancellation Finished 16. See description for bit 0." "0,1" bitfld.long 0x4 15. "CF15,Cancellation Finished 15. See description for bit 0." "0,1" bitfld.long 0x4 14. "CF14,Cancellation Finished 14. See description for bit 0." "0,1" newline bitfld.long 0x4 13. "CF13,Cancellation Finished 13. See description for bit 0." "0,1" bitfld.long 0x4 12. "CF12,Cancellation Finished 12. See description for bit 0." "0,1" bitfld.long 0x4 11. "CF11,Cancellation Finished 11. See description for bit 0." "0,1" newline bitfld.long 0x4 10. "CF10,Cancellation Finished 10. See description for bit 0." "0,1" bitfld.long 0x4 9. "CF9,Cancellation Finished 9. See description for bit 0." "0,1" bitfld.long 0x4 8. "CF8,Cancellation Finished 8. See description for bit 0." "0,1" newline bitfld.long 0x4 7. "CF7,Cancellation Finished 7. See description for bit 0." "0,1" bitfld.long 0x4 6. "CF6,Cancellation Finished 6. See description for bit 0." "0,1" bitfld.long 0x4 5. "CF5,Cancellation Finished 5. See description for bit 0." "0,1" newline bitfld.long 0x4 4. "CF4,Cancellation Finished 4. See description for bit 0." "0,1" bitfld.long 0x4 3. "CF3,Cancellation Finished 3. See description for bit 0." "0,1" bitfld.long 0x4 2. "CF2,Cancellation Finished 2. See description for bit 0." "0,1" newline bitfld.long 0x4 1. "CF1,Cancellation Finished 1. See description for bit 0." "0,1" bitfld.long 0x4 0. "CF0,Cancellation Finished 0." "0,1" group.long 0xE0++0x7 line.long 0x0 "CANFD1_MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable" bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" newline bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1" line.long 0x4 "CANFD1_MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable" bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" newline bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1" group.long 0xF0++0x3 line.long 0x0 "CANFD1_MCAN_TXEFC,MCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1." hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address)." rgroup.long 0xF4++0x3 line.long 0x0 "CANFD1_MCAN_TXEFS,MCAN Tx Event FIFO Status" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset this bit is also reset." "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index.Tx Event FIFO write index pointer range 0 to 31." newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index. Tx Event FIFO read index pointer range 0 to 31." hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level. Number of elements stored in Tx Event FIFO range 0 to 32." group.long 0xF8++0x3 line.long 0x0 "CANFD1_MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to.." tree.end tree "CANFD1_TI_WRAPPER[%s]" base ad:0x40517200 tree "CANFD1_MSP[%s]" base ad:0x40517800 tree "CANFD1_CPU_INT[%s]" base ad:0x40517820 rgroup.long 0x0++0x3 line.long 0x0 "CANFD1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "CANFD1_IMASK,Interrupt mask" bitfld.long 0x0 5. "WAKEUP,Clock Stop Wake Up interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "DED,Massage RAM DED interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "SEC,Message RAM SEC interrupt mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "INTL1,MCAN Interrupt Line 1 mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "INTL0,MCAN Interrupt Line 0 mask." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "CANFD1_RIS,Raw interrupt status" bitfld.long 0x0 5. "WAKEUP,Clock Stop Wake Up interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "DED,Message RAM DED interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "SEC,Message RAM SEC interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "INTL1,MCAN Interrupt Line 1." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "INTL0,MCAN Interrupt Line 0." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "CANFD1_MIS,Masked interrupt status" bitfld.long 0x0 5. "WAKEUP,Masked Clock Stop Wake Up interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Masked External Timestamp Counter Overflow interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "DED,Masked Message RAM DED interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "SEC,Masked Message RAM SEC interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "INTL1,Masked MCAN Interrupt Line 1." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "INTL0,Masked MCAN Interrupt Line 0." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "CANFD1_ISET,Interrupt set" bitfld.long 0x0 5. "WAKEUP,Set Clock Stop Wake Up interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Set External Timestamp Counter Overflow interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "DED,Set Message RAM DED interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "SEC,Set Message RAM SEC interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "INTL1,Set MCAN Interrupt Line 1." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "INTL0,Set MCAN Interrupt Line 0." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "CANFD1_ICLR,Interrupt clear" bitfld.long 0x0 5. "WAKEUP,Clear Clock Stop Wake Up interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "EXT_TS_CNTR_OVFL,Clear External Timestamp Counter Overflow interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "DED,Clear Message RAM DED interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "SEC,Clear Message RAM SEC interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "INTL1,Clear MCAN Interrupt Line 1." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "INTL0,Clear MCAN Interrupt Line 0." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40517800 newline rgroup.long 0xE0++0x3 newline line.long 0x0 "CANFD1_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0xFC++0x3 line.long 0x0 "CANFD1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x100++0xB line.long 0x0 "CANFD1_MCANSS_CLKEN,MCAN module clock enable" bitfld.long 0x0 0. "CLK_REQEN,MCAN functional and MCAN/MCANSS MMR clock request enable bit" "0: MCAN module functional clock and Vbusp is not..,1: Setting this bit requests MCAN module functional.." line.long 0x4 "CANFD1_MCANSS_CLKDIV,Clock divider" bitfld.long 0x4 0.--1. "RATIO,Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS." "0: Divides input clock by 1,1: Divides input clock by 2,2: Divides input clock by 4,3: Divides input clock by 1" line.long 0x8 "CANFD1_MCANSS_CLKCTL,MCAN-SS clock stop control register" bitfld.long 0x8 8. "WKUP_GLTFLT_EN,Setting this bit enables the glitch filter on MCAN RXD input which wakes up the MCAN controller to exit clock gating." "0: Disable glitch filter enable on RXD input when..,1: Enable glitch filter enable on RXD input when.." newline bitfld.long 0x8 4. "WAKEUP_INT_EN,This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity)" "0: Disable MCAN IP clock stop wakeup interrupt,1: Enable MCAN IP clock stop wakeup interrupt" newline bitfld.long 0x8 0. "STOPREQ,This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request." "0: Disable MCAN-SS clock stop request,1: Enable MCAN-SS clock stop request" rgroup.long 0x10C++0x3 line.long 0x0 "CANFD1_MCANSS_CLKSTS,MCANSS clock stop status register" bitfld.long 0x0 8. "CCLKDONE,This bit indicates the status of MCAN contoller clock request from GPRCM." "0: MCAN controller clock is not available to the..,1: MCAN controller clock is enabled and available.." newline bitfld.long 0x0 4. "STOPREQ_HW_OVR,MCANSS clock stop HW override status bit." "0: MCANSS_CLKCTL.STOPREQ bit has not been cleared..,1: MCANSS_CLKCTL.STOPREQ bit has been cleared by HW." newline bitfld.long 0x0 0. "CLKSTOP_ACKSTS,Clock stop acknowledge status from MCAN IP" "0: No clock stop acknowledged.,1: Clock stop has been acknowledged by MCAN IP;.." tree.end base ad:0x40517200 tree "CANFD1_PROCESSORS[%s]" tree "CANFD1_MCAN_ECC_REGS[%s]" base ad:0x40517400 rgroup.long 0x0++0x3 line.long 0x0 "CANFD1_MCANERR_REV,MCAN Error Aggregator Revision Register" bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number" bitfld.long 0x0 8.--10. "REVMAJ,Major Revision of the Error Aggregator" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor Revision of the Error Aggregator" group.long 0x8++0x3 line.long 0x0 "CANFD1_MCANERR_VECTOR,MCAN ECC Vector Register" rbitfld.long 0x0 24. "RD_SVBUS_DONE,Read Completion Flag" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read Address Offset" bitfld.long 0x0 15. "RD_SVBUS,Read Trigger" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the ECC aggregator.." rgroup.long 0xC++0x7 line.long 0x0 "CANFD1_MCANERR_STAT,MCAN Error Misc Status" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Number of RAMs. Number of ECC RAMs serviced by the aggregator." line.long 0x4 "CANFD1_MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register" bitfld.long 0x4 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3" hexmask.long.word 0x4 16.--27. 1. "MODULE_ID,Module Identification Number" bitfld.long 0x4 8.--10. "REVMAJ,Major Revision of the Error Aggregator" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--5. 1. "REVMIN,Minor Revision of the Error Aggregator" group.long 0x14++0xF line.long 0x0 "CANFD1_MCANERR_CTRL,MCAN ECC Control" bitfld.long 0x0 8. "CHECK_SVBUS_TIMEOUT,Enables Serial VBUS timeout mechanism" "0,1" bitfld.long 0x0 6. "ERROR_ONCE,If this bit is set the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled this error will be cleared the cycle following the read.." "0,1" bitfld.long 0x0 5. "FORCE_N_ROW,Enable single/double-bit error on the next RAM read regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode this applies to writes as well as reads." "0,1" bitfld.long 0x0 4. "FORCE_DED,Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting this bit." "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to.." "0,1" bitfld.long 0x0 2. "ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1" bitfld.long 0x0 1. "ECC_CHECK,Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'." "0,1" bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC Generation" "0,1" line.long 0x4 "CANFD1_MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register" line.long 0x8 "CANFD1_MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,Second column/data bit that needs to be flipped when FORCE_DED is set" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set" line.long 0xC "CANFD1_MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register" hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1,ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error." bitfld.long 0xC 15. "CLR_CTRL_REG_ERROR,Writing a '1' clears the CTRL_REG_ERROR bit" "0,1" bitfld.long 0xC 12. "CLR_ECC_OTHER,Writing a '1' clears the ECC_OTHER bit." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided." "0,1,2,3" newline bitfld.long 0xC 8.--9. "CLR_ECC_SEC,Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided." "0,1,2,3" bitfld.long 0xC 7. "CTRL_REG_ERROR,Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state. S/W needs to.." "0,1" bitfld.long 0xC 4. "ECC_OTHER,SEC While Writeback Error Status" "0,1" bitfld.long 0xC 2.--3. "ECC_DED,Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared." "0,1,2,3" newline bitfld.long 0xC 0.--1. "ECC_SEC,Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "CANFD1_MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register" group.long 0x28++0x3 line.long 0x0 "CANFD1_MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register" bitfld.long 0x0 9. "CLR_SVBUS_TIMEOUT,Write 1 to clear the Serial VBUS Timeout Flag" "0,1" bitfld.long 0x0 1. "SVBUS_TIMEOUT,Serial VBUS Timeout Flag. Write 1 to set." "0,1" rbitfld.long 0x0 0. "WB_PEND,Delayed Write Back Pending Status" "0,1" group.long 0x3C++0x3 line.long 0x0 "CANFD1_MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register" bitfld.long 0x0 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "CANFD1_MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register" bitfld.long 0x0 0. "MSGMEM_PEND,Message RAM SEC Interrupt Pending" "0,1" group.long 0x80++0x3 line.long 0x0 "CANFD1_MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0xC0++0x3 line.long 0x0 "CANFD1_MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0x13C++0x3 line.long 0x0 "CANFD1_MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register" bitfld.long 0x0 0. "EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "CANFD1_MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register" bitfld.long 0x0 0. "MSGMEM_PEND,Message RAM DED Interrupt Pending" "0,1" group.long 0x180++0x3 line.long 0x0 "CANFD1_MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_SET,Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0x1C0++0x3 line.long 0x0 "CANFD1_MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register" bitfld.long 0x0 0. "MSGMEM_ENABLE_CLR,Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1" group.long 0x200++0xF line.long 0x0 "CANFD1_MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register" bitfld.long 0x0 1. "ENABLE_TIMEOUT_SET,Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value." "0,1" bitfld.long 0x0 0. "ENABLE_PARITY_SET,Write 1 to enable parity errors. Reads return the corresponding enable bit's current value." "0,1" line.long 0x4 "CANFD1_MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register" bitfld.long 0x4 1. "ENABLE_TIMEOUT_CLR,Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value." "0,1" bitfld.long 0x4 0. "ENABLE_PARITY_CLR,Write 1 to disable parity errors. Reads return the corresponding enable bit's current value." "0,1" line.long 0x8 "CANFD1_MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register" bitfld.long 0x8 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3" bitfld.long 0x8 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3" line.long 0xC "CANFD1_MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register" bitfld.long 0xC 2.--3. "SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3" bitfld.long 0xC 0.--1. "AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3" tree.end base ad:0x40517200 tree "CANFD1_MCANSS_REGS[%s]" rgroup.long 0x0++0x3 line.long 0x0 "CANFD1_MCANSS_PID,MCAN Subsystem Revision Register" bitfld.long 0x0 30.--31. "SCHEME,PID Register Scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module Identification Number" bitfld.long 0x0 8.--10. "MAJOR,Major Revision of the MCAN Subsystem" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision of the MCAN Subsystem" group.long 0x4++0x3 line.long 0x0 "CANFD1_MCANSS_CTRL,MCAN Subsystem Control Register" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable." "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit fully waking the MCAN up on an enabled wakeup request." "0,1" bitfld.long 0x0 4. "WAKEUPREQEN,Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity." "0,1" bitfld.long 0x0 3. "DBGSUSP_FREE,Debug Suspend Free Bit. Enables debug suspend." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "CANFD1_MCANSS_STAT,MCAN Subsystem Status Register" bitfld.long 0x0 2. "ENABLE_FDOE,Enable FD (Flexible Data-Rate) Configuration" "0,1" bitfld.long 0x0 1. "MEM_INIT_DONE,Memory Initialization Done." "0,1" bitfld.long 0x0 0. "RESET,Soft Reset Status." "0,1" group.long 0xC++0xF line.long 0x0 "CANFD1_MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0." "0,1" line.long 0x4 "CANFD1_MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register" bitfld.long 0x4 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit." "0,1" line.long 0x8 "CANFD1_MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register" bitfld.long 0x8 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0." "0,1" line.long 0xC "CANFD1_MCANSS_IE,MCAN Subsystem Interrupt Enable Register" bitfld.long 0xC 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "CANFD1_MCANSS_IES,MCAN Subsystem Interrupt Enable Status" bitfld.long 0x0 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Status. To set use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit." "0,1" group.long 0x20++0x7 line.long 0x0 "CANFD1_MCANSS_EOI,MCAN Subsystem End of Interrupt" hexmask.long.byte 0x0 0.--7. 1. "EOI,End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1 another interrupt is generated." line.long 0x4 "CANFD1_MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0" hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALER,External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value except in the case of 0. A zero value in this bit field will act identically to a value of 0x000001." rgroup.long 0x28++0x3 line.long 0x0 "CANFD1_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1 an MCANSS_EOI write of '1' to bit 0 will issue another interrupt." tree.end tree.end tree.end tree.end endif tree.end endif sif (cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPM0L222*")) tree "COMP (Comparator)" base ad:0x0 sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*")) tree "COMP0" base ad:0x40008000 group.long 0x400++0x7 line.long 0x0 "COMP0_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "COMP0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "COMP0_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "COMP0_GPRCM[%s]" base ad:0x40008800 group.long 0x0++0x3 line.long 0x0 "COMP0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end repeat 2. (list 0x0 0x1)(list ad:0x40009020 ad:0x4000904C) tree "COMP0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "COMP0_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,1: Comparator output ready interrupt,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long ($2+0x8)++0x3 line.long 0x0 "COMP0_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long ($2+0x10)++0x3 line.long 0x0 "COMP0_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long ($2+0x18)++0x3 line.long 0x0 "COMP0_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long ($2+0x20)++0x3 line.long 0x0 "COMP0_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "COMP0_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end repeat.end base ad:0x40008000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "COMP0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP0_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP0_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP0_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--4. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: VREF applied as reference to comparator. DAC is.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP0_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP0_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*")) tree "COMP1" base ad:0x4000A000 group.long 0x400++0x7 line.long 0x0 "COMP1_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "COMP1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "COMP1_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "COMP1_GPRCM[%s]" base ad:0x4000A800 group.long 0x0++0x3 line.long 0x0 "COMP1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end repeat 2. (list 0x0 0x1)(list ad:0x4000B020 ad:0x4000B04C) tree "COMP1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "COMP1_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,1: Comparator output ready interrupt,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long ($2+0x8)++0x3 line.long 0x0 "COMP1_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long ($2+0x10)++0x3 line.long 0x0 "COMP1_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long ($2+0x18)++0x3 line.long 0x0 "COMP1_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long ($2+0x20)++0x3 line.long 0x0 "COMP1_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "COMP1_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end repeat.end base ad:0x4000A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "COMP1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP1_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP1_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP1_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--4. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: VREF applied as reference to comparator. DAC is.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP1_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP1_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*")) tree "COMP2" base ad:0x4000C000 group.long 0x400++0x7 line.long 0x0 "COMP2_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "COMP2_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "COMP2_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "COMP2_GPRCM[%s]" base ad:0x4000C800 group.long 0x0++0x3 line.long 0x0 "COMP2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end repeat 2. (list 0x0 0x1)(list ad:0x4000D020 ad:0x4000D04C) tree "COMP2_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "COMP2_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,1: Comparator output ready interrupt,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long ($2+0x8)++0x3 line.long 0x0 "COMP2_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long ($2+0x10)++0x3 line.long 0x0 "COMP2_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long ($2+0x18)++0x3 line.long 0x0 "COMP2_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long ($2+0x20)++0x3 line.long 0x0 "COMP2_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "COMP2_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end repeat.end base ad:0x4000C000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "COMP2_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP2_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP2_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP2_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP2_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--4. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: VREF applied as reference to comparator. DAC is.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP2_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP2_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) tree "COMP2" base ad:0x4000C000 group.long 0x400++0x7 line.long 0x0 "COMP2_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "COMP2_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "COMP2_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "COMP2_CPU_INT[%s]" base ad:0x4000D020 rgroup.long 0x0++0x3 line.long 0x0 "COMP2_CPU_INT_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,?,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long 0x8++0x3 line.long 0x0 "COMP2_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "COMP2_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long 0x18++0x3 line.long 0x0 "COMP2_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "COMP2_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "COMP2_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end tree "COMP2_GEN_EVENT[%s]" base ad:0x4000D050 rgroup.long 0x0++0x3 line.long 0x0 "COMP2_GEN_EVENT_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,?,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long 0x8++0x3 line.long 0x0 "COMP2_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "COMP2_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long 0x18++0x3 line.long 0x0 "COMP2_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "COMP2_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "COMP2_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end tree "COMP2_GPRCM[%s]" base ad:0x4000C800 group.long 0x0++0x3 line.long 0x0 "COMP2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4000C000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "COMP2_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP2_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP2_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP2_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP2_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--5. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: In devices where internal VREF is buffered and..,?,5: VDDA is used as comparator reference. Note: In..,6: Internal reference selected as the reference..,7: Internal VREF is used as the source of.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP2_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP2_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) tree "COMP1" base ad:0x4000A000 group.long 0x400++0x7 line.long 0x0 "COMP1_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "COMP1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "COMP1_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "COMP1_CPU_INT[%s]" base ad:0x4000B020 rgroup.long 0x0++0x3 line.long 0x0 "COMP1_CPU_INT_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,?,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long 0x8++0x3 line.long 0x0 "COMP1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "COMP1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long 0x18++0x3 line.long 0x0 "COMP1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "COMP1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "COMP1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end tree "COMP1_GEN_EVENT[%s]" base ad:0x4000B050 rgroup.long 0x0++0x3 line.long 0x0 "COMP1_GEN_EVENT_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,?,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long 0x8++0x3 line.long 0x0 "COMP1_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "COMP1_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long 0x18++0x3 line.long 0x0 "COMP1_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "COMP1_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "COMP1_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end tree "COMP1_GPRCM[%s]" base ad:0x4000A800 group.long 0x0++0x3 line.long 0x0 "COMP1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4000A000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "COMP1_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP1_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP1_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP1_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--5. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: In devices where internal VREF is buffered and..,?,5: VDDA is used as comparator reference. Note: In..,6: Internal reference selected as the reference..,7: Internal VREF is used as the source of.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP1_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP1_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "COMP0" base ad:0x40008000 group.long 0x400++0x7 line.long 0x0 "COMP0_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "COMP0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x3 line.long 0x0 "COMP0_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "COMP0_CPU_INT[%s]" base ad:0x40009020 rgroup.long 0x0++0x3 line.long 0x0 "COMP0_CPU_INT_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,?,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long 0x8++0x3 line.long 0x0 "COMP0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "COMP0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long 0x18++0x3 line.long 0x0 "COMP0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "COMP0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "COMP0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end tree "COMP0_GEN_EVENT[%s]" base ad:0x40009050 rgroup.long 0x0++0x3 line.long 0x0 "COMP0_GEN_EVENT_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,?,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long 0x8++0x3 line.long 0x0 "COMP0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "COMP0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long 0x18++0x3 line.long 0x0 "COMP0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "COMP0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "COMP0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end tree "COMP0_GPRCM[%s]" base ad:0x40008800 group.long 0x0++0x3 line.long 0x0 "COMP0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40008000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "COMP0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP0_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP0_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP0_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--5. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: In devices where internal VREF is buffered and..,?,5: VDDA is used as comparator reference. Note: In..,6: Internal reference selected as the reference..,7: Internal VREF is used as the source of.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP0_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP0_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif sif (cpuis("MSPM0L130*")||cpuis("MSPM0L134*")) tree "COMP0" base ad:0x40008000 group.long 0x400++0x7 line.long 0x0 "COMP0_FSUB_0,Subscriber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "COMP0_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x3 line.long 0x0 "COMP0_FPUB_1,Publisher port 1" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "COMP0_GPRCM[%s]" base ad:0x40008800 group.long 0x0++0x3 line.long 0x0 "COMP0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "COMP0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "COMP0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: disable COMP to request SYSOSC,1: enable COMP to request SYSOSC" rgroup.long 0x14++0x3 line.long 0x0 "COMP0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end repeat 2. (list 0x0 0x1)(list ad:0x40009020 ad:0x4000904C) tree "COMP0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "COMP0_IIDX,Interrupt index" bitfld.long 0x0 0.--1. "STAT,Interrupt index status" "0: No pending interrupt,1: Comparator output ready interrupt,2: Comparator output interrupt,3: Comparator output inverted interrupt" group.long ($2+0x8)++0x3 line.long 0x0 "COMP0_IMASK,Interrupt mask" bitfld.long 0x0 3. "OUTRDYIFG,Masks OUTRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "COMPINVIFG,Masks COMPINVIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "COMPIFG,Masks COMPIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long ($2+0x10)++0x3 line.long 0x0 "COMP0_RIS,Raw interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: No interrupt pending,1: Interrupt pending" bitfld.long 0x0 2. "COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x0 1. "COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: No interrupt pending,1: Interrupt pending" rgroup.long ($2+0x18)++0x3 line.long 0x0 "COMP0_MIS,Masked interrupt status" bitfld.long 0x0 3. "OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: OUTRDYIFG does not request an interrupt service..,1: OUTRDYIFG requests an interrupt service routine" bitfld.long 0x0 2. "COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: COMPINVIFG does not request an interrupt service..,1: COMPINVIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "COMPIFG,Masked interrupt status for COMPIFG" "0: COMPIFG does not request an interrupt service..,1: COMPIFG requests an interrupt service routine" wgroup.long ($2+0x20)++0x3 line.long 0x0 "COMP0_ISET,Interrupt set" bitfld.long 0x0 3. "OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is set" bitfld.long 0x0 2. "COMPINVIFG,Sets COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is set" newline bitfld.long 0x0 1. "COMPIFG,Sets COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "COMP0_ICLR,Interrupt clear" bitfld.long 0x0 3. "OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to OUTRDYIFG is cleared" bitfld.long 0x0 2. "COMPINVIFG,Clears COMPINVIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPINVIFG is cleared" newline bitfld.long 0x0 1. "COMPIFG,Clears COMPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to COMPIFG is cleared" tree.end repeat.end base ad:0x40008000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "COMP0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "COMP0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xF line.long 0x0 "COMP0_CTL0,Control 0" bitfld.long 0x0 31. "IMEN,Channel input enable for the negative terminal of the comparator." "0: Selected analog input channel for negative..,1: Selected analog input channel for negative.." bitfld.long 0x0 16.--18. "IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" newline bitfld.long 0x0 15. "IPEN,Channel input enable for the positive terminal of the comparator." "0: Selected analog input channel for positive..,1: Selected analog input channel for positive.." bitfld.long 0x0 0.--2. "IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: Channel 0 selected,1: Channel 1 selected,2: Channel 2 selected,3: Channel 3 selected,4: Channel 4 selected,5: Channel 5 selected,6: Channel 6 selected,7: Channel 7 selected" line.long 0x4 "COMP0_CTL1,Control 1" bitfld.long 0x4 12. "WINCOMPEN,This bit enables window comparator operation of comparator." "0: window comparator is disable,1: window comparator is enable" bitfld.long 0x4 9.--10. "FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: Typical filter delay of 70 ns,1: Typical filter delay of 500 ns,2: Typical filter delay of 1200 ns,3: Typical filter delay of 2700 ns" newline bitfld.long 0x4 8. "FLTEN,This bit enables the analog filter at comparator output." "0: Comparator output filter is disabled,1: Comparator output filter is enabled" bitfld.long 0x4 7. "OUTPOL,This bit selects the comparator output polarity." "0: Comparator output is non-inverted,1: Comparator output is inverted" newline bitfld.long 0x4 5.--6. "HYST,These bits select the hysteresis setting of the comparator." "0: No hysteresis,1: Low hysteresis typical 10mV,2: Medium hysteresis typical 20mV,3: High hysteresis typical 30mV" bitfld.long 0x4 4. "IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: Rising edge sets COMPIFG and falling edge sets..,1: Falling edge sets COMPIFG and rising edge sets.." newline bitfld.long 0x4 3. "SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: Comparator positive and negative input terminals..,1: Comparator positive and negative input terminals.." bitfld.long 0x4 2. "EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: Comparator inputs not exchanged and output not..,1: Comparator inputs exchanged and output inverted" newline bitfld.long 0x4 1. "MODE,This bit selects the comparator operating mode." "0: Comparator is in fast mode,1: Comparator is in ultra-low power mode" bitfld.long 0x4 0. "ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: Comparator is off,1: Comparator is on" line.long 0x8 "COMP0_CTL2,Control 2" bitfld.long 0x8 24. "SAMPMODE,Enable sampled mode of comparator." "0: Sampled mode disabled,1: Sampled mode enabled" bitfld.long 0x8 17. "DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0 selected for 8-bit DAC,1: DACCODE1 selected for 8-bit DAC" newline bitfld.long 0x8 16. "DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: Comparator output controls selection between..,1: DACSW bit controls selection between DACCODE0.." bitfld.long 0x8 8.--10. "BLANKSRC,These bits select the blanking source for the comparator." "0: Blanking source disabled,1: Select Blanking Source 1,2: Select Blanking Source 2,3: Select Blanking Source 3,4: Select Blanking Source 4,5: Select Blanking Source 5,6: Select Blanking Source 6,?" newline bitfld.long 0x8 7. "REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: If EXCH bit is 0 the selected reference is..,1: If EXCH bit is 0 the selected reference is.." bitfld.long 0x8 3.--4. "REFSRC,These bits select the reference source for the comparator." "0: Reference voltage generator is disabled (local..,1: VDDA selected as the reference source to DAC and..,2: VREF selected as reference to DAC and DAC output..,3: VREF applied as reference to comparator. DAC is.." newline bitfld.long 0x8 0. "REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: ULP_REF bandgap local reference buffer and 8-bit..,1: ULP_REF bandgap local reference buffer and 8-bit.." line.long 0xC "COMP0_CTL3,Control 3" hexmask.long.byte 0xC 16.--23. 1. "DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." hexmask.long.byte 0xC 0.--7. 1. "DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256." rgroup.long 0x1120++0x3 line.long 0x0 "COMP0_STAT,Status" bitfld.long 0x0 0. "OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: Comparator output is low,1: Comparator output is high" tree.end endif tree.end endif tree "CPUSS (CPU Subsystem)" base ad:0x40400000 rgroup.long 0x10E0++0x3 line.long 0x0 "CPUSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT_CFG,Event line mode select" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "CPUSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) rgroup.long 0x1100++0x3 line.long 0x0 "CPUSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x1108++0x3 line.long 0x0 "CPUSS_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x1110++0x3 line.long 0x0 "CPUSS_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x1118++0x3 line.long 0x0 "CPUSS_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x1120++0x3 line.long 0x0 "CPUSS_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x1128++0x3 line.long 0x0 "CPUSS_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" group.long 0x1E00++0x3 line.long 0x0 "CPUSS_TEST0,DTB MUX Sel" hexmask.long.byte 0x0 5.--9. 1. "DTB_MUX_SEL_WUC,DTB Mux Sel" bitfld.long 0x0 0.--2. "DTB_MUX_SEL_CPU,DTB Mux Sel" "0,1,2,3,4,5,6,7" endif group.long 0x1300++0x3 line.long 0x0 "CPUSS_CTL,Prefetch/Cache control" bitfld.long 0x0 2. "LITEN,Literal caching and prefetch enable." "0: Literal caching disabled,1: Literal caching enabled" bitfld.long 0x0 1. "ICACHE,Used to enable/disable Instruction caching on flash access." "0: Disable instruction caching.,1: Enable instruction caching." newline bitfld.long 0x0 0. "PREFETCH,Used to enable/disable instruction prefetch to Flash." "0: Disable instruction prefetch.,1: Enable instruction prefetch." sif (cpuis("MSPM0G110*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0G150*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0G151*")) tree "CPUSS_CPU_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" tree.end tree "CPUSS_CPU_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" tree.end endif sif (cpuis("MSPM0G310*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0G350*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0G351*")) tree "CPUSS_CPU_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" tree.end tree "CPUSS_CPU_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" tree.end endif sif (cpuis("MSPM0L110*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0L111*")) tree "CPUSS_CPU_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP0_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" tree.end tree "CPUSS_CPU_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_MIS,Masked interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Masked interrupt status for INT0" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_ISET,Interrupt set" hexmask.long.byte 0x0 0.--7. 1. "INT,Sets INT in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_CPU_INT_GROUP1_ICLR,Interrupt clear" hexmask.long.byte 0x0 0.--7. 1. "INT,Clears INT in RIS register" tree.end endif sif (cpuis("MSPM0L122*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0L130*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0L134*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif sif (cpuis("MSPM0L222*")) tree "CPUSS_INT_GROUP0[%s]" base ad:0x40401100 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP0_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP0_RIS,Raw interrupt status" hexmask.long.byte 0x0 0.--7. 1. "INT,Raw interrupt status for INT" rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end tree "CPUSS_INT_GROUP1[%s]" base ad:0x40401130 rgroup.long 0x0++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" rgroup.long 0x8++0x3 line.long 0x0 "CPUSS_INT_GROUP1_IMASK,Interrupt mask" hexmask.long.byte 0x0 0.--7. 1. "INT,Masks the corresponding interrupt" rgroup.long 0x10++0x3 line.long 0x0 "CPUSS_INT_GROUP1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INT,Raw interrupt status for INT" "0: INT0 did not occur.,1: INT0 occurred." rgroup.long 0x18++0x3 line.long 0x0 "CPUSS_INT_GROUP1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INT,Masked interrupt status for INT0" "0: INT does not request an interrupt service routine,1: INT requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ISET,Interrupt set" bitfld.long 0x0 0. "INT,Sets INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is set" wgroup.long 0x28++0x3 line.long 0x0 "CPUSS_INT_GROUP1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INT,Clears INT in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to INT is cleared" tree.end endif tree.end sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPS003.*")) tree "CRC (Cyclic Redundancy Check)" base ad:0x40440000 tree "CRC_GPRCM[%s]" base ad:0x40440800 group.long 0x0++0x3 line.long 0x0 "CRC_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "CRC_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "CRC_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40440000 newline rgroup.long 0x10FC++0x3 newline line.long 0x0 "CRC_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x3 line.long 0x0 "CRC_CRCCTRL,CRC Control Register" bitfld.long 0x0 4. "OUTPUT_BYTESWAP,CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register." "0: Output byteswapping is disabled,1: Output byteswapping is enabled." bitfld.long 0x0 2. "INPUT_ENDIANNESS,CRC Endian. This bit indicates the byte order within a word or half word of input data." "0: LSB is lowest memory address and first to be..,1: LSB is highest memory address and last to be.." newline bitfld.long 0x0 1. "BITREVERSE,CRC Bit Input and output Reverse. This bit indicates that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator and that the bit order of the calculated CRC is be reversed when read.." "0: Bit order is not reversed.,1: Bit order is reversed." sif (cpuis("MSPM0G110*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" endif wgroup.long 0x1104++0x7 line.long 0x0 "CRC_CRCSEED,CRC Seed Register" hexmask.long 0x0 0.--31. 1. "SEED,Seed Data" line.long 0x4 "CRC_CRCIN,CRC Input Data Register" hexmask.long 0x4 0.--31. 1. "DATA,Input Data" rgroup.long 0x110C++0x3 line.long 0x0 "CRC_CRCOUT,CRC Output Result Register" hexmask.long 0x0 0.--31. 1. "RESULT,Result" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0G150*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0G310*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0G350*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0L110*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0L130*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif sif (cpuis("MSPM0L134*")) repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRC_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end endif tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "CRCP (Cyclic Redundancy Check Polynomial)" base ad:0x40440000 tree "CRCP0_GPRCM[%s]" base ad:0x40440800 group.long 0x0++0x3 line.long 0x0 "CRCP0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "CRCP0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "CRCP0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40440000 newline rgroup.long 0x10FC++0x3 newline line.long 0x0 "CRCP0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x3 line.long 0x0 "CRCP0_CRCCTRL,CRC Control Register" bitfld.long 0x0 4. "OUTPUT_BYTESWAP,CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register." "0: Output byteswapping is disabled,1: Output byteswapping is enabled." bitfld.long 0x0 2. "INPUT_ENDIANNESS,CRC Endian. This bit indicates the byte order within a word or half word of input data." "0: LSB is lowest memory address and first to be..,1: LSB is highest memory address and last to be.." newline bitfld.long 0x0 1. "BITREVERSE,CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator and that the bit order of the calculated CRC is be reversed when read from.." "0: Bit order is not reversed.,1: Bit order is reversed." bitfld.long 0x0 0. "POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC-32 ISO-3309 calulation is performed,1: CRC-16 CCITT is performed" wgroup.long 0x1104++0x7 line.long 0x0 "CRCP0_CRCSEED,CRC Seed Register" hexmask.long 0x0 0.--31. 1. "SEED,Seed Data" line.long 0x4 "CRCP0_CRCIN,CRC Input Data Register" hexmask.long 0x4 0.--31. 1. "DATA,Input Data" rgroup.long 0x110C++0x3 line.long 0x0 "CRCP0_CRCOUT,CRC Output Result Register" hexmask.long 0x0 0.--31. 1. "RESULT,Result" group.long 0x1110++0x3 line.long 0x0 "CRCP0_CRCPOLY,CRC Polynomial configuration register" repeat 512. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x1800)++0x3 line.long 0x0 "CRCP0_CRCIN_IDX[$1],CRC Input Data Array Register" hexmask.long 0x0 0.--31. 1. "DATA,Input Data" repeat.end tree.end endif sif (cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")) tree "DAC (Digital-to-Analog Converter)" base ad:0x40018000 group.long 0x400++0x3 line.long 0x0 "DAC0_FSUB_0,Subscriber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." sif (cpuis("MSPM0G150*")) group.long 0x404++0x3 line.long 0x0 "DAC0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." repeat 2. (list 0x0 0x1)(list ad:0x40019020 ad:0x4001904C) tree "DAC0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DAC0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DAC0_IMASK,Interrupt mask" bitfld.long 0x0 14. "DMADONEIFG,Masks DMADONEIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 13. "FIFOURUNIFG,Masks FIFOURUNIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 11. "FIFO3B4IFG,Masks FIFO3B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 10. "FIFO1B2IFG,Masks FIFO1B2IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 9. "FIFO1B4IFG,Masks FIFO1B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 8. "FIFOFULLIFG,Masks FIFOFULLIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 1. "MODRDYIFG,Masks MODRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long ($2+0x10)++0x3 line.long 0x0 "DAC0_RIS,Raw interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: DMA done condition did not occur,1: DMA done condition occurred" bitfld.long 0x0 13. "FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: FIFO underrun condition did not occur,1: FIFO underrun condition occurred" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: FIFO empty condition did not occur,1: FIFO empty condition occurred" bitfld.long 0x0 11. "FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: FIFO three fourth empty condition did not occur,1: FIFO three fourth empty condition occurred" newline bitfld.long 0x0 10. "FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: FIFO half empty condition did not occur,1: FIFO half empty condition occurred" bitfld.long 0x0 9. "FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: FIFO one fourth empty condition did not occur,1: FIFO one fourth empty condition occurred" newline bitfld.long 0x0 8. "FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: FIFO full condition did not occur,1: FIFO full condition occurred" bitfld.long 0x0 1. "MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: DAC module ready event did not occur,1: DAC module ready event occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DAC0_MIS,Masked interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: DMADONEIFG does not request an interrupt service..,1: DMADONEIFG requests an interrupt service routine" bitfld.long 0x0 13. "FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: FIFOURUNIFG does not request an interrupt..,1: FIFOURUNIFG requests an interrupt service routine" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: FIFOEMPTYIFG does not request an interrupt..,1: FIFOEMPTYIFG requests an interrupt service routine" bitfld.long 0x0 11. "FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: FIFO3B4IFG does not request an interrupt service..,1: FIFO3B4IFG requests an interrupt service routine" newline bitfld.long 0x0 10. "FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: FIFO1B2IFG does not request an interrupt service..,1: FIFO1B2IFG requests an interrupt service routine" bitfld.long 0x0 9. "FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: FIFO1B4IFG does not request an interrupt service..,1: FIFO1B4IFG requests an interrupt service routine" newline bitfld.long 0x0 8. "FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: FIFOFULLIFG does not request an interrupt..,1: FIFOFULLIFG requests an interrupt service routine" bitfld.long 0x0 1. "MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: MODRDYIFG does not request an interrupt service..,1: MODRDYIFG requests an interrupt service routine" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DAC0_ISET,Interrupt set" bitfld.long 0x0 14. "DMADONEIFG,Sets DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is set" bitfld.long 0x0 13. "FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is set" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is set" bitfld.long 0x0 11. "FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is set" newline bitfld.long 0x0 10. "FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is set" bitfld.long 0x0 9. "FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is set" newline bitfld.long 0x0 8. "FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is set" bitfld.long 0x0 1. "MODRDYIFG,Sets MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DAC0_ICLR,Interrupt clear" bitfld.long 0x0 14. "DMADONEIFG,Clears DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is cleared" bitfld.long 0x0 13. "FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is cleared" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is cleared" bitfld.long 0x0 11. "FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is cleared" newline bitfld.long 0x0 10. "FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is cleared" bitfld.long 0x0 9. "FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is cleared" newline bitfld.long 0x0 8. "FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is cleared" bitfld.long 0x0 1. "MODRDYIFG,Clears MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is cleared" tree.end repeat.end base ad:0x40018000 endif sif (cpuis("MSPM0G350*")) group.long 0x404++0x3 line.long 0x0 "DAC0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif group.long 0x444++0x3 line.long 0x0 "DAC0_FPUB_1,Publisher port 1" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "DAC0_GPRCM[%s]" base ad:0x40018800 group.long 0x0++0x3 line.long 0x0 "DAC0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "DAC0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "DAC0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40018000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "DAC0_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: Event handled by software. Software must clear..,2: Event handled by hardware. The hardware (another..,?" rgroup.long 0x10FC++0x3 line.long 0x0 "DAC0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x3 line.long 0x0 "DAC0_CTL0,Control 0" bitfld.long 0x0 16. "DFM,This bit defines the DAC input data format." "0: Straight binary,1: Twos complement" bitfld.long 0x0 8. "RES,These bits define the DAC output voltage resolution." "0: 8-bits resolution,1: 12-bit resolution" newline bitfld.long 0x0 0. "ENABLE,This bit enables the DAC module." "0: DAC is disabled,1: DAC is enabled" group.long 0x1110++0x3 line.long 0x0 "DAC0_CTL1,Control 1" bitfld.long 0x0 24. "OPS,These bits select the DAC output on device pin." "0: No connect. Both DAC output switches are open.,1: OUT0 output is selected" bitfld.long 0x0 9. "REFSN,This bit selects the DAC voltage reference source + input." "0: VEREFN pin as VR-,1: Analog supply (VSSA) as VR-" newline bitfld.long 0x0 8. "REFSP,This bit selects the DAC voltage reference source + input." "0: Analog supply (VDDA) as VR+,1: VEREFP pin as VR+" bitfld.long 0x0 1. "AMPHIZ,AMPHIZ - amplifier output value" "0: amplifier output is high impedance,1: amplifier output is pulled down to ground" newline bitfld.long 0x0 0. "AMPEN,AMP_EN - output amplifier enabled or disabled" "0: disabled,1: enabled" group.long 0x1120++0x3 line.long 0x0 "DAC0_CTL2,Control 2" bitfld.long 0x0 24. "DMATRIGEN,This bit enables the DMA trigger generation mechanism. When this bit is set along with FIFOEN the DMA trigger is generated based on the empty FIFO locations qualified by FIFOTH settings. This bit needs to be cleared by SW to stop further DMA.." "0: DMA trigger generation mechanism is disabled,1: DMA trigger generation mechanism is enabled" sif (cpuis("MSPM0G150*")) bitfld.long 0x0 16.--17. "FIFOTRIGSEL,These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted the data from FIFO (as indicated by read pointer) is moved into internal DAC data register." "0: Sample time generator output,1: Hardware trigger-0 from event fabric,2: Hardware trigger-1 from event fabric,3: Reserved - unimplemented" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 16.--17. "FIFOTRIGSEL,These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted the data from FIFO (as indicated by read pointer) is moved into internal DAC data register." "0: Sample time generator output,1: Hardware trigger-0 from event fabric,2: Reserved - unimplemented,3: Reserved - unimplemented" endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 16.--17. "FIFOTRIGSEL,These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted the data from FIFO (as indicated by read pointer) is moved into internal DAC data register." "0: Sample time generator output,1: Hardware trigger-0 from event fabric,2: Hardware trigger-1 from event fabric,3: Reserved - unimplemented" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 16.--17. "FIFOTRIGSEL,These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted the data from FIFO (as indicated by read pointer) is moved into internal DAC data register." "0: Sample time generator output,1: Hardware trigger-0 from event fabric,2: Reserved - unimplemented,3: Reserved - unimplemented" endif bitfld.long 0x0 8.--9. "FIFOTH,These bits determine the FIFO threshold. In case of DMA based operation DAC generates new DMA trigger when the number of empty locations in FIFO match the selected FIFO threshold level." "0: One fourth of the FIFO locations are empty,1: Half of the FIFO locations are empty,2: Three fourth of the FIFO locations are empty,3: Reserved value. Defaults to same effect as.." newline bitfld.long 0x0 0. "FIFOEN,This bit enables the FIFO and the FIFO hardware control state machine." "0: FIFO is disabled,1: FIFO is enabled" group.long 0x1130++0x3 line.long 0x0 "DAC0_CTL3,Control 3" hexmask.long.byte 0x0 8.--11. 1. "STIMCONFIG,These bits are used to configure the trigger rate from the sample time generator." bitfld.long 0x0 0. "STIMEN,This bit enables the sample time generator." "0: Sample time generator is disabled,1: Sample time generator is enabled" group.long 0x1140++0x3 line.long 0x0 "DAC0_CALCTL,Calibration control" bitfld.long 0x0 1. "CALSEL,This bit is used to select between factory trim or self calibration trim." "0: Factory Trim Calibration Values are used when..,1: Self Calibration Trim Values are used when.." bitfld.long 0x0 0. "CALON,This bit when set initiates the DAC offset error calibration sequence and is automatically reset when the offset error calibration completes." "0: Offset error calibration is not active,1: Initiate offset error calibration or offset.." rgroup.long 0x1160++0x3 line.long 0x0 "DAC0_CALDATA,Calibration data" hexmask.long.byte 0x0 0.--6. 1. "DATA,DAC offset error calibration data. The DAC offset error calibration data is represented in twos complement format providing a range of 64 to +63." group.long 0x1200++0x3 line.long 0x0 "DAC0_DATA0,Data 0" hexmask.long.word 0x0 0.--11. 1. "DATA_VALUE,This is the data written for digital to analog conversion." sif (cpuis("MSPM0G151*")) tree "DAC0_CPU_INT[%s]" base ad:0x40019020 rgroup.long 0x0++0x3 line.long 0x0 "DAC0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DAC0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 14. "DMADONEIFG,Masks DMADONEIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 13. "FIFOURUNIFG,Masks FIFOURUNIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 11. "FIFO3B4IFG,Masks FIFO3B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 10. "FIFO1B2IFG,Masks FIFO1B2IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 9. "FIFO1B4IFG,Masks FIFO1B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 8. "FIFOFULLIFG,Masks FIFOFULLIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 1. "MODRDYIFG,Masks MODRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "DAC0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: DMA done condition did not occur,1: DMA done condition occurred" bitfld.long 0x0 13. "FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: FIFO underrun condition did not occur,1: FIFO underrun condition occurred" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: FIFO empty condition did not occur,1: FIFO empty condition occurred" bitfld.long 0x0 11. "FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: FIFO three fourth empty condition did not occur,1: FIFO three fourth empty condition occurred" newline bitfld.long 0x0 10. "FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: FIFO half empty condition did not occur,1: FIFO half empty condition occurred" bitfld.long 0x0 9. "FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: FIFO one fourth empty condition did not occur,1: FIFO one fourth empty condition occurred" newline bitfld.long 0x0 8. "FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: FIFO full condition did not occur,1: FIFO full condition occurred" bitfld.long 0x0 1. "MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: DAC module ready event did not occur,1: DAC module ready event occurred" rgroup.long 0x18++0x3 line.long 0x0 "DAC0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: DMADONEIFG does not request an interrupt service..,1: DMADONEIFG requests an interrupt service routine" bitfld.long 0x0 13. "FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: FIFOURUNIFG does not request an interrupt..,1: FIFOURUNIFG requests an interrupt service routine" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: FIFOEMPTYIFG does not request an interrupt..,1: FIFOEMPTYIFG requests an interrupt service routine" bitfld.long 0x0 11. "FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: FIFO3B4IFG does not request an interrupt service..,1: FIFO3B4IFG requests an interrupt service routine" newline bitfld.long 0x0 10. "FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: FIFO1B2IFG does not request an interrupt service..,1: FIFO1B2IFG requests an interrupt service routine" bitfld.long 0x0 9. "FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: FIFO1B4IFG does not request an interrupt service..,1: FIFO1B4IFG requests an interrupt service routine" newline bitfld.long 0x0 8. "FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: FIFOFULLIFG does not request an interrupt..,1: FIFOFULLIFG requests an interrupt service routine" bitfld.long 0x0 1. "MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: MODRDYIFG does not request an interrupt service..,1: MODRDYIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "DAC0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 14. "DMADONEIFG,Sets DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is set" bitfld.long 0x0 13. "FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is set" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is set" bitfld.long 0x0 11. "FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is set" newline bitfld.long 0x0 10. "FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is set" bitfld.long 0x0 9. "FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is set" newline bitfld.long 0x0 8. "FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is set" bitfld.long 0x0 1. "MODRDYIFG,Sets MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "DAC0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 14. "DMADONEIFG,Clears DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is cleared" bitfld.long 0x0 13. "FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is cleared" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is cleared" bitfld.long 0x0 11. "FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is cleared" newline bitfld.long 0x0 10. "FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is cleared" bitfld.long 0x0 9. "FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is cleared" newline bitfld.long 0x0 8. "FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is cleared" bitfld.long 0x0 1. "MODRDYIFG,Clears MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is cleared" tree.end tree "DAC0_GEN_EVENT[%s]" base ad:0x40019050 rgroup.long 0x0++0x3 line.long 0x0 "DAC0_GEN_EVENT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DAC0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 14. "DMADONEIFG,Masks DMADONEIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 13. "FIFOURUNIFG,Masks FIFOURUNIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 11. "FIFO3B4IFG,Masks FIFO3B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 10. "FIFO1B2IFG,Masks FIFO1B2IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 9. "FIFO1B4IFG,Masks FIFO1B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 8. "FIFOFULLIFG,Masks FIFOFULLIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 1. "MODRDYIFG,Masks MODRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "DAC0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: DMA done condition did not occur,1: DMA done condition occurred" bitfld.long 0x0 13. "FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: FIFO underrun condition did not occur,1: FIFO underrun condition occurred" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: FIFO empty condition did not occur,1: FIFO empty condition occurred" bitfld.long 0x0 11. "FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: FIFO three fourth empty condition did not occur,1: FIFO three fourth empty condition occurred" newline bitfld.long 0x0 10. "FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: FIFO half empty condition did not occur,1: FIFO half empty condition occurred" bitfld.long 0x0 9. "FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: FIFO one fourth empty condition did not occur,1: FIFO one fourth empty condition occurred" newline bitfld.long 0x0 8. "FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: FIFO full condition did not occur,1: FIFO full condition occurred" bitfld.long 0x0 1. "MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: DAC module ready event did not occur,1: DAC module ready event occurred" rgroup.long 0x18++0x3 line.long 0x0 "DAC0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: DMADONEIFG does not request an interrupt service..,1: DMADONEIFG requests an interrupt service routine" bitfld.long 0x0 13. "FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: FIFOURUNIFG does not request an interrupt..,1: FIFOURUNIFG requests an interrupt service routine" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: FIFOEMPTYIFG does not request an interrupt..,1: FIFOEMPTYIFG requests an interrupt service routine" bitfld.long 0x0 11. "FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: FIFO3B4IFG does not request an interrupt service..,1: FIFO3B4IFG requests an interrupt service routine" newline bitfld.long 0x0 10. "FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: FIFO1B2IFG does not request an interrupt service..,1: FIFO1B2IFG requests an interrupt service routine" bitfld.long 0x0 9. "FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: FIFO1B4IFG does not request an interrupt service..,1: FIFO1B4IFG requests an interrupt service routine" newline bitfld.long 0x0 8. "FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: FIFOFULLIFG does not request an interrupt..,1: FIFOFULLIFG requests an interrupt service routine" bitfld.long 0x0 1. "MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: MODRDYIFG does not request an interrupt service..,1: MODRDYIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "DAC0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 14. "DMADONEIFG,Sets DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is set" bitfld.long 0x0 13. "FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is set" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is set" bitfld.long 0x0 11. "FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is set" newline bitfld.long 0x0 10. "FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is set" bitfld.long 0x0 9. "FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is set" newline bitfld.long 0x0 8. "FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is set" bitfld.long 0x0 1. "MODRDYIFG,Sets MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "DAC0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 14. "DMADONEIFG,Clears DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is cleared" bitfld.long 0x0 13. "FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is cleared" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is cleared" bitfld.long 0x0 11. "FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is cleared" newline bitfld.long 0x0 10. "FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is cleared" bitfld.long 0x0 9. "FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is cleared" newline bitfld.long 0x0 8. "FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is cleared" bitfld.long 0x0 1. "MODRDYIFG,Clears MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is cleared" tree.end endif sif (cpuis("MSPM0G350*")) repeat 2. (list 0x0 0x1)(list ad:0x40019020 ad:0x4001904C) tree "DAC0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DAC0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DAC0_IMASK,Interrupt mask" bitfld.long 0x0 14. "DMADONEIFG,Masks DMADONEIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 13. "FIFOURUNIFG,Masks FIFOURUNIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 11. "FIFO3B4IFG,Masks FIFO3B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 10. "FIFO1B2IFG,Masks FIFO1B2IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 9. "FIFO1B4IFG,Masks FIFO1B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 8. "FIFOFULLIFG,Masks FIFOFULLIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 1. "MODRDYIFG,Masks MODRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long ($2+0x10)++0x3 line.long 0x0 "DAC0_RIS,Raw interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: DMA done condition did not occur,1: DMA done condition occurred" bitfld.long 0x0 13. "FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: FIFO underrun condition did not occur,1: FIFO underrun condition occurred" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: FIFO empty condition did not occur,1: FIFO empty condition occurred" bitfld.long 0x0 11. "FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: FIFO three fourth empty condition did not occur,1: FIFO three fourth empty condition occurred" newline bitfld.long 0x0 10. "FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: FIFO half empty condition did not occur,1: FIFO half empty condition occurred" bitfld.long 0x0 9. "FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: FIFO one fourth empty condition did not occur,1: FIFO one fourth empty condition occurred" newline bitfld.long 0x0 8. "FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: FIFO full condition did not occur,1: FIFO full condition occurred" bitfld.long 0x0 1. "MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: DAC module ready event did not occur,1: DAC module ready event occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DAC0_MIS,Masked interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: DMADONEIFG does not request an interrupt service..,1: DMADONEIFG requests an interrupt service routine" bitfld.long 0x0 13. "FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: FIFOURUNIFG does not request an interrupt..,1: FIFOURUNIFG requests an interrupt service routine" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: FIFOEMPTYIFG does not request an interrupt..,1: FIFOEMPTYIFG requests an interrupt service routine" bitfld.long 0x0 11. "FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: FIFO3B4IFG does not request an interrupt service..,1: FIFO3B4IFG requests an interrupt service routine" newline bitfld.long 0x0 10. "FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: FIFO1B2IFG does not request an interrupt service..,1: FIFO1B2IFG requests an interrupt service routine" bitfld.long 0x0 9. "FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: FIFO1B4IFG does not request an interrupt service..,1: FIFO1B4IFG requests an interrupt service routine" newline bitfld.long 0x0 8. "FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: FIFOFULLIFG does not request an interrupt..,1: FIFOFULLIFG requests an interrupt service routine" bitfld.long 0x0 1. "MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: MODRDYIFG does not request an interrupt service..,1: MODRDYIFG requests an interrupt service routine" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DAC0_ISET,Interrupt set" bitfld.long 0x0 14. "DMADONEIFG,Sets DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is set" bitfld.long 0x0 13. "FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is set" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is set" bitfld.long 0x0 11. "FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is set" newline bitfld.long 0x0 10. "FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is set" bitfld.long 0x0 9. "FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is set" newline bitfld.long 0x0 8. "FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is set" bitfld.long 0x0 1. "MODRDYIFG,Sets MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DAC0_ICLR,Interrupt clear" bitfld.long 0x0 14. "DMADONEIFG,Clears DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is cleared" bitfld.long 0x0 13. "FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is cleared" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is cleared" bitfld.long 0x0 11. "FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is cleared" newline bitfld.long 0x0 10. "FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is cleared" bitfld.long 0x0 9. "FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is cleared" newline bitfld.long 0x0 8. "FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is cleared" bitfld.long 0x0 1. "MODRDYIFG,Clears MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is cleared" tree.end repeat.end base ad:0x40018000 endif sif (cpuis("MSPM0G351*")) tree "DAC0_CPU_INT[%s]" base ad:0x40019020 rgroup.long 0x0++0x3 line.long 0x0 "DAC0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DAC0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 14. "DMADONEIFG,Masks DMADONEIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 13. "FIFOURUNIFG,Masks FIFOURUNIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 11. "FIFO3B4IFG,Masks FIFO3B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 10. "FIFO1B2IFG,Masks FIFO1B2IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 9. "FIFO1B4IFG,Masks FIFO1B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 8. "FIFOFULLIFG,Masks FIFOFULLIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 1. "MODRDYIFG,Masks MODRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "DAC0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: DMA done condition did not occur,1: DMA done condition occurred" bitfld.long 0x0 13. "FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: FIFO underrun condition did not occur,1: FIFO underrun condition occurred" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: FIFO empty condition did not occur,1: FIFO empty condition occurred" bitfld.long 0x0 11. "FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: FIFO three fourth empty condition did not occur,1: FIFO three fourth empty condition occurred" newline bitfld.long 0x0 10. "FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: FIFO half empty condition did not occur,1: FIFO half empty condition occurred" bitfld.long 0x0 9. "FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: FIFO one fourth empty condition did not occur,1: FIFO one fourth empty condition occurred" newline bitfld.long 0x0 8. "FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: FIFO full condition did not occur,1: FIFO full condition occurred" bitfld.long 0x0 1. "MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: DAC module ready event did not occur,1: DAC module ready event occurred" rgroup.long 0x18++0x3 line.long 0x0 "DAC0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: DMADONEIFG does not request an interrupt service..,1: DMADONEIFG requests an interrupt service routine" bitfld.long 0x0 13. "FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: FIFOURUNIFG does not request an interrupt..,1: FIFOURUNIFG requests an interrupt service routine" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: FIFOEMPTYIFG does not request an interrupt..,1: FIFOEMPTYIFG requests an interrupt service routine" bitfld.long 0x0 11. "FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: FIFO3B4IFG does not request an interrupt service..,1: FIFO3B4IFG requests an interrupt service routine" newline bitfld.long 0x0 10. "FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: FIFO1B2IFG does not request an interrupt service..,1: FIFO1B2IFG requests an interrupt service routine" bitfld.long 0x0 9. "FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: FIFO1B4IFG does not request an interrupt service..,1: FIFO1B4IFG requests an interrupt service routine" newline bitfld.long 0x0 8. "FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: FIFOFULLIFG does not request an interrupt..,1: FIFOFULLIFG requests an interrupt service routine" bitfld.long 0x0 1. "MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: MODRDYIFG does not request an interrupt service..,1: MODRDYIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "DAC0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 14. "DMADONEIFG,Sets DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is set" bitfld.long 0x0 13. "FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is set" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is set" bitfld.long 0x0 11. "FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is set" newline bitfld.long 0x0 10. "FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is set" bitfld.long 0x0 9. "FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is set" newline bitfld.long 0x0 8. "FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is set" bitfld.long 0x0 1. "MODRDYIFG,Sets MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "DAC0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 14. "DMADONEIFG,Clears DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is cleared" bitfld.long 0x0 13. "FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is cleared" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is cleared" bitfld.long 0x0 11. "FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is cleared" newline bitfld.long 0x0 10. "FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is cleared" bitfld.long 0x0 9. "FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is cleared" newline bitfld.long 0x0 8. "FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is cleared" bitfld.long 0x0 1. "MODRDYIFG,Clears MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is cleared" tree.end tree "DAC0_GEN_EVENT[%s]" base ad:0x40019050 rgroup.long 0x0++0x3 line.long 0x0 "DAC0_GEN_EVENT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DAC0_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 14. "DMADONEIFG,Masks DMADONEIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 13. "FIFOURUNIFG,Masks FIFOURUNIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 11. "FIFO3B4IFG,Masks FIFO3B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 10. "FIFO1B2IFG,Masks FIFO1B2IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 9. "FIFO1B4IFG,Masks FIFO1B4IFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 8. "FIFOFULLIFG,Masks FIFOFULLIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 1. "MODRDYIFG,Masks MODRDYIFG" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "DAC0_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: DMA done condition did not occur,1: DMA done condition occurred" bitfld.long 0x0 13. "FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: FIFO underrun condition did not occur,1: FIFO underrun condition occurred" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: FIFO empty condition did not occur,1: FIFO empty condition occurred" bitfld.long 0x0 11. "FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: FIFO three fourth empty condition did not occur,1: FIFO three fourth empty condition occurred" newline bitfld.long 0x0 10. "FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: FIFO half empty condition did not occur,1: FIFO half empty condition occurred" bitfld.long 0x0 9. "FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: FIFO one fourth empty condition did not occur,1: FIFO one fourth empty condition occurred" newline bitfld.long 0x0 8. "FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: FIFO full condition did not occur,1: FIFO full condition occurred" bitfld.long 0x0 1. "MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: DAC module ready event did not occur,1: DAC module ready event occurred" rgroup.long 0x18++0x3 line.long 0x0 "DAC0_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 14. "DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: DMADONEIFG does not request an interrupt service..,1: DMADONEIFG requests an interrupt service routine" bitfld.long 0x0 13. "FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: FIFOURUNIFG does not request an interrupt..,1: FIFOURUNIFG requests an interrupt service routine" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: FIFOEMPTYIFG does not request an interrupt..,1: FIFOEMPTYIFG requests an interrupt service routine" bitfld.long 0x0 11. "FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: FIFO3B4IFG does not request an interrupt service..,1: FIFO3B4IFG requests an interrupt service routine" newline bitfld.long 0x0 10. "FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: FIFO1B2IFG does not request an interrupt service..,1: FIFO1B2IFG requests an interrupt service routine" bitfld.long 0x0 9. "FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: FIFO1B4IFG does not request an interrupt service..,1: FIFO1B4IFG requests an interrupt service routine" newline bitfld.long 0x0 8. "FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: FIFOFULLIFG does not request an interrupt..,1: FIFOFULLIFG requests an interrupt service routine" bitfld.long 0x0 1. "MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: MODRDYIFG does not request an interrupt service..,1: MODRDYIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "DAC0_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 14. "DMADONEIFG,Sets DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is set" bitfld.long 0x0 13. "FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is set" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is set" bitfld.long 0x0 11. "FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is set" newline bitfld.long 0x0 10. "FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is set" bitfld.long 0x0 9. "FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is set" newline bitfld.long 0x0 8. "FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is set" bitfld.long 0x0 1. "MODRDYIFG,Sets MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "DAC0_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 14. "DMADONEIFG,Clears DMADONEIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to DMADONEIFG is cleared" bitfld.long 0x0 13. "FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOURUNIFG is cleared" newline bitfld.long 0x0 12. "FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOEMPTYIFG is cleared" bitfld.long 0x0 11. "FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO3B4IFG is cleared" newline bitfld.long 0x0 10. "FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B2IFG is cleared" bitfld.long 0x0 9. "FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFO1B4IFG is cleared" newline bitfld.long 0x0 8. "FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to FIFOFULLIFG is cleared" bitfld.long 0x0 1. "MODRDYIFG,Clears MODRDYIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to MODRDYIFG is cleared" tree.end endif tree.end endif tree "DEBUGSS (Debug Subsystem)" base ad:0x0 sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "DEBUGSS" base ad:0x400C7000 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) tree "DEBUGSS_PINCM[%s]" base ad:0x400C7004 group.long 0x0++0x7 line.long 0x0 "DEBUGSS_SWCLK,SWCLK" bitfld.long 0x0 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x0 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x0 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x0 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x0 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x0 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x0 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x0 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x0 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x0 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x0 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x0 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." line.long 0x4 "DEBUGSS_SWDIO,SWDIO" bitfld.long 0x4 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x4 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x4 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x4 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x4 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x4 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x4 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x4 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x4 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x4 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x4 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x4 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." tree.end newline group.long 0x480++0x3 newline line.long 0x0 "DEBUGSS_CPU_CONNECT_0,CPU Connect" bitfld.long 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." endif rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0G150*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0G151*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0G310*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0G350*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0G351*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0L110*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0L111*")) tree "DEBUGSS" base ad:0x400C7000 tree "DEBUGSS_CPU_INT[%s]" base ad:0x400C8020 rgroup.long 0x0++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x10++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x18++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x20++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x28++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" tree.end base ad:0x400C7000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0L122*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0L130*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0L134*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif sif (cpuis("MSPM0L222*")) tree "DEBUGSS" base ad:0x400C7000 rgroup.long 0x1020++0x3 line.long 0x0 "DEBUGSS_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "DEBUGSS_IMASK,Interrupt mask" bitfld.long 0x0 3. "PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "PWRUPIFG,Masks PWRUPIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "RXIFG,Masks RXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "TXIFG,Masks TXIFG in MIS register" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "DEBUGSS_RIS,Raw interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 2. "PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: PWRUPIFG did not occur,1: PWRUPIFG occurred" newline bitfld.long 0x0 1. "RXIFG,Raw interrupt status for RXIFG" "0: RXIFG did not occur,1: RXIFG occurred" newline bitfld.long 0x0 0. "TXIFG,Raw interrupt status for TXIFG" "0: TXIFG did not occur,1: TXIFG occurred" rgroup.long 0x1038++0x3 line.long 0x0 "DEBUGSS_MIS,Masked interrupt status" bitfld.long 0x0 3. "PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 2. "PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: PWRUPIFG did not request an interrupt service..,1: PWRUPIFG requests an interrupt service routine" newline bitfld.long 0x0 1. "RXIFG,Masked interrupt status for RXIFG" "0: RXIFG did not request an interrupt service routine,1: RXIFG requests an interrupt service routine" newline bitfld.long 0x0 0. "TXIFG,Masked interrupt status for TXIFG" "0: TXIFG did not request an interrupt service routine,1: TXIFG requests an interrupt service routine" wgroup.long 0x1040++0x3 line.long 0x0 "DEBUGSS_ISET,Interrupt set" bitfld.long 0x0 3. "PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 2. "PWRUPIFG,Sets PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is set" newline bitfld.long 0x0 1. "RXIFG,Sets RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is set" newline bitfld.long 0x0 0. "TXIFG,Sets TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is set" wgroup.long 0x1048++0x3 line.long 0x0 "DEBUGSS_ICLR,Interrupt clear" bitfld.long 0x0 3. "PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 2. "PWRUPIFG,Clears PWRUPIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to PWRUPIFG is cleared" newline bitfld.long 0x0 1. "RXIFG,Clears RXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to RXIFG is cleared" newline bitfld.long 0x0 0. "TXIFG,Clears TXIFG in RIS register" "0: Writing a 0 has no effect,1: RIS bit corresponding to TXIFG is cleared" rgroup.long 0x10E0++0x3 line.long 0x0 "DEBUGSS_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral events" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0xB line.long 0x0 "DEBUGSS_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" line.long 0x4 "DEBUGSS_TXD,Transmit data register" line.long 0x8 "DEBUGSS_TXCTL,Transmit control register" hexmask.long 0x8 1.--31. 1. "TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW." newline bitfld.long 0x8 0. "TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: TXD is empty,1: TXD is full" group.long 0x1108++0x7 line.long 0x0 "DEBUGSS_RXD,Receive data register" line.long 0x4 "DEBUGSS_RXCTL,Receive control register" hexmask.long.byte 0x4 1.--7. 1. "RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW." newline rbitfld.long 0x4 0. "RECEIVE,Indicates SW write to the DSSM.RXD register." "0: RXD empty,1: RXD full" rgroup.long 0x1200++0x3 line.long 0x0 "DEBUGSS_SPECIAL_AUTH,Special enable authorization register" bitfld.long 0x0 6. "PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable PWR-AP,1: Enable PWR-AP" newline bitfld.long 0x0 5. "AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: Disable AHB-AP,1: Enable AHB-AP" newline bitfld.long 0x0 4. "CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the Config-AP." "0: Disable CFG-AP,1: Enable CFG-AP" newline bitfld.long 0x0 3. "ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable ET+ -AP,1: Enable ET+ -AP" newline bitfld.long 0x0 2. "DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: Disable DFT-TAP,1: Enable DFT-TAP" newline bitfld.long 0x0 1. "SWDPORTEN,When asserted the SW-DP functions normally." "0: Disable SWD port,1: Enable SWD port" newline bitfld.long 0x0 0. "SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: Disable SEC-AP,1: Enable SEC-AP" rgroup.long 0x1210++0x3 line.long 0x0 "DEBUGSS_APP_AUTH,Application CPU0 authorization register" bitfld.long 0x0 3. "SPNIDEN,Secure non-invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 2. "SPIDEN,Secure invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" newline bitfld.long 0x0 1. "NIDEN,Controls non-invasive debug enable." "0: Non-invasive debug disabled,1: Non-invasive debug enabled" newline bitfld.long 0x0 0. "DBGEN,Controls invasive debug enable." "0: Invasive debug disabled,1: Invasive debug enabled" tree.end endif tree.end tree "DMA (Direct Memory Access)" base ad:0x4042A000 group.long 0x400++0x7 line.long 0x0 "DMA_FSUB_0,Subscriber Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif line.long 0x4 "DMA_FSUB_1,Subscriber Port 1" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L110*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif group.long 0x444++0x3 line.long 0x0 "DMA_FPUB_1,Publisher Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) group.long 0x480++0x3 line.long 0x0 "DMA_CPU_CONNECT_0,CPU Connect" bitfld.long 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." bitfld.long 0x0 0. "NWPW_CONN,NWPW connect bit." "0: The NWPW is not connected.,1: The NWPW is connected." tree "DMA_DMATRIG[%s]" base ad:0x4042B110 group.long 0x0++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end tree "DMA_DMACHAN[%s]" base ad:0x4042B200 group.long 0x0++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end endif group.long 0x1018++0x3 line.long 0x0 "DMA_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." rgroup.long 0x10E0++0x3 line.long 0x0 "DMA_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to generic event INT_EVENT[1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to interrupt event INT_EVENT[0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "DMA_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the DMA: number of DMA channel minus one (e.g. 0->1ch 2->3ch 15->16ch)." newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x3 line.long 0x0 "DMA_DMAPRIO,DMA Channel Priority Control" bitfld.long 0x0 16.--17. "BURSTSZ,Define the burst size of a block transfer before the priority is re-evaluated" "0: There is no burst size the whole block transfer..,1: The burst size is 8 after 8 transfers the block..,2: The burst size is 16 after 16 transfers the..,3: The burst size is 32 after 32 transfers the.." bitfld.long 0x0 0. "ROUNDROBIN,Round robin. This bit enables the round-robin DMA channel priorities." "0: Roundrobin priority disabled DMA channel..,1: Roundrobin priority enabled DMA channel priority.." sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G110*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G110*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G110*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G150*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G150*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G150*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G151*")) tree "DMA_CPU_INT[%s]" base ad:0x4042B020 rgroup.long 0x0++0x3 line.long 0x0 "DMA_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end tree "DMA_GEN_EVENT[%s]" base ad:0x4042B050 rgroup.long 0x0++0x3 line.long 0x0 "DMA_GEN_EVENT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0G151*")) repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128 ad:0x4042B12C ad:0x4042B130 ad:0x4042B134 ad:0x4042B138 ad:0x4042B13C) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G151*")) repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260 ad:0x4042B270 ad:0x4042B280 ad:0x4042B290 ad:0x4042B2A0 ad:0x4042B2B0) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,1: Gather mode will read a data from an address..,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--14. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word long word or long-long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit),4: Source data width is LONG-LONG-WORD (128-bit),?,?,?" bitfld.long 0x0 8.--10. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word long word or long-long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit),4: Source data width is LONG-LONG-WORD (128-bit),?,?,?" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 2.--3. "DMAAUTOEN,Automatic DMA channel enable on DMASA DMADA DMASZ register write." "0: No automatic DMA enable,1: Automatic DMA enable on DMASA register write.,2: Automatic DMA enable on DMADA register write.,3: Automatic DMA enable on DMASZ register write." newline bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G310*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G310*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G310*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G350*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G350*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G350*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G351*")) tree "DMA_CPU_INT[%s]" base ad:0x4042B020 rgroup.long 0x0++0x3 line.long 0x0 "DMA_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end tree "DMA_GEN_EVENT[%s]" base ad:0x4042B050 rgroup.long 0x0++0x3 line.long 0x0 "DMA_GEN_EVENT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 21. "PREIRQCH5,Pre-IRQ for Channel 5. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 20. "PREIRQCH4,Pre-IRQ for Channel 4. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 19. "PREIRQCH3,Pre-IRQ for Channel 3. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 11. "DMACH11,DMA Channel 11 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "DMACH10,DMA Channel 10 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "DMACH9,DMA Channel 9 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMACH8,DMA Channel 8 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "DMACH7,DMA Channel 7 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0G351*")) repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128 ad:0x4042B12C ad:0x4042B130 ad:0x4042B134 ad:0x4042B138 ad:0x4042B13C) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0G351*")) repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260 ad:0x4042B270 ad:0x4042B280 ad:0x4042B290 ad:0x4042B2A0 ad:0x4042B2B0) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,1: Gather mode will read a data from an address..,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--14. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word long word or long-long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit),4: Source data width is LONG-LONG-WORD (128-bit),?,?,?" bitfld.long 0x0 8.--10. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word long word or long-long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit),4: Source data width is LONG-LONG-WORD (128-bit),?,?,?" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 2.--3. "DMAAUTOEN,Automatic DMA channel enable on DMASA DMADA DMASZ register write." "0: No automatic DMA enable,1: Automatic DMA enable on DMASA register write.,2: Automatic DMA enable on DMADA register write.,3: Automatic DMA enable on DMASZ register write." newline bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L110*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L110*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L110*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L111*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L111*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L111*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L122*")) tree "DMA_CPU_INT[%s]" base ad:0x4042B020 rgroup.long 0x0++0x3 line.long 0x0 "DMA_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end tree "DMA_GEN_EVENT[%s]" base ad:0x4042B050 rgroup.long 0x0++0x3 line.long 0x0 "DMA_GEN_EVENT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0L122*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L122*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L130*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L130*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L130*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L134*")) repeat 2. (list 0x0 0x1)(list ad:0x4042B020 ad:0x4042B04C) tree "DMA_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "DMA_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "DMA_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long ($2+0x10)++0x3 line.long 0x0 "DMA_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long ($2+0x18)++0x3 line.long 0x0 "DMA_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long ($2+0x20)++0x3 line.long 0x0 "DMA_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long ($2+0x28)++0x3 line.long 0x0 "DMA_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L134*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L134*")) repeat 3. (list 0x0 0x1 0x2)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L222*")) tree "DMA_CPU_INT[%s]" base ad:0x4042B020 rgroup.long 0x0++0x3 line.long 0x0 "DMA_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end tree "DMA_GEN_EVENT[%s]" base ad:0x4042B050 rgroup.long 0x0++0x3 line.long 0x0 "DMA_GEN_EVENT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "DMA_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" rgroup.long 0x10++0x3 line.long 0x0 "DMA_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "DMA_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "DMA_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "DMA_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 25. "DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 24. "ADDRERR,DMA address error SRC address not reachable." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 18. "PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 17. "PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" newline bitfld.long 0x0 16. "PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: Clear interrupt mask bit,1: Set interrupt mask bit" bitfld.long 0x0 6. "DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0L222*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B110 ad:0x4042B114 ad:0x4042B118 ad:0x4042B11C ad:0x4042B120 ad:0x4042B124 ad:0x4042B128) tree "DMA_DMATRIG[$1]" base $2 group.long ($2)++0x3 line.long 0x0 "DMA_DMATCTL,DMA Trigger Select" bitfld.long 0x0 7. "DMATINT,DMA Trigger by Internal Channel" "0: DMATSEL will define external trigger select as..,1: DMATSEL will define internal channel as transfer.." hexmask.long.byte 0x0 0.--5. 1. "DMATSEL,DMA Trigger Select" tree.end repeat.end base ad:0x4042A000 endif sif (cpuis("MSPM0L222*")) repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0x4042B200 ad:0x4042B210 ad:0x4042B220 ad:0x4042B230 ad:0x4042B240 ad:0x4042B250 ad:0x4042B260) tree "DMA_DMACHAN[$1]" base $2 group.long ($2)++0xF line.long 0x0 "DMA_DMACTL,DMA Channel Control" bitfld.long 0x0 28.--29. "DMATM,DMA transfer mode register" "0: Single transfer. Each transfers requires a new..,1: Block transfer. Each trigger transfers the..,2: Repeated single transfer. Each transfers..,3: Repeated block transfer. Each trigger transfers.." bitfld.long 0x0 24.--25. "DMAEM,DMA extended mode" "0: Normal mode is related to transfers from SRC to..,?,2: Fill mode will copy the SA register content as..,3: Table mode will read an address and data value.." newline hexmask.long.byte 0x0 20.--23. 1. "DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1.." hexmask.long.byte 0x0 16.--19. 1. "DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a.." newline bitfld.long 0x0 12.--13. "DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: Destination data width is BYTE (8-bit),1: Destination data width is HALF-WORD (16-bit),2: Destination data width is WORD (32-bit),3: Destination data width is LONG-WORD (64-bit)" bitfld.long 0x0 8.--9. "DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: Source data width is BYTE (8-bit),1: Source data width is HALF-WORD (16-bit),2: Source data width is WORD (32-bit),3: Source data width is LONG-WORD (64-bit)" newline bitfld.long 0x0 4.--6. "DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: Pre-IRQ event disabled.,1: Issure Pre-IRQ event when DMASZ=1,2: Issure Pre-IRQ event when DMASZ=2,3: Issure Pre-IRQ event when DMASZ=4,4: Issure Pre-IRQ event when DMASZ=8,5: Issure Pre-IRQ event when DMASZ=32,6: Issure Pre-IRQ event when DMASZ=64,7: Issure Pre-IRQ event when DMASZ reached the half.." bitfld.long 0x0 1. "DMAEN,DMA enable" "0: DMA channel disabled,1: DMA channel enabled" newline bitfld.long 0x0 0. "DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: Default read value,1: DMA transfer request (start DMA)" line.long 0x4 "DMA_DMASA,DMA Channel Source Address" hexmask.long 0x4 0.--31. 1. "ADDR,DMA Channel Source Address" line.long 0x8 "DMA_DMADA,DMA Channel Destination Address" hexmask.long 0x8 0.--31. 1. "ADDR,DMA Channel Destination Address" line.long 0xC "DMA_DMASZ,DMA Channel Size" hexmask.long.word 0xC 0.--15. 1. "SIZE,DMA Channel Size in number of transfers" tree.end repeat.end base ad:0x4042A000 endif tree.end tree "EVENTLP" base ad:0x400C9000 rgroup.long 0xF8++0x7 line.long 0x0 "EVENTLP_PUBCFG_DESC_EX,Extended Module Description" hexmask.long.byte 0x0 24.--31. 1. "NUM_EXPORT,Number of export ports available in this EventManager instantiation" hexmask.long.byte 0x0 16.--23. 1. "NUM_IMPORT,Number of import ports available in this EventManager instantiation" hexmask.long.byte 0x0 8.--15. 1. "NUM_DUAL_CHANNEL,Number of dual channels contained in this instance of event manager" hexmask.long.byte 0x0 0.--7. 1. "NUM_SINGLE_CHANNEL,Number of single channels contained in this instance of event manager" line.long 0x4 "EVENTLP_PUBCFG_DESC,Module Description" hexmask.long.word 0x4 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x4 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" hexmask.long.byte 0x4 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor rev of the IP" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 13. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end endif tree.end endif sif (cpuis("MSPM0G150*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 26. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" bitfld.long 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 26. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" bitfld.byte 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end tree.end endif sif (cpuis("MSPM0G151*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT,Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT,Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM,CPU connect register" tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT,Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT,Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM,CPU connect register" tree.end endif sif (cpuis("MSPM0G310*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 26. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" bitfld.long 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 26. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" bitfld.byte 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end tree.end endif sif (cpuis("MSPM0G350*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 26. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" bitfld.long 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 26. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" bitfld.byte 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end tree.end endif sif (cpuis("MSPM0G351*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT,Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT,Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM,CPU connect register" tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT,Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT,Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM,CPU connect register" tree.end endif sif (cpuis("MSPM0L110*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 17. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 13. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 17. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 13. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end endif sif (cpuis("MSPM0L111*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT,Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT,Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM,CPU connect register" tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT,Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT,Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM,CPU connect register" tree.end endif sif (cpuis("MSPM0L122*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 25. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 21. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 27. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 25. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 21. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 27. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end endif sif (cpuis("MSPM0L130*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 17. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 13. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 17. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 13. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end endif sif (cpuis("MSPM0L134*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 17. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 13. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 17. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 13. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end endif sif (cpuis("MSPM0L222*")) tree "EVENTLP_PUBCFG_FSUB[%s]" base ad:0x400C9100 repeat 25. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 repeat 21. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 repeat 27. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 repeat 25. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 repeat 21. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end tree.end tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 repeat 27. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" repeat.end tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "EVENTLP_PUBCFG_FPUB[%s]" base ad:0x400C9300 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 26. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end endif tree.end endif tree "EVENTLP_PUBCFG_EXPORT[%s]" base ad:0x400C9500 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_EXPORT_PORT,Export channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for export side to connect to" tree.end tree "EVENTLP_PUBCFG_IMPORT[%s]" base ad:0x400C9700 group.long 0x0++0x3 line.long 0x0 "EVENTLP_PUBCFG_IMPORT_PORT,Import channel ID registe" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for import side to connect to" tree.end sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "EVENTLP_PUBCFG_CPU_CONNECT[%s]" base ad:0x400C9900 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 12. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "EVENTLP_PUBCFG_CPU_NUM[$1],CPU connect register" bitfld.long 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end endif tree.end endif rgroup.long 0x10F8++0x7 line.long 0x0 "EVENTLP_SECCFG_DESC_EX,Extended Module Description" hexmask.long.byte 0x0 24.--31. 1. "NUM_EXPORT,Number of export ports available in this EventManager instantiation" hexmask.long.byte 0x0 16.--23. 1. "NUM_IMPORT,Number of import ports available in this EventManager instantiation" hexmask.long.byte 0x0 8.--15. 1. "NUM_DUAL_CHANNEL,Number of dual channels contained in this instance of event manager" hexmask.long.byte 0x0 0.--7. 1. "NUM_SINGLE_CHANNEL,Number of single channels contained in this instance of event manager" line.long 0x4 "EVENTLP_SECCFG_DESC,Module Description" hexmask.long.word 0x4 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x4 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" hexmask.long.byte 0x4 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor rev of the IP" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "EVENTLP_SECCFG_FSUB[%s]" base ad:0x400CA100 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 13. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FSUB_PORT[$1],Subscriber channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for subscriber to connect to" repeat.end endif tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "EVENTLP_SECCFG_FPUB[%s]" base ad:0x400CA180 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 10. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 26. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_FPUB_PORT[$1],Publisher channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for publisher to connect to" repeat.end endif tree.end endif tree "EVENTLP_SECCFG_EXPORT[%s]" base ad:0x400CA200 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_EXPORT_PORT,Export channel ID register" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for export side to connect to" tree.end tree "EVENTLP_SECCFG_IMPORT[%s]" base ad:0x400CA280 group.byte 0x0++0x0 line.byte 0x0 "EVENTLP_SECCFG_IMPORT_PORT,Import channel ID registe" hexmask.byte 0x0 0.--7. 1. "CHANID,Channel ID for import side to connect to" tree.end sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "EVENTLP_SECCFG_CPU_CONNECT[%s]" base ad:0x400CA300 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 12. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "EVENTLP_SECCFG_CPU_NUM[$1],CPU connect register" bitfld.byte 0x0 1. "CPUSS0_CONN,CPUSS0 connect bit." "0: The CPU is not connected.,1: The CPU is connected." repeat.end endif tree.end endif group.byte 0x1400++0x0 line.byte 0x0 "EVENTLP_CTL,Event Manager control register" hexmask.byte 0x0 0.--3. 1. "OVRWR_EN,Enable overwrite of config even if resources are already configured. By default a configuration cannot be overwritten." tree "EVENTLP_IMPEXPCFG_EXPORT[%s]" base ad:0x400CB000 group.long 0x0++0x3 line.long 0x0 "EVENTLP_IMPEXPCFG_EXPORT_PORT,Export channel ID register" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for import side to connect to" tree.end tree "EVENTLP_IMPEXPCFG_IMPORT[%s]" base ad:0x400CB200 group.long 0x0++0x3 line.long 0x0 "EVENTLP_IMPEXPCFG_IMPORT_PORT,Import channel ID registe" hexmask.long.byte 0x0 0.--7. 1. "CHANID,Channel ID for import side to connect to" tree.end tree "EVENTLP_LMGMT_SFTYDIAG[%s]" base ad:0x400CAC00 wgroup.long 0xEC++0x303 line.long 0x0 "EVENTLP_DIAGPAR192,Diagnostic Parity Register 768" bitfld.long 0x0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x4 "EVENTLP_DIAGPAR191,Diagnostic Parity Register 191" bitfld.long 0x4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x8 "EVENTLP_DIAGPAR190,Diagnostic Parity Register 190" bitfld.long 0x8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xC "EVENTLP_DIAGPAR189,Diagnostic Parity Register 189" bitfld.long 0xC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x10 "EVENTLP_DIAGPAR188,Diagnostic Parity Register 188" bitfld.long 0x10 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x14 "EVENTLP_DIAGPAR187,Diagnostic Parity Register 187" bitfld.long 0x14 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x18 "EVENTLP_DIAGPAR186,Diagnostic Parity Register 186" bitfld.long 0x18 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1C "EVENTLP_DIAGPAR185,Diagnostic Parity Register 185" bitfld.long 0x1C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x20 "EVENTLP_DIAGPAR184,Diagnostic Parity Register 184" bitfld.long 0x20 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x24 "EVENTLP_DIAGPAR183,Diagnostic Parity Register 183" bitfld.long 0x24 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x28 "EVENTLP_DIAGPAR182,Diagnostic Parity Register 182" bitfld.long 0x28 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2C "EVENTLP_DIAGPAR181,Diagnostic Parity Register 181" bitfld.long 0x2C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x30 "EVENTLP_DIAGPAR180,Diagnostic Parity Register 180" bitfld.long 0x30 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x34 "EVENTLP_DIAGPAR179,Diagnostic Parity Register 179" bitfld.long 0x34 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x38 "EVENTLP_DIAGPAR178,Diagnostic Parity Register 178" bitfld.long 0x38 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x3C "EVENTLP_DIAGPAR177,Diagnostic Parity Register 177" bitfld.long 0x3C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x40 "EVENTLP_DIAGPAR176,Diagnostic Parity Register 176" bitfld.long 0x40 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x44 "EVENTLP_DIAGPAR175,Diagnostic Parity Register 175" bitfld.long 0x44 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x48 "EVENTLP_DIAGPAR174,Diagnostic Parity Register 174" bitfld.long 0x48 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x4C "EVENTLP_DIAGPAR173,Diagnostic Parity Register 173" bitfld.long 0x4C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x50 "EVENTLP_DIAGPAR172,Diagnostic Parity Register 172" bitfld.long 0x50 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x54 "EVENTLP_DIAGPAR171,Diagnostic Parity Register 171" bitfld.long 0x54 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x58 "EVENTLP_DIAGPAR170,Diagnostic Parity Register 170" bitfld.long 0x58 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x5C "EVENTLP_DIAGPAR169,Diagnostic Parity Register 169" bitfld.long 0x5C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x60 "EVENTLP_DIAGPAR168,Diagnostic Parity Register 168" bitfld.long 0x60 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x64 "EVENTLP_DIAGPAR167,Diagnostic Parity Register 167" bitfld.long 0x64 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x68 "EVENTLP_DIAGPAR166,Diagnostic Parity Register 166" bitfld.long 0x68 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x6C "EVENTLP_DIAGPAR165,Diagnostic Parity Register 165" bitfld.long 0x6C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x70 "EVENTLP_DIAGPAR164,Diagnostic Parity Register 164" bitfld.long 0x70 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x74 "EVENTLP_DIAGPAR163,Diagnostic Parity Register 163" bitfld.long 0x74 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x78 "EVENTLP_DIAGPAR162,Diagnostic Parity Register 162" bitfld.long 0x78 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x7C "EVENTLP_DIAGPAR161,Diagnostic Parity Register 161" bitfld.long 0x7C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x80 "EVENTLP_DIAGPAR160,Diagnostic Parity Register 160" bitfld.long 0x80 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x84 "EVENTLP_DIAGPAR159,Diagnostic Parity Register 159" bitfld.long 0x84 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x88 "EVENTLP_DIAGPAR158,Diagnostic Parity Register 158" bitfld.long 0x88 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x8C "EVENTLP_DIAGPAR157,Diagnostic Parity Register 157" bitfld.long 0x8C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x90 "EVENTLP_DIAGPAR156,Diagnostic Parity Register 156" bitfld.long 0x90 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x94 "EVENTLP_DIAGPAR155,Diagnostic Parity Register 155" bitfld.long 0x94 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x98 "EVENTLP_DIAGPAR154,Diagnostic Parity Register 154" bitfld.long 0x98 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x9C "EVENTLP_DIAGPAR153,Diagnostic Parity Register 153" bitfld.long 0x9C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xA0 "EVENTLP_DIAGPAR152,Diagnostic Parity Register 152" bitfld.long 0xA0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xA4 "EVENTLP_DIAGPAR151,Diagnostic Parity Register 151" bitfld.long 0xA4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xA8 "EVENTLP_DIAGPAR150,Diagnostic Parity Register 150" bitfld.long 0xA8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xAC "EVENTLP_DIAGPAR149,Diagnostic Parity Register 149" bitfld.long 0xAC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xB0 "EVENTLP_DIAGPAR148,Diagnostic Parity Register 148" bitfld.long 0xB0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xB4 "EVENTLP_DIAGPAR147,Diagnostic Parity Register 147" bitfld.long 0xB4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xB8 "EVENTLP_DIAGPAR146,Diagnostic Parity Register 146" bitfld.long 0xB8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xBC "EVENTLP_DIAGPAR145,Diagnostic Parity Register 145" bitfld.long 0xBC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xC0 "EVENTLP_DIAGPAR144,Diagnostic Parity Register 144" bitfld.long 0xC0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xC4 "EVENTLP_DIAGPAR143,Diagnostic Parity Register 143" bitfld.long 0xC4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xC8 "EVENTLP_DIAGPAR142,Diagnostic Parity Register 142" bitfld.long 0xC8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xCC "EVENTLP_DIAGPAR141,Diagnostic Parity Register 141" bitfld.long 0xCC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xD0 "EVENTLP_DIAGPAR140,Diagnostic Parity Register 140" bitfld.long 0xD0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xD4 "EVENTLP_DIAGPAR139,Diagnostic Parity Register 139" bitfld.long 0xD4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xD8 "EVENTLP_DIAGPAR138,Diagnostic Parity Register 138" bitfld.long 0xD8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xDC "EVENTLP_DIAGPAR137,Diagnostic Parity Register 137" bitfld.long 0xDC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xE0 "EVENTLP_DIAGPAR136,Diagnostic Parity Register 136" bitfld.long 0xE0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xE4 "EVENTLP_DIAGPAR135,Diagnostic Parity Register 135" bitfld.long 0xE4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xE8 "EVENTLP_DIAGPAR134,Diagnostic Parity Register 134" bitfld.long 0xE8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xEC "EVENTLP_DIAGPAR133,Diagnostic Parity Register 133" bitfld.long 0xEC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xF0 "EVENTLP_DIAGPAR132,Diagnostic Parity Register 132" bitfld.long 0xF0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xF4 "EVENTLP_DIAGPAR131,Diagnostic Parity Register 131" bitfld.long 0xF4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xF8 "EVENTLP_DIAGPAR130,Diagnostic Parity Register 130" bitfld.long 0xF8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0xFC "EVENTLP_DIAGPAR129,Diagnostic Parity Register 129" bitfld.long 0xFC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x100 "EVENTLP_DIAGPAR128,Diagnostic Parity Register 128" bitfld.long 0x100 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x104 "EVENTLP_DIAGPAR127,Diagnostic Parity Register 127" bitfld.long 0x104 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x108 "EVENTLP_DIAGPAR126,Diagnostic Parity Register 126" bitfld.long 0x108 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x10C "EVENTLP_DIAGPAR125,Diagnostic Parity Register 125" bitfld.long 0x10C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x110 "EVENTLP_DIAGPAR124,Diagnostic Parity Register 124" bitfld.long 0x110 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x114 "EVENTLP_DIAGPAR123,Diagnostic Parity Register 123" bitfld.long 0x114 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x118 "EVENTLP_DIAGPAR122,Diagnostic Parity Register 122" bitfld.long 0x118 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x11C "EVENTLP_DIAGPAR121,Diagnostic Parity Register 121" bitfld.long 0x11C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x120 "EVENTLP_DIAGPAR120,Diagnostic Parity Register 120" bitfld.long 0x120 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x124 "EVENTLP_DIAGPAR119,Diagnostic Parity Register 119" bitfld.long 0x124 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x128 "EVENTLP_DIAGPAR118,Diagnostic Parity Register 118" bitfld.long 0x128 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x12C "EVENTLP_DIAGPAR117,Diagnostic Parity Register 117" bitfld.long 0x12C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x130 "EVENTLP_DIAGPAR116,Diagnostic Parity Register 116" bitfld.long 0x130 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x134 "EVENTLP_DIAGPAR115,Diagnostic Parity Register 115" bitfld.long 0x134 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x138 "EVENTLP_DIAGPAR114,Diagnostic Parity Register 114" bitfld.long 0x138 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x13C "EVENTLP_DIAGPAR113,Diagnostic Parity Register 113" bitfld.long 0x13C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x140 "EVENTLP_DIAGPAR112,Diagnostic Parity Register 112" bitfld.long 0x140 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x144 "EVENTLP_DIAGPAR111,Diagnostic Parity Register 111" bitfld.long 0x144 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x148 "EVENTLP_DIAGPAR110,Diagnostic Parity Register 110" bitfld.long 0x148 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x14C "EVENTLP_DIAGPAR109,Diagnostic Parity Register 109" bitfld.long 0x14C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x150 "EVENTLP_DIAGPAR108,Diagnostic Parity Register 108" bitfld.long 0x150 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x154 "EVENTLP_DIAGPAR107,Diagnostic Parity Register 107" bitfld.long 0x154 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x158 "EVENTLP_DIAGPAR106,Diagnostic Parity Register 106" bitfld.long 0x158 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x15C "EVENTLP_DIAGPAR105,Diagnostic Parity Register 105" bitfld.long 0x15C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x160 "EVENTLP_DIAGPAR104,Diagnostic Parity Register 104" bitfld.long 0x160 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x164 "EVENTLP_DIAGPAR103,Diagnostic Parity Register 103" bitfld.long 0x164 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x168 "EVENTLP_DIAGPAR102,Diagnostic Parity Register 102" bitfld.long 0x168 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x16C "EVENTLP_DIAGPAR101,Diagnostic Parity Register 101" bitfld.long 0x16C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x170 "EVENTLP_DIAGPAR100,Diagnostic Parity Register 100" bitfld.long 0x170 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x174 "EVENTLP_DIAGPAR99,Diagnostic Parity Register 99" bitfld.long 0x174 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x178 "EVENTLP_DIAGPAR98,Diagnostic Parity Register 98" bitfld.long 0x178 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x17C "EVENTLP_DIAGPAR97,Diagnostic Parity Register 97" bitfld.long 0x17C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x180 "EVENTLP_DIAGPAR96,Diagnostic Parity Register 96" bitfld.long 0x180 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x184 "EVENTLP_DIAGPAR95,Diagnostic Parity Register 95" bitfld.long 0x184 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x188 "EVENTLP_DIAGPAR94,Diagnostic Parity Register 94" bitfld.long 0x188 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x18C "EVENTLP_DIAGPAR93,Diagnostic Parity Register 93" bitfld.long 0x18C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x190 "EVENTLP_DIAGPAR92,Diagnostic Parity Register 92" bitfld.long 0x190 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x194 "EVENTLP_DIAGPAR91,Diagnostic Parity Register 91" bitfld.long 0x194 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x198 "EVENTLP_DIAGPAR90,Diagnostic Parity Register 90" bitfld.long 0x198 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x19C "EVENTLP_DIAGPAR89,Diagnostic Parity Register 89" bitfld.long 0x19C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1A0 "EVENTLP_DIAGPAR88,Diagnostic Parity Register 88" bitfld.long 0x1A0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1A4 "EVENTLP_DIAGPAR87,Diagnostic Parity Register 87" bitfld.long 0x1A4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1A8 "EVENTLP_DIAGPAR86,Diagnostic Parity Register 86" bitfld.long 0x1A8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1AC "EVENTLP_DIAGPAR85,Diagnostic Parity Register 85" bitfld.long 0x1AC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1B0 "EVENTLP_DIAGPAR84,Diagnostic Parity Register 84" bitfld.long 0x1B0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1B4 "EVENTLP_DIAGPAR83,Diagnostic Parity Register 83" bitfld.long 0x1B4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1B8 "EVENTLP_DIAGPAR82,Diagnostic Parity Register 82" bitfld.long 0x1B8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1BC "EVENTLP_DIAGPAR81,Diagnostic Parity Register 81" bitfld.long 0x1BC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1C0 "EVENTLP_DIAGPAR80,Diagnostic Parity Register 80" bitfld.long 0x1C0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1C4 "EVENTLP_DIAGPAR79,Diagnostic Parity Register 79" bitfld.long 0x1C4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1C8 "EVENTLP_DIAGPAR78,Diagnostic Parity Register 78" bitfld.long 0x1C8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1CC "EVENTLP_DIAGPAR77,Diagnostic Parity Register 77" bitfld.long 0x1CC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1D0 "EVENTLP_DIAGPAR76,Diagnostic Parity Register 76" bitfld.long 0x1D0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1D4 "EVENTLP_DIAGPAR75,Diagnostic Parity Register 75" bitfld.long 0x1D4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1D8 "EVENTLP_DIAGPAR74,Diagnostic Parity Register 74" bitfld.long 0x1D8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1DC "EVENTLP_DIAGPAR73,Diagnostic Parity Register 73" bitfld.long 0x1DC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1E0 "EVENTLP_DIAGPAR72,Diagnostic Parity Register 72" bitfld.long 0x1E0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1E4 "EVENTLP_DIAGPAR71,Diagnostic Parity Register 71" bitfld.long 0x1E4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1E8 "EVENTLP_DIAGPAR70,Diagnostic Parity Register 70" bitfld.long 0x1E8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1EC "EVENTLP_DIAGPAR69,Diagnostic Parity Register 69" bitfld.long 0x1EC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1F0 "EVENTLP_DIAGPAR68,Diagnostic Parity Register 68" bitfld.long 0x1F0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1F4 "EVENTLP_DIAGPAR67,Diagnostic Parity Register 67" bitfld.long 0x1F4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1F8 "EVENTLP_DIAGPAR66,Diagnostic Parity Register 66" bitfld.long 0x1F8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x1FC "EVENTLP_DIAGPAR65,Diagnostic Parity Register 65" bitfld.long 0x1FC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x200 "EVENTLP_DIAGPAR64,Diagnostic Parity Register 64" bitfld.long 0x200 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x204 "EVENTLP_DIAGPAR63,Diagnostic Parity Register 63" bitfld.long 0x204 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x208 "EVENTLP_DIAGPAR62,Diagnostic Parity Register 62" bitfld.long 0x208 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x20C "EVENTLP_DIAGPAR61,Diagnostic Parity Register 61" bitfld.long 0x20C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x210 "EVENTLP_DIAGPAR60,Diagnostic Parity Register 60" bitfld.long 0x210 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x214 "EVENTLP_DIAGPAR59,Diagnostic Parity Register 59" bitfld.long 0x214 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x218 "EVENTLP_DIAGPAR58,Diagnostic Parity Register 58" bitfld.long 0x218 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x21C "EVENTLP_DIAGPAR57,Diagnostic Parity Register 57" bitfld.long 0x21C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x220 "EVENTLP_DIAGPAR56,Diagnostic Parity Register 56" bitfld.long 0x220 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x224 "EVENTLP_DIAGPAR55,Diagnostic Parity Register 55" bitfld.long 0x224 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x228 "EVENTLP_DIAGPAR54,Diagnostic Parity Register 54" bitfld.long 0x228 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x22C "EVENTLP_DIAGPAR53,Diagnostic Parity Register 53" bitfld.long 0x22C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x230 "EVENTLP_DIAGPAR52,Diagnostic Parity Register 52" bitfld.long 0x230 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x234 "EVENTLP_DIAGPAR51,Diagnostic Parity Register 51" bitfld.long 0x234 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x238 "EVENTLP_DIAGPAR50,Diagnostic Parity Register 50" bitfld.long 0x238 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x23C "EVENTLP_DIAGPAR49,Diagnostic Parity Register 49" bitfld.long 0x23C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x240 "EVENTLP_DIAGPAR48,Diagnostic Parity Register 48" bitfld.long 0x240 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x244 "EVENTLP_DIAGPAR47,Diagnostic Parity Register 47" bitfld.long 0x244 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x248 "EVENTLP_DIAGPAR46,Diagnostic Parity Register 46" bitfld.long 0x248 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x24C "EVENTLP_DIAGPAR45,Diagnostic Parity Register 45" bitfld.long 0x24C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x250 "EVENTLP_DIAGPAR44,Diagnostic Parity Register 44" bitfld.long 0x250 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x254 "EVENTLP_DIAGPAR43,Diagnostic Parity Register 43" bitfld.long 0x254 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x258 "EVENTLP_DIAGPAR42,Diagnostic Parity Register 42" bitfld.long 0x258 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x25C "EVENTLP_DIAGPAR41,Diagnostic Parity Register 41" bitfld.long 0x25C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x260 "EVENTLP_DIAGPAR40,Diagnostic Parity Register 40" bitfld.long 0x260 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x264 "EVENTLP_DIAGPAR39,Diagnostic Parity Register 39" bitfld.long 0x264 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x268 "EVENTLP_DIAGPAR38,Diagnostic Parity Register 38" bitfld.long 0x268 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x26C "EVENTLP_DIAGPAR37,Diagnostic Parity Register 37" bitfld.long 0x26C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x270 "EVENTLP_DIAGPAR36,Diagnostic Parity Register 36" bitfld.long 0x270 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x274 "EVENTLP_DIAGPAR35,Diagnostic Parity Register 35" bitfld.long 0x274 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x278 "EVENTLP_DIAGPAR34,Diagnostic Parity Register 34" bitfld.long 0x278 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x27C "EVENTLP_DIAGPAR33,Diagnostic Parity Register 33" bitfld.long 0x27C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x280 "EVENTLP_DIAGPAR32,Diagnostic Parity Register 32" bitfld.long 0x280 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x284 "EVENTLP_DIAGPAR31,Diagnostic Parity Register 31" bitfld.long 0x284 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x288 "EVENTLP_DIAGPAR30,Diagnostic Parity Register 30" bitfld.long 0x288 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x28C "EVENTLP_DIAGPAR29,Diagnostic Parity Register 29" bitfld.long 0x28C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x290 "EVENTLP_DIAGPAR28,Diagnostic Parity Register 28" bitfld.long 0x290 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x294 "EVENTLP_DIAGPAR27,Diagnostic Parity Register 27" bitfld.long 0x294 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x298 "EVENTLP_DIAGPAR26,Diagnostic Parity Register 26" bitfld.long 0x298 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x29C "EVENTLP_DIAGPAR25,Diagnostic Parity Register 25" bitfld.long 0x29C 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2A0 "EVENTLP_DIAGPAR24,Diagnostic Parity Register 24" bitfld.long 0x2A0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2A4 "EVENTLP_DIAGPAR23,Diagnostic Parity Register 23" bitfld.long 0x2A4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2A8 "EVENTLP_DIAGPAR22,Diagnostic Parity Register 22" bitfld.long 0x2A8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2AC "EVENTLP_DIAGPAR21,Diagnostic Parity Register 21" bitfld.long 0x2AC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2B0 "EVENTLP_DIAGPAR20,Diagnostic Parity Register 20" bitfld.long 0x2B0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2B4 "EVENTLP_DIAGPAR19,Diagnostic Parity Register 19" bitfld.long 0x2B4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2B8 "EVENTLP_DIAGPAR18,Diagnostic Parity Register 18" bitfld.long 0x2B8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2BC "EVENTLP_DIAGPAR17,Diagnostic Parity Register 17" bitfld.long 0x2BC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2C0 "EVENTLP_DIAGPAR16,Diagnostic Parity Register 16" bitfld.long 0x2C0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2C4 "EVENTLP_DIAGPAR15,Diagnostic Parity Register 15" bitfld.long 0x2C4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2C8 "EVENTLP_DIAGPAR14,Diagnostic Parity Register 14" bitfld.long 0x2C8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2CC "EVENTLP_DIAGPAR13,Diagnostic Parity Register 13" bitfld.long 0x2CC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2D0 "EVENTLP_DIAGPAR12,Diagnostic Parity Register 12" bitfld.long 0x2D0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2D4 "EVENTLP_DIAGPAR11,Diagnostic Parity Register 11" bitfld.long 0x2D4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2D8 "EVENTLP_DIAGPAR10,Diagnostic Parity Register 10" bitfld.long 0x2D8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2DC "EVENTLP_DIAGPAR9,Diagnostic Parity Register 9" bitfld.long 0x2DC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2E0 "EVENTLP_DIAGPAR8,Diagnostic Parity Register 8" bitfld.long 0x2E0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2E4 "EVENTLP_DIAGPAR7,Diagnostic Parity Register 7" bitfld.long 0x2E4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2E8 "EVENTLP_DIAGPAR6,Diagnostic Parity Register 6" bitfld.long 0x2E8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2EC "EVENTLP_DIAGPAR5,Diagnostic Parity Register 5" bitfld.long 0x2EC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2F0 "EVENTLP_DIAGPAR4,Diagnostic Parity Register 4" bitfld.long 0x2F0 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2F4 "EVENTLP_DIAGPAR3,Diagnostic Parity Register 3" bitfld.long 0x2F4 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2F8 "EVENTLP_DIAGPAR2,Diagnostic Parity Register 2" bitfld.long 0x2F8 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x2FC "EVENTLP_DIAGPAR1,Diagnostic Parity Register 1" bitfld.long 0x2FC 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" line.long 0x300 "EVENTLP_DIAGPAR0,Diagnostic Parity Register 0" bitfld.long 0x300 0. "ASSERTDIAG,Writing a 1 will cause the safety diagnostic logic to generate a diagnostic check." "0: No Effect,1: Generate diagnostic check" wgroup.long 0x3F4++0x3 line.long 0x0 "EVENTLP_DIAGIFRST,Diagnostic Interface Reset Register" bitfld.long 0x0 1. "DIAGPASSCLR,Writing a 1 will synchronously clear the PARFV MMR DPINDEX field. The STICKY bit for DIAGPASS status will be cleared as well." "0: No Effect,1: Clear" bitfld.long 0x0 0. "ASSERTIFRST,Writing a 1 will synchronously clear the Diagnostic Interface. The STICKY bits for status and well as the PARFV will be cleared. If a true functional failure still exists the interface will re-assert FUNCFAIL on the cycle following the.." "0: No Effect,1: Clear" rgroup.long 0x3F8++0x7 line.long 0x0 "EVENTLP_DIAGPARFV,Diagnostic Parity Fail Vector Register" hexmask.long.word 0x0 16.--25. 1. "DPINDEX,Index of DIAG PASS MMR. NOTE: DPINDEX value of 1 corresponds to DIAGPAR0 2 corresponds to DIAGPAR1 and so on." hexmask.long.word 0x0 0.--9. 1. "INDEX,Index of DIAG MMR creating the failure. NOTE: INDEX value of 1 corresponds to DIAGPAR0 2 corresponds to DIAGPAR1 and so on." line.long 0x4 "EVENTLP_DIAGSTAT,Diagnostic Status Register" hexmask.long.word 0x4 16.--25. 1. "NUMDIAG,This is a hardware constant that indicates how many DIAGPAR registers are included in this SFTYDIAG sub-region." bitfld.long 0x4 0.--2. "STATE,Current diagnostic state" "0: No failures and no diagnostic,1: Functional Failure,2: Diagnostic Failure,?,4: Diagnostic Pass,?,?,?" tree.end tree.end tree "FLASH" base ad:0x0 tree.end tree "FLASHCTL (Flash Controller)" base ad:0x400CD000 rgroup.long 0x1020++0x3 line.long 0x0 "FLASHCTL_IIDX,Interrupt Index Register" bitfld.long 0x0 0. "STAT,Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read only one interrupt is indicated. On a read the current interrupt (highest priority) is automatically cleared by the hardware and the.." "0: No Interrupt Pending,1: DONE Interrupt Pending" group.long 0x1028++0x3 line.long 0x0 "FLASHCTL_IMASK,Interrupt Mask Register" bitfld.long 0x0 0. "DONE,Interrupt mask for DONE:" "0: Interrupt is disabled in MIS register,1: Interrupt is enabled in MIS register" rgroup.long 0x1030++0x3 line.long 0x0 "FLASHCTL_RIS,Raw Interrupt Status Register" bitfld.long 0x0 0. "DONE,Flash wrapper operation completed." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x1038++0x3 line.long 0x0 "FLASHCTL_MIS,Masked Interrupt Status Register" bitfld.long 0x0 0. "DONE,Flash wrapper operation completed." "0: Masked interrupt did not occur,1: Masked interrupt occurred" wgroup.long 0x1040++0x3 line.long 0x0 "FLASHCTL_ISET,Interrupt Set Register" bitfld.long 0x0 0. "DONE,0: No effect" "0: No effect,1: Set the DONE interrupt in the RIS register" wgroup.long 0x1048++0x3 line.long 0x0 "FLASHCTL_ICLR,Interrupt Clear Register" bitfld.long 0x0 0. "DONE,0: No effect" "0: No effect,1: Clear the DONE interrupt in the RIS register" rgroup.long 0x10E0++0x3 line.long 0x0 "FLASHCTL_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for peripheral event" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "FLASHCTL_DESC,Hardware Version Description Register" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module ID" newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature set" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance number" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision" group.long 0x1100++0xB line.long 0x0 "FLASHCTL_CMDEXEC,Command Execute Register" bitfld.long 0x0 0. "VAL,Command Execute value" "0: Command will not execute or is not executing in..,1: Command will execute or is executing in flash.." line.long 0x4 "FLASHCTL_CMDTYPE,Command Type Register" bitfld.long 0x4 4.--6. "SIZE,Command size" "0: Operate on 1 flash word,1: Operate on 2 flash words,2: Operate on 4 flash words,3: Operate on 8 flash words,4: Operate on a flash sector,5: Operate on an entire flash bank,?,?" newline bitfld.long 0x4 0.--2. "COMMAND,Command type" "0: No Operation,1: Program,2: Erase,3: Read Verify - Perform a standalone read verify..,4: Mode Change - Perform a mode change only no..,5: Clear Status - Clear status bits in FW_SMSTAT..,6: Blank Verify - Check whether a flash word is in..,?" line.long 0x8 "FLASHCTL_CMDCTL,Command Control Register" bitfld.long 0x8 21. "DATAVEREN,Enable invalid data verify." "0: Disable,1: Enable" newline bitfld.long 0x8 20. "SSERASEDIS,Disable Stair-Step Erase. If set the default VHV trim voltage setting will be used" "0: Enable,1: Disable" newline sif (cpuis("MSPM0G110*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x8 17. "ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: Do not override,1: Override" newline endif bitfld.long 0x8 16. "ADDRXLATEOVR,Override hardware address translation of address in CMDADDR from a" "0: Do not override,1: Override" newline hexmask.long.byte 0x8 9.--12. 1. "REGIONSEL,Bank Region" newline sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x8 4.--8. 1. "BANKSEL,Bank Select" newline endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x8 4.--8. 1. "BANKSEL,Bank Select" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x8 4.--5. "BANKSEL,Bank Select" "?,1: Bank 0,2: Bank 1,?" newline endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x8 4.--8. 1. "BANKSEL,Bank Select" newline endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x8 4.--8. 1. "BANKSEL,Bank Select" newline endif hexmask.long.byte 0x8 0.--3. 1. "MODESEL,Mode" group.long 0x1120++0x7 line.long 0x0 "FLASHCTL_CMDADDR,Command Address Register" hexmask.long 0x0 0.--31. 1. "VAL,Address value" line.long 0x4 "FLASHCTL_CMDBYTEN,Command Program Byte Enable Register" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x4 0.--7. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0G110*")) hexmask.long.word 0x4 0.--8. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0G150*")) hexmask.long.word 0x4 0.--8. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0G151*")) hexmask.long.tbyte 0x4 0.--17. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0G310*")) hexmask.long.word 0x4 0.--8. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0G350*")) hexmask.long.word 0x4 0.--8. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0G351*")) hexmask.long.tbyte 0x4 0.--17. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0L110*")) hexmask.long.byte 0x4 0.--7. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x4 0.--8. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0L122*")) hexmask.long.tbyte 0x4 0.--17. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0L130*")) hexmask.long.byte 0x4 0.--7. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0L134*")) hexmask.long.byte 0x4 0.--7. 1. "VAL,Command Byte Enable value." newline endif sif (cpuis("MSPM0L222*")) hexmask.long.tbyte 0x4 0.--17. 1. "VAL,Command Byte Enable value." endif sif (cpuis("MSPM0G151*")) group.long 0x112C++0x3 line.long 0x0 "FLASHCTL_CMDDATAINDEX,Command Data Index Register" bitfld.long 0x0 0.--2. "VAL,Data register index" "0,1,2,3,4,5,6,7" group.long 0x1138++0x97 line.long 0x0 "FLASHCTL_CMDDATA2,Command Data Register 2" hexmask.long 0x0 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4 "FLASHCTL_CMDDATA3,Command Data Register Bits 127:96" hexmask.long 0x4 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x8 "FLASHCTL_CMDDATA4,Command Data Register 4" hexmask.long 0x8 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0xC "FLASHCTL_CMDDATA5,Command Data Register 5" hexmask.long 0xC 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x10 "FLASHCTL_CMDDATA6,Command Data Register 6" hexmask.long 0x10 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x14 "FLASHCTL_CMDDATA7,Command Data Register 7" hexmask.long 0x14 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x18 "FLASHCTL_CMDDATA8,Command Data Register 8" hexmask.long 0x18 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x1C "FLASHCTL_CMDDATA9,Command Data Register 9" hexmask.long 0x1C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x20 "FLASHCTL_CMDDATA10,Command Data Register 10" hexmask.long 0x20 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x24 "FLASHCTL_CMDDATA11,Command Data Register 11" hexmask.long 0x24 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x28 "FLASHCTL_CMDDATA12,Command Data Register 12" hexmask.long 0x28 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x2C "FLASHCTL_CMDDATA13,Command Data Register 13" hexmask.long 0x2C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x30 "FLASHCTL_CMDDATA14,Command Data Register 14" hexmask.long 0x30 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x34 "FLASHCTL_CMDDATA15,Command Data Register 15" hexmask.long 0x34 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x38 "FLASHCTL_CMDDATA16,Command Data Register 16" hexmask.long 0x38 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x3C "FLASHCTL_CMDDATA17,Command Data Register 17" hexmask.long 0x3C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x40 "FLASHCTL_CMDDATA18,Command Data Register 18" hexmask.long 0x40 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x44 "FLASHCTL_CMDDATA19,Command Data Register 19" hexmask.long 0x44 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x48 "FLASHCTL_CMDDATA20,Command Data Register 20" hexmask.long 0x48 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4C "FLASHCTL_CMDDATA21,Command Data Register 21" hexmask.long 0x4C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x50 "FLASHCTL_CMDDATA22,Command Data Register 22" hexmask.long 0x50 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x54 "FLASHCTL_CMDDATA23,Command Data Register 23" hexmask.long 0x54 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x58 "FLASHCTL_CMDDATA24,Command Data Register 24" hexmask.long 0x58 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x5C "FLASHCTL_CMDDATA25,Command Data Register 25" hexmask.long 0x5C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x60 "FLASHCTL_CMDDATA26,Command Data Register 26" hexmask.long 0x60 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x64 "FLASHCTL_CMDDATA27,Command Data Register 27" hexmask.long 0x64 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x68 "FLASHCTL_CMDDATA28,Command Data Register 28" hexmask.long 0x68 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x6C "FLASHCTL_CMDDATA29,Command Data Register 29" hexmask.long 0x6C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x70 "FLASHCTL_CMDDATA30,Command Data Register 30" hexmask.long 0x70 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x74 "FLASHCTL_CMDDATA31,Command Data Register 31" hexmask.long 0x74 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x78 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x78 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x78 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x7C "FLASHCTL_CMDDATAECC1,Command Data Register ECC 1" hexmask.long.byte 0x7C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x7C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x80 "FLASHCTL_CMDDATAECC2,Command Data Register ECC 2" hexmask.long.byte 0x80 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x80 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x84 "FLASHCTL_CMDDATAECC3,Command Data Register ECC 3" hexmask.long.byte 0x84 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x84 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x88 "FLASHCTL_CMDDATAECC4,Command Data Register ECC 4" hexmask.long.byte 0x88 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x88 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x8C "FLASHCTL_CMDDATAECC5,Command Data Register ECC 5" hexmask.long.byte 0x8C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x8C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x90 "FLASHCTL_CMDDATAECC6,Command Data Register ECC 6" hexmask.long.byte 0x90 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x90 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x94 "FLASHCTL_CMDDATAECC7,Command Data Register ECC 7" hexmask.long.byte 0x94 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x94 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" endif sif (cpuis("MSPM0G351*")) group.long 0x112C++0x3 line.long 0x0 "FLASHCTL_CMDDATAINDEX,Command Data Index Register" bitfld.long 0x0 0.--2. "VAL,Data register index" "0,1,2,3,4,5,6,7" group.long 0x1138++0x97 line.long 0x0 "FLASHCTL_CMDDATA2,Command Data Register 2" hexmask.long 0x0 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4 "FLASHCTL_CMDDATA3,Command Data Register Bits 127:96" hexmask.long 0x4 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x8 "FLASHCTL_CMDDATA4,Command Data Register 4" hexmask.long 0x8 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0xC "FLASHCTL_CMDDATA5,Command Data Register 5" hexmask.long 0xC 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x10 "FLASHCTL_CMDDATA6,Command Data Register 6" hexmask.long 0x10 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x14 "FLASHCTL_CMDDATA7,Command Data Register 7" hexmask.long 0x14 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x18 "FLASHCTL_CMDDATA8,Command Data Register 8" hexmask.long 0x18 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x1C "FLASHCTL_CMDDATA9,Command Data Register 9" hexmask.long 0x1C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x20 "FLASHCTL_CMDDATA10,Command Data Register 10" hexmask.long 0x20 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x24 "FLASHCTL_CMDDATA11,Command Data Register 11" hexmask.long 0x24 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x28 "FLASHCTL_CMDDATA12,Command Data Register 12" hexmask.long 0x28 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x2C "FLASHCTL_CMDDATA13,Command Data Register 13" hexmask.long 0x2C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x30 "FLASHCTL_CMDDATA14,Command Data Register 14" hexmask.long 0x30 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x34 "FLASHCTL_CMDDATA15,Command Data Register 15" hexmask.long 0x34 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x38 "FLASHCTL_CMDDATA16,Command Data Register 16" hexmask.long 0x38 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x3C "FLASHCTL_CMDDATA17,Command Data Register 17" hexmask.long 0x3C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x40 "FLASHCTL_CMDDATA18,Command Data Register 18" hexmask.long 0x40 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x44 "FLASHCTL_CMDDATA19,Command Data Register 19" hexmask.long 0x44 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x48 "FLASHCTL_CMDDATA20,Command Data Register 20" hexmask.long 0x48 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4C "FLASHCTL_CMDDATA21,Command Data Register 21" hexmask.long 0x4C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x50 "FLASHCTL_CMDDATA22,Command Data Register 22" hexmask.long 0x50 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x54 "FLASHCTL_CMDDATA23,Command Data Register 23" hexmask.long 0x54 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x58 "FLASHCTL_CMDDATA24,Command Data Register 24" hexmask.long 0x58 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x5C "FLASHCTL_CMDDATA25,Command Data Register 25" hexmask.long 0x5C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x60 "FLASHCTL_CMDDATA26,Command Data Register 26" hexmask.long 0x60 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x64 "FLASHCTL_CMDDATA27,Command Data Register 27" hexmask.long 0x64 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x68 "FLASHCTL_CMDDATA28,Command Data Register 28" hexmask.long 0x68 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x6C "FLASHCTL_CMDDATA29,Command Data Register 29" hexmask.long 0x6C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x70 "FLASHCTL_CMDDATA30,Command Data Register 30" hexmask.long 0x70 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x74 "FLASHCTL_CMDDATA31,Command Data Register 31" hexmask.long 0x74 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x78 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x78 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x78 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x7C "FLASHCTL_CMDDATAECC1,Command Data Register ECC 1" hexmask.long.byte 0x7C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x7C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x80 "FLASHCTL_CMDDATAECC2,Command Data Register ECC 2" hexmask.long.byte 0x80 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x80 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x84 "FLASHCTL_CMDDATAECC3,Command Data Register ECC 3" hexmask.long.byte 0x84 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x84 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x88 "FLASHCTL_CMDDATAECC4,Command Data Register ECC 4" hexmask.long.byte 0x88 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x88 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x8C "FLASHCTL_CMDDATAECC5,Command Data Register ECC 5" hexmask.long.byte 0x8C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x8C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x90 "FLASHCTL_CMDDATAECC6,Command Data Register ECC 6" hexmask.long.byte 0x90 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x90 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x94 "FLASHCTL_CMDDATAECC7,Command Data Register ECC 7" hexmask.long.byte 0x94 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x94 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" rgroup.long 0x1410++0x7 line.long 0x0 "FLASHCTL_BANK1INFO0,Bank Information Register 0 for Bank 1" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK1INFO1,Bank Information Register 1 for Bank 1" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1420++0x7 line.long 0x0 "FLASHCTL_BANK2INFO0,Bank Information Register 0 for Bank 2" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK2INFO1,Bank Information Register 1 for Bank 2" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1430++0x7 line.long 0x0 "FLASHCTL_BANK3INFO0,Bank Information Register 0 for Bank 3" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK3INFO1,Bank Information Register 1 for Bank 3" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1440++0x3 line.long 0x0 "FLASHCTL_BANK4INFO0,Bank Information Register 0 for Bank 4" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" endif sif (cpuis("MSPM0L122*")) group.long 0x112C++0x3 line.long 0x0 "FLASHCTL_CMDDATAINDEX,Command Data Index Register" bitfld.long 0x0 0.--2. "VAL,Data register index" "0,1,2,3,4,5,6,7" group.long 0x1138++0x97 line.long 0x0 "FLASHCTL_CMDDATA2,Command Data Register 2" hexmask.long 0x0 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4 "FLASHCTL_CMDDATA3,Command Data Register Bits 127:96" hexmask.long 0x4 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x8 "FLASHCTL_CMDDATA4,Command Data Register 4" hexmask.long 0x8 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0xC "FLASHCTL_CMDDATA5,Command Data Register 5" hexmask.long 0xC 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x10 "FLASHCTL_CMDDATA6,Command Data Register 6" hexmask.long 0x10 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x14 "FLASHCTL_CMDDATA7,Command Data Register 7" hexmask.long 0x14 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x18 "FLASHCTL_CMDDATA8,Command Data Register 8" hexmask.long 0x18 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x1C "FLASHCTL_CMDDATA9,Command Data Register 9" hexmask.long 0x1C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x20 "FLASHCTL_CMDDATA10,Command Data Register 10" hexmask.long 0x20 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x24 "FLASHCTL_CMDDATA11,Command Data Register 11" hexmask.long 0x24 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x28 "FLASHCTL_CMDDATA12,Command Data Register 12" hexmask.long 0x28 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x2C "FLASHCTL_CMDDATA13,Command Data Register 13" hexmask.long 0x2C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x30 "FLASHCTL_CMDDATA14,Command Data Register 14" hexmask.long 0x30 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x34 "FLASHCTL_CMDDATA15,Command Data Register 15" hexmask.long 0x34 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x38 "FLASHCTL_CMDDATA16,Command Data Register 16" hexmask.long 0x38 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x3C "FLASHCTL_CMDDATA17,Command Data Register 17" hexmask.long 0x3C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x40 "FLASHCTL_CMDDATA18,Command Data Register 18" hexmask.long 0x40 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x44 "FLASHCTL_CMDDATA19,Command Data Register 19" hexmask.long 0x44 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x48 "FLASHCTL_CMDDATA20,Command Data Register 20" hexmask.long 0x48 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4C "FLASHCTL_CMDDATA21,Command Data Register 21" hexmask.long 0x4C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x50 "FLASHCTL_CMDDATA22,Command Data Register 22" hexmask.long 0x50 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x54 "FLASHCTL_CMDDATA23,Command Data Register 23" hexmask.long 0x54 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x58 "FLASHCTL_CMDDATA24,Command Data Register 24" hexmask.long 0x58 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x5C "FLASHCTL_CMDDATA25,Command Data Register 25" hexmask.long 0x5C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x60 "FLASHCTL_CMDDATA26,Command Data Register 26" hexmask.long 0x60 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x64 "FLASHCTL_CMDDATA27,Command Data Register 27" hexmask.long 0x64 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x68 "FLASHCTL_CMDDATA28,Command Data Register 28" hexmask.long 0x68 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x6C "FLASHCTL_CMDDATA29,Command Data Register 29" hexmask.long 0x6C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x70 "FLASHCTL_CMDDATA30,Command Data Register 30" hexmask.long 0x70 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x74 "FLASHCTL_CMDDATA31,Command Data Register 31" hexmask.long 0x74 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x78 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x78 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x78 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x7C "FLASHCTL_CMDDATAECC1,Command Data Register ECC 1" hexmask.long.byte 0x7C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x7C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x80 "FLASHCTL_CMDDATAECC2,Command Data Register ECC 2" hexmask.long.byte 0x80 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x80 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x84 "FLASHCTL_CMDDATAECC3,Command Data Register ECC 3" hexmask.long.byte 0x84 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x84 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x88 "FLASHCTL_CMDDATAECC4,Command Data Register ECC 4" hexmask.long.byte 0x88 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x88 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x8C "FLASHCTL_CMDDATAECC5,Command Data Register ECC 5" hexmask.long.byte 0x8C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x8C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x90 "FLASHCTL_CMDDATAECC6,Command Data Register ECC 6" hexmask.long.byte 0x90 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x90 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x94 "FLASHCTL_CMDDATAECC7,Command Data Register ECC 7" hexmask.long.byte 0x94 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x94 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" group.long 0x1218++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTEN,Command Write Erase Protect Engr Register" hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." rgroup.long 0x1410++0x7 line.long 0x0 "FLASHCTL_BANK1INFO0,Bank Information Register 0 for Bank 1" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK1INFO1,Bank Information Register 1 for Bank 1" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1420++0x7 line.long 0x0 "FLASHCTL_BANK2INFO0,Bank Information Register 0 for Bank 2" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK2INFO1,Bank Information Register 1 for Bank 2" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1430++0x7 line.long 0x0 "FLASHCTL_BANK3INFO0,Bank Information Register 0 for Bank 3" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK3INFO1,Bank Information Register 1 for Bank 3" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1440++0x3 line.long 0x0 "FLASHCTL_BANK4INFO0,Bank Information Register 0 for Bank 4" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" endif sif (cpuis("MSPM0L222*")) group.long 0x112C++0x3 line.long 0x0 "FLASHCTL_CMDDATAINDEX,Command Data Index Register" bitfld.long 0x0 0.--2. "VAL,Data register index" "0,1,2,3,4,5,6,7" group.long 0x1138++0x97 line.long 0x0 "FLASHCTL_CMDDATA2,Command Data Register 2" hexmask.long 0x0 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4 "FLASHCTL_CMDDATA3,Command Data Register Bits 127:96" hexmask.long 0x4 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x8 "FLASHCTL_CMDDATA4,Command Data Register 4" hexmask.long 0x8 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0xC "FLASHCTL_CMDDATA5,Command Data Register 5" hexmask.long 0xC 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x10 "FLASHCTL_CMDDATA6,Command Data Register 6" hexmask.long 0x10 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x14 "FLASHCTL_CMDDATA7,Command Data Register 7" hexmask.long 0x14 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x18 "FLASHCTL_CMDDATA8,Command Data Register 8" hexmask.long 0x18 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x1C "FLASHCTL_CMDDATA9,Command Data Register 9" hexmask.long 0x1C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x20 "FLASHCTL_CMDDATA10,Command Data Register 10" hexmask.long 0x20 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x24 "FLASHCTL_CMDDATA11,Command Data Register 11" hexmask.long 0x24 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x28 "FLASHCTL_CMDDATA12,Command Data Register 12" hexmask.long 0x28 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x2C "FLASHCTL_CMDDATA13,Command Data Register 13" hexmask.long 0x2C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x30 "FLASHCTL_CMDDATA14,Command Data Register 14" hexmask.long 0x30 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x34 "FLASHCTL_CMDDATA15,Command Data Register 15" hexmask.long 0x34 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x38 "FLASHCTL_CMDDATA16,Command Data Register 16" hexmask.long 0x38 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x3C "FLASHCTL_CMDDATA17,Command Data Register 17" hexmask.long 0x3C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x40 "FLASHCTL_CMDDATA18,Command Data Register 18" hexmask.long 0x40 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x44 "FLASHCTL_CMDDATA19,Command Data Register 19" hexmask.long 0x44 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x48 "FLASHCTL_CMDDATA20,Command Data Register 20" hexmask.long 0x48 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4C "FLASHCTL_CMDDATA21,Command Data Register 21" hexmask.long 0x4C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x50 "FLASHCTL_CMDDATA22,Command Data Register 22" hexmask.long 0x50 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x54 "FLASHCTL_CMDDATA23,Command Data Register 23" hexmask.long 0x54 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x58 "FLASHCTL_CMDDATA24,Command Data Register 24" hexmask.long 0x58 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x5C "FLASHCTL_CMDDATA25,Command Data Register 25" hexmask.long 0x5C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x60 "FLASHCTL_CMDDATA26,Command Data Register 26" hexmask.long 0x60 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x64 "FLASHCTL_CMDDATA27,Command Data Register 27" hexmask.long 0x64 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x68 "FLASHCTL_CMDDATA28,Command Data Register 28" hexmask.long 0x68 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x6C "FLASHCTL_CMDDATA29,Command Data Register 29" hexmask.long 0x6C 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x70 "FLASHCTL_CMDDATA30,Command Data Register 30" hexmask.long 0x70 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x74 "FLASHCTL_CMDDATA31,Command Data Register 31" hexmask.long 0x74 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x78 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x78 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x78 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x7C "FLASHCTL_CMDDATAECC1,Command Data Register ECC 1" hexmask.long.byte 0x7C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x7C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x80 "FLASHCTL_CMDDATAECC2,Command Data Register ECC 2" hexmask.long.byte 0x80 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x80 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x84 "FLASHCTL_CMDDATAECC3,Command Data Register ECC 3" hexmask.long.byte 0x84 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x84 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x88 "FLASHCTL_CMDDATAECC4,Command Data Register ECC 4" hexmask.long.byte 0x88 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x88 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x8C "FLASHCTL_CMDDATAECC5,Command Data Register ECC 5" hexmask.long.byte 0x8C 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x8C 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x90 "FLASHCTL_CMDDATAECC6,Command Data Register ECC 6" hexmask.long.byte 0x90 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x90 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." line.long 0x94 "FLASHCTL_CMDDATAECC7,Command Data Register ECC 7" hexmask.long.byte 0x94 8.--15. 1. "VAL1,ECC data for bits 127:64 of the data is placed here." hexmask.long.byte 0x94 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" group.long 0x1218++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTEN,Command Write Erase Protect Engr Register" hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." rgroup.long 0x1410++0x7 line.long 0x0 "FLASHCTL_BANK1INFO0,Bank Information Register 0 for Bank 1" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK1INFO1,Bank Information Register 1 for Bank 1" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1420++0x7 line.long 0x0 "FLASHCTL_BANK2INFO0,Bank Information Register 0 for Bank 2" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK2INFO1,Bank Information Register 1 for Bank 2" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1430++0x7 line.long 0x0 "FLASHCTL_BANK3INFO0,Bank Information Register 0 for Bank 3" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK3INFO1,Bank Information Register 1 for Bank 3" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1440++0x3 line.long 0x0 "FLASHCTL_BANK4INFO0,Bank Information Register 0 for Bank 4" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" endif group.long 0x1130++0x7 line.long 0x0 "FLASHCTL_CMDDATA0,Command Data Register 0" hexmask.long 0x0 0.--31. 1. "VAL,A 32-bit data value is placed in this field." line.long 0x4 "FLASHCTL_CMDDATA1,Command Data Register 1" hexmask.long 0x4 0.--31. 1. "VAL,A 32-bit data value is placed in this field." sif (cpuis("MSPM0G110*")) group.long 0x11B0++0x3 line.long 0x0 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x0 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." endif sif (cpuis("MSPM0G150*")) group.long 0x11B0++0x3 line.long 0x0 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x0 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." endif sif (cpuis("MSPM0G310*")) group.long 0x11B0++0x3 line.long 0x0 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x0 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." endif sif (cpuis("MSPM0G350*")) group.long 0x11B0++0x3 line.long 0x0 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x0 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." endif sif (cpuis("MSPM0L111*")) group.long 0x11B0++0x3 line.long 0x0 "FLASHCTL_CMDDATAECC0,Command Data Register ECC 0" hexmask.long.byte 0x0 0.--7. 1. "VAL0,ECC data for bits 63:0 of the data is placed here." rgroup.long 0x1410++0x7 line.long 0x0 "FLASHCTL_BANK1INFO0,Bank Information Register 0 for Bank 1" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK1INFO1,Bank Information Register 1 for Bank 1" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" endif group.long 0x11D0++0x7 line.long 0x0 "FLASHCTL_CMDWEPROTA,Command Write Erase Protect A Register" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L110*")||cpuis("MSPS003.*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L111*")) hexmask.long.byte 0x0 0.--7. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L122*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L130*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L134*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L222*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." endif line.long 0x4 "FLASHCTL_CMDWEPROTB,Command Write Erase Protect B Register" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x4 0.--3. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0G110*")) hexmask.long.word 0x4 0.--11. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0G150*")) hexmask.long.word 0x4 0.--11. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0G151*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0G310*")) hexmask.long.word 0x4 0.--11. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0G350*")) hexmask.long.word 0x4 0.--11. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0G351*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0L110*")) hexmask.long.byte 0x4 0.--3. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0L111*")) hexmask.long.byte 0x4 0.--7. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0L122*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0L130*")) hexmask.long.byte 0x4 0.--3. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0L134*")) hexmask.long.byte 0x4 0.--3. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" newline endif sif (cpuis("MSPM0L222*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" endif sif (cpuis("MSPM0L110*")) group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" endif sif (cpuis("MSPM0L130*")) group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" group.long 0x1218++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTEN,Command Write Erase Protect Engr Register" bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" endif sif (cpuis("MSPM0L134*")) group.long 0x11D8++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTC,Command Write Erase Protect C Register" group.long 0x1218++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTEN,Command Write Erase Protect Engr Register" bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" endif group.long 0x1210++0x7 line.long 0x0 "FLASHCTL_CMDWEPROTNM,Command Write Erase Protect Non-Main Register" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPS003.*")) bitfld.long 0x0 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0G151*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0G351*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" newline endif sif (cpuis("MSPM0L122*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L222*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." endif line.long 0x4 "FLASHCTL_CMDWEPROTTR,Command Write Erase Protect Trim Register" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPS003.*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0G151*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0G351*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L122*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 0. "VAL,Each bit protects 1 sector." "0,1" newline endif sif (cpuis("MSPM0L222*")) hexmask.long 0x4 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L110*")||cpuis("MSPS003.*")) group.long 0x1218++0x3 line.long 0x0 "FLASHCTL_CMDWEPROTEN,Command Write Erase Protect Engr Register" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" newline endif sif (cpuis("MSPM0G151*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" newline endif sif (cpuis("MSPM0G351*")) hexmask.long 0x0 0.--31. 1. "VAL,Each bit protects 1 sector." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--1. "VAL,Each bit protects 1 sector." "0,1,2,3" newline endif endif group.long 0x13B0++0x7 line.long 0x0 "FLASHCTL_CFGCMD,Command Configuration Register" sif (cpuis("MSPM0G151*")) bitfld.long 0x0 6. "HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to the" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from the" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from the" "0: Disable,1: Enable" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 6. "HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to the" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from the" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from the" "0: Disable,1: Enable" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 6. "HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to the" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from the" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from the" "0: Disable,1: Enable" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 6. "HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to the" "0: Disable,1: Enable" newline bitfld.long 0x0 5. "CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from the" "0: Disable,1: Enable" newline bitfld.long 0x0 4. "RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from the" "0: Disable,1: Enable" newline endif hexmask.long.byte 0x0 0.--3. 1. "WAITSTATE,Wait State setting for program verify erase verify and read verify" line.long 0x4 "FLASHCTL_CFGPCNT,Pulse Counter Configuration Register" sif (cpuis("MSPM0G151*")) hexmask.long.word 0x4 20.--31. 1. "MAXERSPCNTVAL,Override maximum pulse count for erase with this value." newline endif sif (cpuis("MSPM0G351*")) hexmask.long.word 0x4 20.--31. 1. "MAXERSPCNTVAL,Override maximum pulse count for erase with this value." newline endif sif (cpuis("MSPM0L122*")) hexmask.long.word 0x4 20.--31. 1. "MAXERSPCNTVAL,Override maximum pulse count for erase with this value." newline endif sif (cpuis("MSPM0L222*")) hexmask.long.word 0x4 20.--31. 1. "MAXERSPCNTVAL,Override maximum pulse count for erase with this value." newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x4 16. "MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase. If set then the value" "0: Use hard-wired (default) value for maximum pulse..,1: Use value from MAXERSPCNTVAL field as maximum.." newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x4 16. "MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase. If set then the value" "0: Use hard-wired (default) value for maximum pulse..,1: Use value from MAXERSPCNTVAL field as maximum.." newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x4 16. "MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase. If set then the value" "0: Use hard-wired (default) value for maximum pulse..,1: Use value from MAXERSPCNTVAL field as maximum.." newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x4 16. "MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase. If set then the value" "0: Use hard-wired (default) value for maximum pulse..,1: Use value from MAXERSPCNTVAL field as maximum.." newline endif hexmask.long.byte 0x4 4.--11. 1. "MAXPCNTVAL,Override maximum pulse counter with this value." newline bitfld.long 0x4 0. "MAXPCNTOVR,Override hard-wired maximum pulse count. If MAXERSPCNTOVR" "0: Use hard-wired (default) value for maximum pulse..,1: Use value from MAXPCNTVAL field as maximum puse.." rgroup.long 0x13D0++0xF line.long 0x0 "FLASHCTL_STATCMD,Command Status Register" bitfld.long 0x0 12. "FAILMISC,Command failed due to error other than write/erase protect violation or verify" "0: No Fail,1: Fail" newline bitfld.long 0x0 8. "FAILINVDATA,Program command failed because an attempt was made to program a stored" "0: No Fail,1: Fail" newline bitfld.long 0x0 7. "FAILMODE,Command failed because a bank has been set to a mode other than READ." "0: No Fail,1: Fail" newline bitfld.long 0x0 6. "FAILILLADDR,Command failed due to the use of an illegal address" "0: No Fail,1: Fail" newline bitfld.long 0x0 5. "FAILVERIFY,Command failed due to verify error" "0: No Fail,1: Fail" newline bitfld.long 0x0 4. "FAILWEPROT,Command failed due to Write/Erase Protect Sector Violation" "0: No Fail,1: Fail" newline bitfld.long 0x0 2. "CMDINPROGRESS,Command In Progress" "0: Complete,1: In Progress" newline bitfld.long 0x0 1. "CMDPASS,Command Pass - valid when CMD_DONE field is 1" "0: Fail,1: Pass" newline bitfld.long 0x0 0. "CMDDONE,Command Done" "0: Not Done,1: Done" line.long 0x4 "FLASHCTL_STATADDR,Address Status Register" hexmask.long.byte 0x4 21.--25. 1. "BANKID,Current Bank ID" newline hexmask.long.byte 0x4 16.--20. 1. "REGIONID,Current Region ID" newline hexmask.long.word 0x4 0.--15. 1. "BANKADDR,Current Bank Address" line.long 0x8 "FLASHCTL_STATPCNT,Pulse Count Status Register" hexmask.long.word 0x8 0.--11. 1. "PULSECNT,Current Pulse Counter Value" line.long 0xC "FLASHCTL_STATMODE,Mode Status Register" bitfld.long 0xC 17. "BANK1TRDY,Bank 1T Ready." "0: Not ready,1: Ready" newline bitfld.long 0xC 16. "BANK2TRDY,Bank 2T Ready." "0: Not ready,1: Ready" newline hexmask.long.byte 0xC 8.--11. 1. "BANKMODE,Indicates mode of bank(s) that are not in READ mode" newline sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPS003.*")) bitfld.long 0xC 0. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0xC 0. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0xC 0. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0" newline endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0xC 0.--4. 1. "BANKNOTINRD,Bank not in read mode." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0xC 0. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0xC 0.--1. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0,2: Bank 1,?" newline endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0xC 0.--4. 1. "BANKNOTINRD,Bank not in read mode." newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0xC 0. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0xC 0. "BANKNOTINRD,Bank not in read mode." "?,1: Bank 0" newline endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0xC 0.--4. 1. "BANKNOTINRD,Bank not in read mode." newline endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0xC 0.--4. 1. "BANKNOTINRD,Bank not in read mode." endif rgroup.long 0x13F0++0xB line.long 0x0 "FLASHCTL_GBLINFO0,Global Information Register 0" bitfld.long 0x0 16.--18. "NUMBANKS,Number of banks instantiated" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--15. 1. "SECTORSIZE,Sector size in bytes" line.long 0x4 "FLASHCTL_GBLINFO1,Global Information Register 1" bitfld.long 0x4 16.--18. "REDWIDTH,Redundant data width in bits" "0: Redundant data width is 0. Redundancy/Repair not..,?,2: Redundant data width is 2 bits,?,4: Redundant data width is 4 bits,?,?,?" newline hexmask.long.byte 0x4 8.--12. 1. "ECCWIDTH,ECC data width in bits" newline hexmask.long.byte 0x4 0.--7. 1. "DATAWIDTH,Data width in bits" line.long 0x8 "FLASHCTL_GBLINFO2,Global Information Register 2" hexmask.long.byte 0x8 0.--3. 1. "DATAREGISTERS,Number of data registers present." rgroup.long 0x1400++0x7 line.long 0x0 "FLASHCTL_BANK0INFO0,Bank Information Register 0 for Bank 0" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK0INFO1,Bank Information Register 1 for Bank 0" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" newline hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" sif (cpuis("MSPM0G151*")) rgroup.long 0x1410++0x7 line.long 0x0 "FLASHCTL_BANK1INFO0,Bank Information Register 0 for Bank 1" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK1INFO1,Bank Information Register 1 for Bank 1" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1420++0x7 line.long 0x0 "FLASHCTL_BANK2INFO0,Bank Information Register 0 for Bank 2" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK2INFO1,Bank Information Register 1 for Bank 2" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1430++0x7 line.long 0x0 "FLASHCTL_BANK3INFO0,Bank Information Register 0 for Bank 3" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK3INFO1,Bank Information Register 1 for Bank 3" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" rgroup.long 0x1440++0x7 line.long 0x0 "FLASHCTL_BANK4INFO0,Bank Information Register 0 for Bank 4" hexmask.long.word 0x0 0.--11. 1. "MAINSIZE,Main region size in sectors" line.long 0x4 "FLASHCTL_BANK4INFO1,Bank Information Register 1 for Bank 4" hexmask.long.byte 0x4 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x4 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x4 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" endif sif (cpuis("MSPM0G351*")) rgroup.long 0x1444++0x3 line.long 0x0 "FLASHCTL_BANK4INFO1,Bank Information Register 1 for Bank 4" hexmask.long.byte 0x0 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x0 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x0 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" endif sif (cpuis("MSPM0L122*")) rgroup.long 0x1444++0x3 line.long 0x0 "FLASHCTL_BANK4INFO1,Bank Information Register 1 for Bank 4" hexmask.long.byte 0x0 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x0 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x0 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" endif sif (cpuis("MSPM0L222*")) rgroup.long 0x1444++0x3 line.long 0x0 "FLASHCTL_BANK4INFO1,Bank Information Register 1 for Bank 4" hexmask.long.byte 0x0 16.--23. 1. "ENGRSIZE,Engr region size in sectors" hexmask.long.byte 0x0 8.--15. 1. "TRIMSIZE,Trim region size in sectors" newline hexmask.long.byte 0x0 0.--7. 1. "NONMAINSIZE,Non-main region size in sectors" endif tree.end tree "GPIO (General Purpose Input/Output)" base ad:0x0 sif (cpuis("MSPM0C110*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPS003.*")) tree "GPIOA" base ad:0x400A0000 group.long 0x400++0x7 line.long 0x0 "GPIOA_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "GPIOA_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "GPIOA_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "GPIOA_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "GPIOA_GPRCM[%s]" base ad:0x400A0800 group.long 0x0++0x3 line.long 0x0 "GPIOA_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOA_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOA_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A0000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOA_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOA_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOA_INT_EVENT0[%s]" base ad:0x400A1020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_INT_EVENT1[%s]" base ad:0x400A1050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_INT_EVENT2[%s]" base ad:0x400A1080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A0000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOA_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOA_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOA_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOA_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOA_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOA_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOA_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOA_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOA_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOA_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOA_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOA_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOA_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOA_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOA_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOA_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOA_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOA_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOA_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOA_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOA_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOA_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOA_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOA_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOA_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOA_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOA_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOA_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOA_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOA_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOA_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOA_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOA_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOA_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOA_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "GPIOB" base ad:0x400A2000 group.long 0x400++0x7 line.long 0x0 "GPIOB_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOB_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOB_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOB_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "GPIOB_GPRCM[%s]" base ad:0x400A2800 group.long 0x0++0x3 line.long 0x0 "GPIOB_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOB_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOB_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A2000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOB_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOB_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOB_INT_EVENT0[%s]" base ad:0x400A3020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOB_INT_EVENT1[%s]" base ad:0x400A3050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOB_INT_EVENT2[%s]" base ad:0x400A3080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A2000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOB_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOB_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOB_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOB_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOB_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOB_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOB_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOB_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOB_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOB_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOB_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOB_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOB_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOB_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOB_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOB_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOB_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOB_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOB_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOB_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOB_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOB_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOB_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOB_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOB_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOB_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOB_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOB_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOB_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOB_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOB_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOB_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOB_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOB_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOB_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "GPIOA" base ad:0x400A0000 group.long 0x400++0x7 line.long 0x0 "GPIOA_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOA_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOA_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOA_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "GPIOA_GPRCM[%s]" base ad:0x400A0800 group.long 0x0++0x3 line.long 0x0 "GPIOA_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOA_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOA_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A0000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOA_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOA_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOA_INT_EVENT0[%s]" base ad:0x400A1020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_INT_EVENT1[%s]" base ad:0x400A1050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_INT_EVENT2[%s]" base ad:0x400A1080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A0000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOA_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOA_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOA_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOA_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOA_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOA_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOA_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOA_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOA_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOA_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOA_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOA_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOA_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOA_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOA_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOA_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOA_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOA_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOA_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOA_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOA_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOA_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOA_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOA_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOA_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOA_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOA_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOA_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOA_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOA_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOA_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOA_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOA_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOA_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOA_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "GPIOA" base ad:0x400A0000 group.long 0x400++0x7 line.long 0x0 "GPIOA_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOA_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOA_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOA_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "GPIOA_GPRCM[%s]" base ad:0x400A0800 group.long 0x0++0x3 line.long 0x0 "GPIOA_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOA_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOA_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A0000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOA_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOA_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOA_CPU_INT[%s]" base ad:0x400A1020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_GEN_EVENT0[%s]" base ad:0x400A1050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_GEN_EVENT1[%s]" base ad:0x400A1080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A0000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOA_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOA_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOA_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOA_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOA_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOA_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOA_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOA_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOA_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOA_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOA_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOA_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOA_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOA_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOA_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOA_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOA_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOA_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOA_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOA_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOA_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOA_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOA_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOA_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOA_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOA_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOA_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOA_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOA_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOA_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOA_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOA_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOA_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOA_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOA_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "GPIOB" base ad:0x400A2000 group.long 0x400++0x7 line.long 0x0 "GPIOB_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOB_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOB_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOB_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "GPIOB_GPRCM[%s]" base ad:0x400A2800 group.long 0x0++0x3 line.long 0x0 "GPIOB_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOB_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOB_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A2000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOB_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOB_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOB_CPU_INT[%s]" base ad:0x400A3020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOB_GEN_EVENT0[%s]" base ad:0x400A3050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOB_GEN_EVENT1[%s]" base ad:0x400A3080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A2000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOB_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOB_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOB_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOB_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOB_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOB_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOB_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOB_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOB_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOB_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOB_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOB_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOB_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOB_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOB_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOB_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOB_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOB_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOB_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOB_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOB_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOB_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOB_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOB_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOB_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOB_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOB_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOB_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOB_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOB_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOB_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOB_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOB_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOB_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOB_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "GPIOC" base ad:0x400A4000 group.long 0x400++0x7 line.long 0x0 "GPIOC_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOC_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOC_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOC_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "GPIOC_GPRCM[%s]" base ad:0x400A4800 group.long 0x0++0x3 line.long 0x0 "GPIOC_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOC_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOC_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A4000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOC_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOC_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOC_CPU_INT[%s]" base ad:0x400A5020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOC_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOC_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOC_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOC_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOC_GEN_EVENT0[%s]" base ad:0x400A5050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOC_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOC_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOC_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOC_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOC_GEN_EVENT1[%s]" base ad:0x400A5080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOC_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOC_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOC_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOC_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOC_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOC_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A4000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOC_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOC_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOC_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOC_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOC_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOC_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOC_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOC_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOC_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOC_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOC_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOC_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOC_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOC_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOC_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOC_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOC_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOC_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOC_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOC_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOC_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOC_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOC_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOC_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOC_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOC_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOC_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOC_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOC_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOC_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOC_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOC_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOC_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOC_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOC_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0L111*")) tree "GPIOA" base ad:0x400A0000 group.long 0x400++0x7 line.long 0x0 "GPIOA_FSUB_0,Subsciber Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOA_FSUB_1,Subscriber Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOA_FPUB_0,Publisher Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOA_FPUB_1,Publisher Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." tree "GPIOA_GPRCM[%s]" base ad:0x400A0800 group.long 0x0++0x3 line.long 0x0 "GPIOA_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOA_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOA_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A0000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOA_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOA_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOA_CPU_INT[%s]" base ad:0x400A1020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_GEN_EVENT0[%s]" base ad:0x400A1050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOA_GEN_EVENT1[%s]" base ad:0x400A1080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOA_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A0000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOA_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOA_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOA_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOA_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOA_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOA_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOA_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOA_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOA_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOA_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOA_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOA_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOA_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOA_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOA_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOA_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOA_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOA_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOA_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOA_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOA_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOA_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOA_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOA_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOA_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOA_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOA_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOA_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOA_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOA_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOA_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOA_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOA_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOA_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOA_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif sif (cpuis("MSPM0L111*")) tree "GPIOB" base ad:0x400A2000 group.long 0x400++0x7 line.long 0x0 "GPIOB_FSUB_0,Subsciber Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOB_FSUB_1,Subscriber Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "GPIOB_FPUB_0,Publisher Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "GPIOB_FPUB_1,Publisher Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." tree "GPIOB_GPRCM[%s]" base ad:0x400A2800 group.long 0x0++0x3 line.long 0x0 "GPIOB_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "GPIOB_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "GPIOB_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400A2000 newline group.long 0x1010++0x3 newline line.long 0x0 "GPIOB_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x1018++0x3 line.long 0x0 "GPIOB_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "GPIOB_CPU_INT[%s]" base ad:0x400A3020 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" newline bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" newline bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" newline bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" newline bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" newline bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOB_GEN_EVENT0[%s]" base ad:0x400A3050 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 15. "DIO15,DIO15 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 14. "DIO14,DIO14 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 13. "DIO13,DIO13 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 12. "DIO12,DIO12 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 11. "DIO11,DIO11 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 10. "DIO10,DIO10 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 9. "DIO9,DIO9 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 8. "DIO8,DIO8 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 7. "DIO7,DIO7 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 6. "DIO6,DIO6 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 5. "DIO5,DIO5 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 4. "DIO4,DIO4 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 3. "DIO3,DIO3 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 2. "DIO2,DIO2 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 1. "DIO1,DIO1 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 0. "DIO0,DIO0 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: DIO15 event did not occur,1: DIO15 event occurred" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: DIO14 event did not occur,1: DIO14 event occurred" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: DIO13 event did not occur,1: DIO13 event occurred" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: DIO12 event did not occur,1: DIO12 event occurred" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: DIO11 event did not occur,1: DIO11 event occurred" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: DIO10 event did not occur,1: DIO10 event occurred" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: DIO9 event did not occur,1: DIO9 event occurred" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: DIO8 event did not occur,1: DIO8 event occurred" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: DIO7 event did not occur,1: DIO7 event occurred" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: DIO6 event did not occur,1: DIO6 event occurred" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: DIO5 event did not occur,1: DIO5 event occurred" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: DIO4 event did not occur,1: DIO4 event occurred" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: DIO3 event did not occur,1: DIO3 event occurred" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: DIO2 event did not occur,1: DIO2 event occurred" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: DIO1 event did not occur,1: DIO1 event occurred" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: DIO0 event did not occur,1: DIO0 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Sets DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Sets DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Sets DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Sets DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Sets DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Sets DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Sets DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Sets DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Sets DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Sets DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Sets DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Sets DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Sets DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Sets DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Sets DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Sets DIO0 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 15. "DIO15,DIO15 event" "0: No effect,1: Clears DIO15 in RIS register" bitfld.long 0x0 14. "DIO14,DIO14 event" "0: No effect,1: Clears DIO14 in RIS register" bitfld.long 0x0 13. "DIO13,DIO13 event" "0: No effect,1: Clears DIO13 in RIS register" newline bitfld.long 0x0 12. "DIO12,DIO12 event" "0: No effect,1: Clears DIO12 in RIS register" bitfld.long 0x0 11. "DIO11,DIO11 event" "0: No effect,1: Clears DIO11 in RIS register" bitfld.long 0x0 10. "DIO10,DIO10 event" "0: No effect,1: Clears DIO10 in RIS register" newline bitfld.long 0x0 9. "DIO9,DIO9 event" "0: No effect,1: Clears DIO9 in RIS register" bitfld.long 0x0 8. "DIO8,DIO8 event" "0: No effect,1: Clears DIO8 in RIS register" bitfld.long 0x0 7. "DIO7,DIO7 event" "0: No effect,1: Clears DIO7 in RIS register" newline bitfld.long 0x0 6. "DIO6,DIO6 event" "0: No effect,1: Clears DIO6 in RIS register" bitfld.long 0x0 5. "DIO5,DIO5 event" "0: No effect,1: Clears DIO5 in RIS register" bitfld.long 0x0 4. "DIO4,DIO4 event" "0: No effect,1: Clears DIO4 in RIS register" newline bitfld.long 0x0 3. "DIO3,DIO3 event" "0: No effect,1: Clears DIO3 in RIS register" bitfld.long 0x0 2. "DIO2,DIO2 event" "0: No effect,1: Clears DIO2 in RIS register" bitfld.long 0x0 1. "DIO1,DIO1 event" "0: No effect,1: Clears DIO1 in RIS register" newline bitfld.long 0x0 0. "DIO0,DIO0 event" "0: No effect,1: Clears DIO0 in RIS register" tree.end tree "GPIOB_GEN_EVENT1[%s]" base ad:0x400A3080 rgroup.long 0x0++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 31. "DIO31,DIO31 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 30. "DIO30,DIO30 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 29. "DIO29,DIO29 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 28. "DIO28,DIO28 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 27. "DIO27,DIO27 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 26. "DIO26,DIO26 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 25. "DIO25,DIO25 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 24. "DIO24,DIO24 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 23. "DIO23,DIO23 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 22. "DIO22,DIO22 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 21. "DIO21,DIO21 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 20. "DIO20,DIO20 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 19. "DIO19,DIO19 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 18. "DIO18,DIO18 event mask" "0: Event is masked,1: Event is unmasked" bitfld.long 0x0 17. "DIO17,DIO17 event mask" "0: Event is masked,1: Event is unmasked" newline bitfld.long 0x0 16. "DIO16,DIO16 event mask" "0: Event is masked,1: Event is unmasked" rgroup.long 0x10++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" rgroup.long 0x18++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: DIO31 event did not occur,1: DIO31 event occurred" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: DIO30 event did not occur,1: DIO30 event occurred" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: DIO29 event did not occur,1: DIO29 event occurred" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: DIO28 event did not occur,1: DIO28 event occurred" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: DIO27 event did not occur,1: DIO27 event occurred" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: DIO26 event did not occur,1: DIO26 event occurred" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: DIO25 event did not occur,1: DIO25 event occurred" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: DIO24 event did not occur,1: DIO24 event occurred" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: DIO23 event did not occur,1: DIO23 event occurred" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: DIO22 event did not occur,1: DIO22 event occurred" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: DIO21 event did not occur,1: DIO21 event occurred" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: DIO20 event did not occur,1: DIO20 event occurred" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: DIO19 event did not occur,1: DIO19 event occurred" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: DIO18 event did not occur,1: DIO18 event occurred" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: DIO17 event did not occur,1: DIO17 event occurred" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: DIO16 event did not occur,1: DIO16 event occurred" wgroup.long 0x20++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Sets DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Sets DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Sets DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Sets DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Sets DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Sets DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Sets DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Sets DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Sets DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Sets DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Sets DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Sets DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Sets DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Sets DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Sets DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Sets DIO16 in RIS register" wgroup.long 0x28++0x3 line.long 0x0 "GPIOB_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 31. "DIO31,DIO31 event" "0: No effect,1: Clears DIO31 in RIS register" bitfld.long 0x0 30. "DIO30,DIO30 event" "0: No effect,1: Clears DIO30 in RIS register" bitfld.long 0x0 29. "DIO29,DIO29 event" "0: No effect,1: Clears DIO29 in RIS register" newline bitfld.long 0x0 28. "DIO28,DIO28 event" "0: No effect,1: Clears DIO28 in RIS register" bitfld.long 0x0 27. "DIO27,DIO27 event" "0: No effect,1: Clears DIO27 in RIS register" bitfld.long 0x0 26. "DIO26,DIO26 event" "0: No effect,1: Clears DIO26 in RIS register" newline bitfld.long 0x0 25. "DIO25,DIO25 event" "0: No effect,1: Clears DIO25 in RIS register" bitfld.long 0x0 24. "DIO24,DIO24 event" "0: No effect,1: Clears DIO24 in RIS register" bitfld.long 0x0 23. "DIO23,DIO23 event" "0: No effect,1: Clears DIO23 in RIS register" newline bitfld.long 0x0 22. "DIO22,DIO22 event" "0: No effect,1: Clears DIO22 in RIS register" bitfld.long 0x0 21. "DIO21,DIO21 event" "0: No effect,1: Clears DIO21 in RIS register" bitfld.long 0x0 20. "DIO20,DIO20 event" "0: No effect,1: Clears DIO20 in RIS register" newline bitfld.long 0x0 19. "DIO19,DIO19 event" "0: No effect,1: Clears DIO19 in RIS register" bitfld.long 0x0 18. "DIO18,DIO18 event" "0: No effect,1: Clears DIO18 in RIS register" bitfld.long 0x0 17. "DIO17,DIO17 event" "0: No effect,1: Clears DIO17 in RIS register" newline bitfld.long 0x0 16. "DIO16,DIO16 event" "0: No effect,1: Clears DIO16 in RIS register" tree.end base ad:0x400A2000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "GPIOB_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "GPIOB_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" wgroup.long 0x1200++0x1F line.long 0x0 "GPIOB_DOUT3_0,Data output 3 to 0" bitfld.long 0x0 24. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "GPIOB_DOUT7_4,Data output 7 to 4" bitfld.long 0x4 24. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "GPIOB_DOUT11_8,Data output 11 to 8" bitfld.long 0x8 24. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0xC "GPIOB_DOUT15_12,Data output 15 to 12" bitfld.long 0xC 24. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 16. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0xC 8. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0xC 0. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x10 "GPIOB_DOUT19_16,Data output 19 to 16" bitfld.long 0x10 24. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 16. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x10 8. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x10 0. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x14 "GPIOB_DOUT23_20,Data output 23 to 20" bitfld.long 0x14 24. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 16. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x14 8. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x14 0. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x18 "GPIOB_DOUT27_24,Data output 27 to 24" bitfld.long 0x18 24. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 16. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x18 8. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x18 0. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x1C "GPIOB_DOUT31_28,Data output 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 16. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x1C 8. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x1C 0. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1280++0x3 line.long 0x0 "GPIOB_DOUT31_0,Data output 31 to 0" bitfld.long 0x0 31. "DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 30. "DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 29. "DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 28. "DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 27. "DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 26. "DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 25. "DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 24. "DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 23. "DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 22. "DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 21. "DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 20. "DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 19. "DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 18. "DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 17. "DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 15. "DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 14. "DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 13. "DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 12. "DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 11. "DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 10. "DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 9. "DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 8. "DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 7. "DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 6. "DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 5. "DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 4. "DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 3. "DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 2. "DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 1. "DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: Output is set to 0,1: Output is set to 1" wgroup.long 0x1290++0x3 line.long 0x0 "GPIOB_DOUTSET31_0,Data output set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOUT31_0" wgroup.long 0x12A0++0x3 line.long 0x0 "GPIOB_DOUTCLR31_0,Data output clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOUT31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOUT31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOUT31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOUT31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOUT31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOUT31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOUT31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOUT31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOUT31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOUT31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOUT31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOUT31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOUT31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOUT31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOUT31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOUT31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOUT31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOUT31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOUT31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOUT31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOUT31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOUT31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOUT31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOUT31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOUT31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOUT31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOUT31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOUT31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOUT31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOUT31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOUT31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOUT31_0" wgroup.long 0x12B0++0x3 line.long 0x0 "GPIOB_DOUTTGL31_0,Data output toggle 31 to 0" bitfld.long 0x0 31. "DIO31,This bit is used to toggle DIO31 output." "0: No effect,1: Toggle output" bitfld.long 0x0 30. "DIO30,This bit is used to toggle DIO30 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 29. "DIO29,This bit is used to toggle DIO29 output." "0: No effect,1: Toggle output" bitfld.long 0x0 28. "DIO28,This bit is used to toggle DIO28 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 27. "DIO27,This bit is used to toggle DIO27 output." "0: No effect,1: Toggle output" bitfld.long 0x0 26. "DIO26,This bit is used to toggle DIO26 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 25. "DIO25,This bit is used to toggle DIO25 output." "0: No effect,1: Toggle output" bitfld.long 0x0 24. "DIO24,This bit is used to toggle DIO24 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 23. "DIO23,This bit is used to toggle DIO23 output." "0: No effect,1: Toggle output" bitfld.long 0x0 22. "DIO22,This bit is used to toggle DIO22 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 21. "DIO21,This bit is used to toggle DIO21 output." "0: No effect,1: Toggle output" bitfld.long 0x0 20. "DIO20,This bit is used to toggle DIO20 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 19. "DIO19,This bit is used to toggle DIO19 output." "0: No effect,1: Toggle output" bitfld.long 0x0 18. "DIO18,This bit is used to toggle DIO18 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 17. "DIO17,This bit is used to toggle DIO17 output." "0: No effect,1: Toggle output" bitfld.long 0x0 16. "DIO16,This bit is used to toggle DIO16 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 15. "DIO15,This bit is used to toggle DIO15 output." "0: No effect,1: Toggle output" bitfld.long 0x0 14. "DIO14,This bit is used to toggle DIO14 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 13. "DIO13,This bit is used to toggle DIO13 output." "0: No effect,1: Toggle output" bitfld.long 0x0 12. "DIO12,This bit is used to toggle DIO12 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 11. "DIO11,This bit is used to toggle DIO11 output." "0: No effect,1: Toggle output" bitfld.long 0x0 10. "DIO10,This bit is used to toggle DIO10 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 9. "DIO9,This bit is used to toggle DIO9 output." "0: No effect,1: Toggle output" bitfld.long 0x0 8. "DIO8,This bit is used to toggle DIO8 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 7. "DIO7,This bit is used to toggle DIO7 output." "0: No effect,1: Toggle output" bitfld.long 0x0 6. "DIO6,This bit is used to toggle DIO6 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 5. "DIO5,This bit is used to toggle DIO5 output." "0: No effect,1: Toggle output" bitfld.long 0x0 4. "DIO4,This bit is used to toggle DIO4 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 3. "DIO3,This bit is used to toggle DIO3 output." "0: No effect,1: Toggle output" bitfld.long 0x0 2. "DIO2,This bit is used to toggle DIO2 output." "0: No effect,1: Toggle output" newline bitfld.long 0x0 1. "DIO1,This bit is used to toggle DIO1 output." "0: No effect,1: Toggle output" bitfld.long 0x0 0. "DIO0,This bit is used to toggle DIO0 output." "0: No effect,1: Toggle output" group.long 0x12C0++0x3 line.long 0x0 "GPIOB_DOE31_0,Data output enable 31 to 0" bitfld.long 0x0 31. "DIO31,Enables data output for DIO31." "0: Output disabled,1: Output enabled" bitfld.long 0x0 30. "DIO30,Enables data output for DIO30." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 29. "DIO29,Enables data output for DIO29." "0: Output disabled,1: Output enabled" bitfld.long 0x0 28. "DIO28,Enables data output for DIO28." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 27. "DIO27,Enables data output for DIO27." "0: Output disabled,1: Output enabled" bitfld.long 0x0 26. "DIO26,Enables data output for DIO26." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 25. "DIO25,Enables data output for DIO25." "0: Output disabled,1: Output enabled" bitfld.long 0x0 24. "DIO24,Enables data output for DIO24." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 23. "DIO23,Enables data output for DIO23." "0: Output disabled,1: Output enabled" bitfld.long 0x0 22. "DIO22,Enables data output for DIO22." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 21. "DIO21,Enables data output for DIO21." "0: Output disabled,1: Output enabled" bitfld.long 0x0 20. "DIO20,Enables data output for DIO20." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 19. "DIO19,Enables data output for DIO19." "0: Output disabled,1: Output enabled" bitfld.long 0x0 18. "DIO18,Enables data output for DIO18." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 17. "DIO17,Enables data output for DIO17." "0: Output disabled,1: Output enabled" bitfld.long 0x0 16. "DIO16,Enables data output for DIO16." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 15. "DIO15,Enables data output for DIO15." "0: Output disabled,1: Output enabled" bitfld.long 0x0 14. "DIO14,Enables data output for DIO14." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 13. "DIO13,Enables data output for DIO13." "0: Output disabled,1: Output enabled" bitfld.long 0x0 12. "DIO12,Enables data output for DIO12." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 11. "DIO11,Enables data output for DIO11." "0: Output disabled,1: Output enabled" bitfld.long 0x0 10. "DIO10,Enables data output for DIO10." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 9. "DIO9,Enables data output for DIO9." "0: Output disabled,1: Output enabled" bitfld.long 0x0 8. "DIO8,Enables data output for DIO8." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 7. "DIO7,Enables data output for DIO7." "0: Output disabled,1: Output enabled" bitfld.long 0x0 6. "DIO6,Enables data output for DIO6." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 5. "DIO5,Enables data output for DIO5." "0: Output disabled,1: Output enabled" bitfld.long 0x0 4. "DIO4,Enables data output for DIO4." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 3. "DIO3,Enables data output for DIO3." "0: Output disabled,1: Output enabled" bitfld.long 0x0 2. "DIO2,Enables data output for DIO2." "0: Output disabled,1: Output enabled" newline bitfld.long 0x0 1. "DIO1,Enables data output for DIO1." "0: Output disabled,1: Output enabled" bitfld.long 0x0 0. "DIO0,Enables data output for DIO0." "0: Output disabled,1: Output enabled" wgroup.long 0x12D0++0x3 line.long 0x0 "GPIOB_DOESET31_0,Data output enable set 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Sets DIO0 in DOE31_0" wgroup.long 0x12E0++0x3 line.long 0x0 "GPIOB_DOECLR31_0,Data output enable clear 31 to 0" bitfld.long 0x0 31. "DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO31 in DOE31_0" bitfld.long 0x0 30. "DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO30 in DOE31_0" newline bitfld.long 0x0 29. "DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO29 in DOE31_0" bitfld.long 0x0 28. "DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO28 in DOE31_0" newline bitfld.long 0x0 27. "DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO27 in DOE31_0" bitfld.long 0x0 26. "DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO26 in DOE31_0" newline bitfld.long 0x0 25. "DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO25 in DOE31_0" bitfld.long 0x0 24. "DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO24 in DOE31_0" newline bitfld.long 0x0 23. "DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO23 in DOE31_0" bitfld.long 0x0 22. "DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO22 in DOE31_0" newline bitfld.long 0x0 21. "DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO21 in DOE31_0" bitfld.long 0x0 20. "DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO20 in DOE31_0" newline bitfld.long 0x0 19. "DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO19 in DOE31_0" bitfld.long 0x0 18. "DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO18 in DOE31_0" newline bitfld.long 0x0 17. "DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO17 in DOE31_0" bitfld.long 0x0 16. "DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO16 in DOE31_0" newline bitfld.long 0x0 15. "DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO15 in DOE31_0" bitfld.long 0x0 14. "DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO14 in DOE31_0" newline bitfld.long 0x0 13. "DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO13 in DOE31_0" bitfld.long 0x0 12. "DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO12 in DOE31_0" newline bitfld.long 0x0 11. "DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO11 in DOE31_0" bitfld.long 0x0 10. "DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO10 in DOE31_0" newline bitfld.long 0x0 9. "DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO9 in DOE31_0" bitfld.long 0x0 8. "DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO8 in DOE31_0" newline bitfld.long 0x0 7. "DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO7 in DOE31_0" bitfld.long 0x0 6. "DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO6 in DOE31_0" newline bitfld.long 0x0 5. "DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO5 in DOE31_0" bitfld.long 0x0 4. "DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO4 in DOE31_0" newline bitfld.long 0x0 3. "DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO3 in DOE31_0" bitfld.long 0x0 2. "DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO2 in DOE31_0" newline bitfld.long 0x0 1. "DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO1 in DOE31_0" bitfld.long 0x0 0. "DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: No effect,1: Clears DIO0 in DOE31_0" rgroup.long 0x1300++0x1F line.long 0x0 "GPIOB_DIN3_0,Data input 3 to 0" bitfld.long 0x0 24. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" line.long 0x4 "GPIOB_DIN7_4,Data input 7 to 4" bitfld.long 0x4 24. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" line.long 0x8 "GPIOB_DIN11_8,Data input 11 to 8" bitfld.long 0x8 24. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" line.long 0xC "GPIOB_DIN15_12,Data input 15 to 12" bitfld.long 0xC 24. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 16. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0xC 8. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0xC 0. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" line.long 0x10 "GPIOB_DIN19_16,Data input 19 to 16" bitfld.long 0x10 24. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 16. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x10 8. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x10 0. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" line.long 0x14 "GPIOB_DIN23_20,Data input 23 to 20" bitfld.long 0x14 24. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 16. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x14 8. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x14 0. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" line.long 0x18 "GPIOB_DIN27_24,Data input 27 to 24" bitfld.long 0x18 24. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 16. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x18 8. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x18 0. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" line.long 0x1C "GPIOB_DIN31_28,Data input 31 to 28" bitfld.long 0x1C 24. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 16. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x1C 8. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x1C 0. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" rgroup.long 0x1380++0x3 line.long 0x0 "GPIOB_DIN31_0,Data input 31 to 0" bitfld.long 0x0 31. "DIO31,This bit reads the data input value of DIO31." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 30. "DIO30,This bit reads the data input value of DIO30." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 29. "DIO29,This bit reads the data input value of DIO29." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 28. "DIO28,This bit reads the data input value of DIO28." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 27. "DIO27,This bit reads the data input value of DIO27." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 26. "DIO26,This bit reads the data input value of DIO26." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 25. "DIO25,This bit reads the data input value of DIO25." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 24. "DIO24,This bit reads the data input value of DIO24." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 23. "DIO23,This bit reads the data input value of DIO23." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 22. "DIO22,This bit reads the data input value of DIO22." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 21. "DIO21,This bit reads the data input value of DIO21." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 20. "DIO20,This bit reads the data input value of DIO20." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 19. "DIO19,This bit reads the data input value of DIO19." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 18. "DIO18,This bit reads the data input value of DIO18." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 17. "DIO17,This bit reads the data input value of DIO17." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "DIO16,This bit reads the data input value of DIO16." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 15. "DIO15,This bit reads the data input value of DIO15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 14. "DIO14,This bit reads the data input value of DIO14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 13. "DIO13,This bit reads the data input value of DIO13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 12. "DIO12,This bit reads the data input value of DIO12." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 11. "DIO11,This bit reads the data input value of DIO11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 10. "DIO10,This bit reads the data input value of DIO10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 9. "DIO9,This bit reads the data input value of DIO9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 8. "DIO8,This bit reads the data input value of DIO8." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 7. "DIO7,This bit reads the data input value of DIO7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 6. "DIO6,This bit reads the data input value of DIO6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 5. "DIO5,This bit reads the data input value of DIO5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 4. "DIO4,This bit reads the data input value of DIO4." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 3. "DIO3,This bit reads the data input value of DIO3." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 2. "DIO2,This bit reads the data input value of DIO2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 1. "DIO1,This bit reads the data input value of DIO1." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "DIO0,This bit reads the data input value of DIO0." "0: Input value is 0,1: Input value is 1" group.long 0x1390++0x3 line.long 0x0 "GPIOB_POLARITY15_0,Polarity 15 to 0" bitfld.long 0x0 30.--31. "DIO15,Enables and configures edge detection polarity for DIO15." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO14,Enables and configures edge detection polarity for DIO14." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO13,Enables and configures edge detection polarity for DIO13." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO12,Enables and configures edge detection polarity for DIO12." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO11,Enables and configures edge detection polarity for DIO11." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO10,Enables and configures edge detection polarity for DIO10." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO9,Enables and configures edge detection polarity for DIO9." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO8,Enables and configures edge detection polarity for DIO8." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO7,Enables and configures edge detection polarity for DIO7." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO6,Enables and configures edge detection polarity for DIO6." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO5,Enables and configures edge detection polarity for DIO5." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO4,Enables and configures edge detection polarity for DIO4." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO3,Enables and configures edge detection polarity for DIO3." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO2,Enables and configures edge detection polarity for DIO2." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO1,Enables and configures edge detection polarity for DIO1." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO0,Enables and configures edge detection polarity for DIO0." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x13A0++0x3 line.long 0x0 "GPIOB_POLARITY31_16,Polarity 31 to 16" bitfld.long 0x0 30.--31. "DIO31,Enables and configures edge detection polarity for DIO31." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 28.--29. "DIO30,Enables and configures edge detection polarity for DIO30." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 26.--27. "DIO29,Enables and configures edge detection polarity for DIO29." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 24.--25. "DIO28,Enables and configures edge detection polarity for DIO28." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 22.--23. "DIO27,Enables and configures edge detection polarity for DIO27." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 20.--21. "DIO26,Enables and configures edge detection polarity for DIO26." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 18.--19. "DIO25,Enables and configures edge detection polarity for DIO25." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 16.--17. "DIO24,Enables and configures edge detection polarity for DIO24." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 14.--15. "DIO23,Enables and configures edge detection polarity for DIO23." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 12.--13. "DIO22,Enables and configures edge detection polarity for DIO22." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 10.--11. "DIO21,Enables and configures edge detection polarity for DIO21." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 8.--9. "DIO20,Enables and configures edge detection polarity for DIO20." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 6.--7. "DIO19,Enables and configures edge detection polarity for DIO19." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 4.--5. "DIO18,Enables and configures edge detection polarity for DIO18." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 2.--3. "DIO17,Enables and configures edge detection polarity for DIO17." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." bitfld.long 0x0 0.--1. "DIO16,Enables and configures edge detection polarity for DIO16." "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." group.long 0x1400++0x7 line.long 0x0 "GPIOB_CTL,FAST WAKE GLOBAL EN" bitfld.long 0x0 0. "FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: The global control of fastwake is not enabled..,1: The global control of fastwake is enabled" line.long 0x4 "GPIOB_FASTWAKE,FAST WAKE ENABLE" bitfld.long 0x4 31. "DIN31,Enable fastwake feature for DIN31" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 30. "DIN30,Enable fastwake feature for DIN30" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 29. "DIN29,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 28. "DIN28,Enable fastwake feature for DIN29" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 27. "DIN27,Enable fastwake feature for DIN27" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 26. "DIN26,Enable fastwake feature for DIN26" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 25. "DIN25,Enable fastwake feature for DIN25" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 24. "DIN24,Enable fastwake feature for DIN24" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 23. "DIN23,Enable fastwake feature for DIN23" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 22. "DIN22,Enable fastwake feature for DIN22" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 21. "DIN21,Enable fastwake feature for DIN21" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 20. "DIN20,Enable fastwake feature for DIN20" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 19. "DIN19,Enable fastwake feature for DIN19" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 18. "DIN18,Enable fastwake feature for DIN18" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 17. "DIN17,Enable fastwake feature for DIN17" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 16. "DIN16,Enable fastwake feature for DIN16" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 15. "DIN15,Enable fastwake feature for DIN15" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 14. "DIN14,Enable fastwake feature for DIN14" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 13. "DIN13,Enable fastwake feature for DIN13" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 12. "DIN12,Enable fastwake feature for DIN12" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 11. "DIN11,Enable fastwake feature for DIN11" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 10. "DIN10,Enable fastwake feature for DIN10" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 9. "DIN9,Enable fastwake feature for DIN9" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 8. "DIN8,Enable fastwake feature for DIN8" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 7. "DIN7,Enable fastwake feature for DIN7" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 6. "DIN6,Enable fastwake feature for DIN6" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 5. "DIN5,Enable fastwake feature for DIN5" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 4. "DIN4,Enable fastwake feature for DIN4" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 3. "DIN3,Enable fastwake feature for DIN3" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 2. "DIN2,Enable fastwake feature for DIN2" "0: fastwake feature is disabled,1: fastwake feature is enabled" newline bitfld.long 0x4 1. "DIN1,Enable fastwake feature for DIN1" "0: fastwake feature is disabled,1: fastwake feature is enabled" bitfld.long 0x4 0. "DIN0,Enable fastwake feature for DIN0" "0: fastwake feature is disabled,1: fastwake feature is enabled" group.long 0x1500++0x3 line.long 0x0 "GPIOB_SUB0CFG,Subscriber 0 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 0 event." "0: Subscriber 0 event is disabled,1: Subscriber 0 event is enabled" group.long 0x1508++0xB line.long 0x0 "GPIOB_FILTEREN15_0,Filter Enable 15 to 0" bitfld.long 0x0 30.--31. "DIN15,Programmable counter length of digital glitch filter for DIN15" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 28.--29. "DIN14,Programmable counter length of digital glitch filter for DIN14" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 26.--27. "DIN13,Programmable counter length of digital glitch filter for DIN13" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 24.--25. "DIN12,Programmable counter length of digital glitch filter for DIN12" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 22.--23. "DIN11,Programmable counter length of digital glitch filter for DIN11" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 20.--21. "DIN10,Programmable counter length of digital glitch filter for DIN10" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 18.--19. "DIN9,Programmable counter length of digital glitch filter for DIN9" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 16.--17. "DIN8,Programmable counter length of digital glitch filter for DIN8" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 14.--15. "DIN7,Programmable counter length of digital glitch filter for DIN7" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 12.--13. "DIN6,Programmable counter length of digital glitch filter for DIN6" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 10.--11. "DIN5,Programmable counter length of digital glitch filter for DIN5" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 8.--9. "DIN4,Programmable counter length of digital glitch filter for DIN4" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 6.--7. "DIN3,Programmable counter length of digital glitch filter for DIN3" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 4.--5. "DIN2,Programmable counter length of digital glitch filter for DIN2" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x0 2.--3. "DIN1,Programmable counter length of digital glitch filter for DIN1" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x0 0.--1. "DIN0,Programmable counter length of digital glitch filter for DIN0" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x4 "GPIOB_FILTEREN31_16,Filter Enable 31 to 16" bitfld.long 0x4 30.--31. "DIN31,Programmable counter length of digital glitch filter for DIN31" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 28.--29. "DIN30,Programmable counter length of digital glitch filter for DIN30" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 26.--27. "DIN29,Programmable counter length of digital glitch filter for DIN29" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 24.--25. "DIN28,Programmable counter length of digital glitch filter for DIN28" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 22.--23. "DIN27,Programmable counter length of digital glitch filter for DIN27" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 20.--21. "DIN26,Programmable counter length of digital glitch filter for DIN26" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 18.--19. "DIN25,Programmable counter length of digital glitch filter for DIN25" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 16.--17. "DIN24,Programmable counter length of digital glitch filter for DIN24" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 14.--15. "DIN23,Programmable counter length of digital glitch filter for DIN23" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 12.--13. "DIN22,Programmable counter length of digital glitch filter for DIN22" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 10.--11. "DIN21,Programmable counter length of digital glitch filter for DIN21" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 8.--9. "DIN20,Programmable counter length of digital glitch filter for DIN20" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 6.--7. "DIN19,Programmable counter length of digital glitch filter for DIN19" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 4.--5. "DIN18,Programmable counter length of digital glitch filter for DIN18" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" newline bitfld.long 0x4 2.--3. "DIN17,Programmable counter length of digital glitch filter for DIN17" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" bitfld.long 0x4 0.--1. "DIN16,Programmable counter length of digital glitch filter for DIN16" "0: No additional filter beyond the CDC..,1: 1 ULPCLK minimum sample,2: 3 ULPCLK minimum sample,3: 8 ULPCLK minimum sample" line.long 0x8 "GPIOB_DMAMASK,DMA Write MASK" bitfld.long 0x8 31. "DOUT31,DMA is allowed to modify DOUT31" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 30. "DOUT30,DMA is allowed to modify DOUT30" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 29. "DOUT29,DMA is allowed to modify DOUT29" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 28. "DOUT28,DMA is allowed to modify DOUT28" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 27. "DOUT27,DMA is allowed to modify DOUT27" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 26. "DOUT26,DMA is allowed to modify DOUT26" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 25. "DOUT25,DMA is allowed to modify DOUT25" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 24. "DOUT24,DMA is allowed to modify DOUT24" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 23. "DOUT23,DMA is allowed to modify DOUT23" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 22. "DOUT22,DMA is allowed to modify DOUT22" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 21. "DOUT21,DMA is allowed to modify DOUT21" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 20. "DOUT20,DMA is allowed to modify DOUT20" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 19. "DOUT19,DMA is allowed to modify DOUT19" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 18. "DOUT18,DMA is allowed to modify DOUT18" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 17. "DOUT17,DMA is allowed to modify DOUT17" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 16. "DOUT16,DMA is allowed to modify DOUT16" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 15. "DOUT15,DMA is allowed to modify DOUT15" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 14. "DOUT14,DMA is allowed to modify DOUT14" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 13. "DOUT13,DMA is allowed to modify DOUT13" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 12. "DOUT12,DMA is allowed to modify DOUT12" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 11. "DOUT11,DMA is allowed to modify DOUT11" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 10. "DOUT10,DMA is allowed to modify DOUT10" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 9. "DOUT9,DMA is allowed to modify DOUT9" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 8. "DOUT8,DMA is allowed to modify DOUT8" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 7. "DOUT7,DMA is allowed to modify DOUT7" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 6. "DOUT6,DMA is allowed to modify DOUT6" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 5. "DOUT5,DMA is allowed to modify DOUT5" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 4. "DOUT4,DMA is allowed to modify DOUT4" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 3. "DOUT3,DMA is allowed to modify DOUT3" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 2. "DOUT2,DMA is allowed to modify DOUT2" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" newline bitfld.long 0x8 1. "DOUT1,DMA is allowed to modify DOUT1" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" bitfld.long 0x8 0. "DOUT0,DMA is allowed to modify DOUT0" "0: DMA is not allowed to modify this bit lane,1: DMA is allowed to modify this bit lane" group.long 0x1520++0x3 line.long 0x0 "GPIOB_SUB1CFG,Subscriber 1 configuration" hexmask.long.byte 0x0 16.--19. 1. "INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action" bitfld.long 0x0 8.--9. "OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: Selected DIO pins are set,1: Selected DIO pins are cleared,2: Selected DIO pins are toggled,?" newline bitfld.long 0x0 0. "ENABLE,This bit is used to enable subscriber 1 event." "0: Subscriber 1 event is disabled,1: Subscriber 1 event is enabled" tree.end endif tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0x0 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) tree "I2C0" base ad:0x400F0000 tree "I2C0_GPRCM[%s]" base ad:0x400F0800 group.long 0x0++0x3 line.long 0x0 "I2C0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "I2C0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "I2C0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "I2C0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400F0000 newline group.long 0x1000++0x7 newline line.long 0x0 "I2C0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "I2C0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "I2C0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "I2C0_INT_EVENT0[%s]" base ad:0x400F1020 rgroup.long 0x0++0x3 line.long 0x0 "I2C0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 31. "INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 30. "SARBLOST,Slave Arbitration Lost" "0: Clear Set Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 29. "SRX_OVFL,Slave RX FIFO overflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 28. "STX_UNFL,Slave TX FIFO underflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 27. "SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 26. "SDMA_DONE_RX,Slave DMA Done on Event Channel RX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 25. "SDMA_DONE_TX,Slave DMA Done on Event Channel TX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 24. "SGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 23. "SSTOP,Stop Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 22. "SSTART,Start Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 21. "STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 20. "SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "STXDONE,Slave Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "SRXDONE,Slave Receive Data Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "MDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "MDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "MARBLOST,Arbitration Lost Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "MSTOP,STOP Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "MSTART,START Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "MNACK,Address/Data NACK Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXDONE,Master Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXDONE,Master Receive Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "SARBLOST,Slave Arbitration Lost" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 29. "SRX_OVFL,Slave RX FIFO overflow" "0: Interrupt did not occur,1: Interrupt Occured" newline bitfld.long 0x0 28. "STX_UNFL,Slave TX FIFO underflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 27. "SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt ocuured" bitfld.long 0x0 26. "SDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear interrupt,1: Set interrupt" newline bitfld.long 0x0 25. "SDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear interrupt,1: Set interrupt" bitfld.long 0x0 24. "SGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 23. "SSTOP,Stop Condition Interrupt" "0: Clear Interrupt,1: Set interrupt" newline bitfld.long 0x0 22. "SSTART,Start Condition Interrupt" "0: Clear interrupt,1: Set Interrupt" bitfld.long 0x0 21. "STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 20. "SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "STXDONE,Slave Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "SRXDONE,Slave Receive Data Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt Occured" bitfld.long 0x0 12. "MDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "MDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "MARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 9. "MSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 8. "MSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "MNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 5. "MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 4. "MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXDONE,Master Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXDONE,Master Receive Transaction completed Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "SARBLOST,Slave Arbitration Lost" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 29. "SRX_OVFL,Slave RX FIFO overflow" "0: Clear interrupt mask,1: Set interrupt mask" newline bitfld.long 0x0 28. "STX_UNFL,Slave TX FIFO underflow" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 27. "SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 26. "SDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 25. "SDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 24. "SGENCALL,General Call Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 23. "SSTOP,Slave STOP Detection Interrupt" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 22. "SSTART,Slave START Detection Interrupt" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 21. "STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 20. "SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "STXDONE,Slave Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "SRXDONE,Slave Receive Data Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 12. "MDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "MDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "MARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 9. "MSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 8. "MSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "MNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 5. "MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Set Interrupt Mask" bitfld.long 0x0 4. "MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXDONE,Master Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXDONE,Master Receive Data Interrupt" "0: Interrupt did not occur,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Set interrupt" bitfld.long 0x0 30. "SARBLOST,Slave Arbitration Lost" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 29. "SRX_OVFL,Slave RX FIFO overflow" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 28. "STX_UNFL,Slave TX FIFO underflow" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 27. "SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 26. "SDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 25. "SDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 24. "SGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 23. "SSTOP,Stop Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 22. "SSTART,Start Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 21. "STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 20. "SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "STXDONE,Slave Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "SRXDONE,Slave Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "MDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "MDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "MARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 9. "MSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 8. "MSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "MNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 5. "MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 4. "MRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXDONE,Master Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXDONE,Master Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Clear interrupt" bitfld.long 0x0 30. "SARBLOST,Slave Arbitration Lost" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 29. "SRX_OVFL,Slave RX FIFO overflow" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 28. "STX_UNFL,Slave TX FIFO underflow" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 27. "SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 26. "SDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 25. "SDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 24. "SGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 23. "SSTOP,Slave STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 22. "SSTART,Slave START Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 21. "STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 20. "SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "STXDONE,Slave Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "SRXDONE,Slave Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "MDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "MDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "MARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 9. "MSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 8. "MSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "MNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 5. "MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt Mask" bitfld.long 0x0 4. "MRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXDONE,Master Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXDONE,Master Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "I2C0_INT_EVENT1[%s]" base ad:0x400F1050 rgroup.long 0x0++0x3 line.long 0x0 "I2C0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end tree "I2C0_INT_EVENT2[%s]" base ad:0x400F1080 rgroup.long 0x0++0x3 line.long 0x0 "I2C0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 3. "STXFIFOTRG,Slave Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "SRXFIFOTRG,Slave Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "MTXFIFOTRG,Master Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "MRXFIFOTRG,Master Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end base ad:0x400F0000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "I2C0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "I2C0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." rgroup.long 0x10FC++0x3 line.long 0x0 "I2C0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1200++0x7 line.long 0x0 "I2C0_GFCTL,I2C Glitch Filter Control" bitfld.long 0x0 11. "CHAIN,Analog and digital noise filters chaining enable." "0: When 0 chaining is disabled and only digital..,1: When 1 analog and digital glitch filters are.." bitfld.long 0x0 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0x0 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" bitfld.long 0x0 0.--2. "DGFSEL,Glitch Suppression Pulse Width" "0: Bypass,1: 1 clock,2: 2 clocks,3: 3 clocks,4: 4 clocks,5: 8 clocks,6: 16 clocks,7: 31 clocks" line.long 0x4 "I2C0_TIMEOUT_CTL,I2C Timeout Count Control Register" bitfld.long 0x4 31. "TCNTBEN,Timeout Counter B Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 16.--23. 1. "TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h." newline bitfld.long 0x4 15. "TCNTAEN,Timeout Counter A Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 0.--7. 1. "TCNTLA,Timeout counter A load value" rgroup.long 0x1208++0x3 line.long 0x0 "I2C0_TIMEOUT_CNT,I2C Timeout Count Register" hexmask.long.byte 0x0 16.--23. 1. "TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B" hexmask.long.byte 0x0 0.--7. 1. "TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A" tree "I2C0_MASTER[%s]" base ad:0x400F1210 group.long 0x0++0x7 line.long 0x0 "I2C0_MSA,I2C Master Slave Address Register" bitfld.long 0x0 15. "MMODE,This bit selects the adressing mode to be used in master mode" "0: 7-bit addressing mode,1: 10-bit addressing mode" newline hexmask.long.word 0x0 1.--10. 1. "SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address." newline bitfld.long 0x0 0. "DIR,Receive/Send" "0: The master is in transmit mode.,1: The master is in receive mode." line.long 0x4 "I2C0_MCTR,I2C Master Control Register" hexmask.long.word 0x4 16.--27. 1. "MBLEN,I2C transaction length" newline bitfld.long 0x4 5. "RD_ON_TXEMPTY,Read on TX Empty" "0: No special behavior,1: When 1 the master will transmit all bytes from.." newline bitfld.long 0x4 4. "MACKOEN,Master ACK overrride Enable" "0: No special behavior,1: When 1 and the master is receiving data and the.." newline bitfld.long 0x4 3. "ACK,Data Acknowledge Enable." "0: The last received data byte of a transaction is..,1: The last received data byte of a transaction is.." newline bitfld.long 0x4 2. "STOP,Generate STOP" "0: The controller does not generate the STOP..,1: The controller generates the STOP condition. See.." newline bitfld.long 0x4 1. "START,Generate START" "0: The controller does not generate the START..,1: The controller generates the START or repeated.." newline bitfld.long 0x4 0. "BURSTRUN,I2C Master Enable" "0: In standard mode this encoding means the master..,1: The master is able to transmit or receive data." rgroup.long 0x8++0x7 line.long 0x0 "I2C0_MSR,I2C Master Status Register" hexmask.long.word 0x0 16.--27. 1. "MBCNT,I2C Master Transaction Count" newline bitfld.long 0x0 6. "BUSBSY,I2C Bus is Busy" "0: The I2C bus is idle.,1: 'This Status bit is set on a START or when SCL.." newline bitfld.long 0x0 5. "IDLE,I2C Idle" "0: The I2C controller is not idle.,1: The I2C controller is idle." newline bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0: The I2C controller won arbitration.,1: The I2C controller lost arbitration." newline bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0: The transmitted data was acknowledged,1: The transmitted data was not acknowledged." newline bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0: The transmitted address was acknowledged,1: The transmitted address was not acknowledged." newline bitfld.long 0x0 1. "ERR,Error" "0: No error was detected on the last operation.,1: An error occurred on the last operation." newline bitfld.long 0x0 0. "BUSY,I2C Master FSM Busy" "0: The controller is idle.,1: The controller is busy." line.long 0x4 "I2C0_MRXDATA,I2C Master RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x10++0xB line.long 0x0 "I2C0_MTXDATA,I2C Master TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C0_MTPR,I2C Master Timer Period" hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period" line.long 0x8 "I2C0_MCR,I2C Master Configuration" bitfld.long 0x8 8. "LPBK,I2C Loopback" "0: Normal operation.,1: The controller in a test mode loopback.." newline bitfld.long 0x8 2. "CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: Disables the clock stretching detection. This..,1: Enables the clock stretching detection. Enabling.." newline bitfld.long 0x8 1. "MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: Disable Multimaster mode.,1: Enable Multimaster mode." newline bitfld.long 0x8 0. "ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: Disables the I2C master operation.,1: Enables the I2C master operation." rgroup.long 0x24++0x3 line.long 0x0 "I2C0_MBMON,I2C Master Bus Monitor" bitfld.long 0x0 1. "SDA,I2C SDA Status" "0: The I2CSDA signal is low.,1: The I2CSDA signal is high. Note: During and.." newline bitfld.long 0x0 0. "SCL,I2C SCL Status" "0: The I2CSCL signal is low.,1: The I2CSCL signal is high. Note: During and.." group.long 0x28++0x3 line.long 0x0 "I2C0_MFIFOCTL,I2C Master FIFO Control" bitfld.long 0x0 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 8.--10. "RXTRIG,RX FIFO Trigger" "0: Trigger when RX FIFO contains >= 1 byte,1: Trigger when RX FIFO contains >= 2 byte,2: Trigger when RX FIFO contains >= 3 byte,3: Trigger when RX FIFO contains >= 4 byte,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x0 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0: Trigger when the TX FIFO is empty.,1: Trigger when TX FIFO contains 1 byte,2: Trigger when TX FIFO contains 2 byte,3: Trigger when TX FIFO contains 3 byte,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x2C++0x3 line.long 0x0 "I2C0_MFIFOSR,I2C Master FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x30++0x3 line.long 0x0 "I2C0_MASTER_I2CPECCTL,I2C master PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC is disabled in master mode,1: PEC is enabled in master mode" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,PEC Count" rgroup.long 0x34++0x3 line.long 0x0 "I2C0_MASTER_PECSR,I2C master PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates if a PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates if the PEC was checked in the.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,PEC Byte Count" tree.end tree "I2C0_SLAVE[%s]" base ad:0x400F1250 group.long 0x0++0xB line.long 0x0 "I2C0_SOAR,I2C Slave Own Address" bitfld.long 0x0 15. "SMODE,This bit selects the adressing mode to be used in slave mode." "0: Enable 7-bit addressing,1: Enable 10-bit addressing" newline bitfld.long 0x0 14. "OAREN,I2C Slave Own Address Enable" "0: Disable OAR address,1: Enable OAR address" newline hexmask.long.word 0x0 0.--9. 1. "OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address." line.long 0x4 "I2C0_SOAR2,I2C Slave Own Address 2" hexmask.long.byte 0x4 16.--22. 1. "OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address." newline bitfld.long 0x4 7. "OAR2EN,I2C Slave Own Address 2 Enable" "0: The alternate address is disabled.,1: Enables the use of the alternate address in the.." newline hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Slave Own Address 2" line.long 0x8 "I2C0_SCTR,I2C Slave Control Register" bitfld.long 0x8 10. "SWUEN,Slave Wakeup Enable" "0: When 0 the slave is not allowed to clock stretch..,1: When 1 the slave is allowed to clock stretch on.." newline bitfld.long 0x8 9. "EN_DEFDEVADR,Enable Deault device address" "0: When this bit is 0 the default device address is..,1: When this bit is 1 default device address of.." newline bitfld.long 0x8 8. "EN_ALRESPADR,Enable Alert Response Address" "0: When this bit is 0 the alert response address is..,1: When this bit is 1 alert response address of.." newline bitfld.long 0x8 7. "EN_DEFHOSTADR,Enable Default Host Address" "0: When this bit is 0 the default host address is..,1: When this bit is 1 default host address of.." newline bitfld.long 0x8 6. "RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: When 0 RIS:SRXFULL will be set when only the..,1: When 1 RIS:SRXFULL will be set when the Slave.." newline bitfld.long 0x8 5. "TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: When 0 the TX FIFO empty signal to the Slave..,1: When 1 the TX FIFO empty signal to the Slave.." newline bitfld.long 0x8 4. "TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: No special behavior,1: When 1 RIS:TXFIFOTRG will be set when the Slave.." newline bitfld.long 0x8 3. "TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: When 0 RIS:STXEMPTY will be set when only the..,1: When 1 RIS:STXEMPTY will be set when the Slave.." newline bitfld.long 0x8 2. "SCLKSTRETCH,Slave Clock Stretch Enable" "0: Slave clock stretching is disabled,1: Slave clock stretching is enabled" newline bitfld.long 0x8 1. "GENCALL,General call response enable" "0: Do not respond to a general call,1: Respond to a general call" newline bitfld.long 0x8 0. "ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: Disables the I2C slave operation.,1: Enables the I2C slave operation." rgroup.long 0xC++0x7 line.long 0x0 "I2C0_SSR,I2C Slave Status Register" hexmask.long.word 0x0 9.--18. 1. "ADDRMATCH,Indicates the address for which slave address match happened" newline bitfld.long 0x0 8. "STALE_TXFIFO,Stale Tx FIFO" "0: Tx FIFO is not stale,1: The TX FIFO is stale. This occurs when the TX.." newline bitfld.long 0x0 7. "TXMODE,Slave FSM is in TX MODE" "0: The Slave State Machine is not in TX_DATA..,1: The Slave State Machine is in TX_DATA TX_WAIT.." newline bitfld.long 0x0 6. "BUSBSY,I2C bus is busy" "0: The I2C Bus is not busy,1: The I2C Bus is busy. This is cleared on a timeout." newline rbitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read" newline rbitfld.long 0x0 4. "QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.." newline rbitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0: Either the OAR2 address is not matched or the..,1: OAR2 address matched and ACKed by the slave." newline bitfld.long 0x0 2. "RXMODE,Slave FSM is in Rx MODE" "0: The Slave State Machine is not in the RX_DATA..,1: The Slave State Machine is in the RX_DATA RX_ACK.." newline rbitfld.long 0x0 1. "TREQ,Transmit Request" "0: No outstanding transmit request.,1: The I2C controller has been addressed as a slave.." newline rbitfld.long 0x0 0. "RREQ,Receive Request" "0: No outstanding receive data.,1: The I2C controller has outstanding receive data.." line.long 0x4 "I2C0_SRXDATA,I2C Slave RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x14++0xB line.long 0x0 "I2C0_STXDATA,I2C Slave TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C0_SACKCTL,I2C Slave ACK Control" bitfld.long 0x4 4. "ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 3. "ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 2. "ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 1. "ACKOVAL,I2C Slave ACK Override Value" "0: An ACK is sent indicating valid data or command.,1: A NACK is sent indicating invalid data or command." newline bitfld.long 0x4 0. "ACKOEN,I2C Slave ACK Override Enable" "0: A response in not provided.,1: An ACK or NACK is sent according to the value.." line.long 0x8 "I2C0_SFIFOCTL,I2C Slave FIFO Control" bitfld.long 0x8 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 8.--10. "RXTRIG,RX FIFO Trigger" "?,?,?,?,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x8 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 0.--2. "TXTRIG,TX FIFO Trigger" "?,?,?,?,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x20++0x3 line.long 0x0 "I2C0_SFIFOSR,I2C Slave FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFOFlush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x24++0x3 line.long 0x0 "I2C0_SLAVE_PECCTL,I2C Slave PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC transmission and check is disabled,1: PEC transmission and check is enabled" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO." rgroup.long 0x28++0x3 line.long 0x0 "I2C0_SLAVE_PECSR,I2C slave PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates PEC was checked in the transaction.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine." tree.end tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L110*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPM0L222*")) tree "I2C0" base ad:0x400F0000 tree "I2C0_GPRCM[%s]" base ad:0x400F0800 group.long 0x0++0x3 line.long 0x0 "I2C0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "I2C0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "I2C0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "I2C0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400F0000 newline group.long 0x1000++0x7 newline line.long 0x0 "I2C0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "I2C0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "I2C0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "I2C0_CPU_INT[%s]" base ad:0x400F1020 rgroup.long 0x0++0x3 line.long 0x0 "I2C0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Clear Set Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 26. "TDMA_DONE_RX,Target DMA Done on Event Channel RX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 25. "TDMA_DONE_TX,Target DMA Done on Event Channel TX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 21. "TTXEMPTY,Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an Target RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Interrupt did not occur,1: Interrupt Occured" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt ocuured" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear interrupt,1: Set interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear interrupt,1: Set interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Clear Interrupt,1: Set interrupt" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Clear interrupt,1: Set Interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Interrupt occured" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt Occured" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "I2C0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Clear interrupt mask,1: Set interrupt mask" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 23. "TSTOP,Target STOP Detection Interrupt" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 22. "TSTART,Target START Detection Interrupt" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Interrupt occured" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "I2C0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Set interrupt" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "I2C0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Clear interrupt" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 23. "TSTOP,Target STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 22. "TSTART,Target START Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Clear Interrupt" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "I2C0_DMA_TRIG0[%s]" base ad:0x400F1080 rgroup.long 0x0++0x3 line.long 0x0 "I2C0_DMA_TRIG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C0_DMA_TRIG0_IMASK,Interrupt mask" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C0_DMA_TRIG0_RIS,Raw interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C0_DMA_TRIG0_MIS,Masked interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C0_DMA_TRIG0_ISET,Interrupt set" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C0_DMA_TRIG0_ICLR,Interrupt clear" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end tree "I2C0_DMA_TRIG1[%s]" base ad:0x400F1050 rgroup.long 0x0++0x3 line.long 0x0 "I2C0_DMA_TRIG1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C0_DMA_TRIG1_IMASK,Interrupt mask" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C0_DMA_TRIG1_RIS,Raw interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C0_DMA_TRIG1_MIS,Masked interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C0_DMA_TRIG1_ISET,Interrupt set" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C0_DMA_TRIG1_ICLR,Interrupt clear" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end base ad:0x400F0000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "I2C0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "I2C0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." rgroup.long 0x10FC++0x3 line.long 0x0 "I2C0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1200++0x7 line.long 0x0 "I2C0_GFCTL,I2C Glitch Filter Control" bitfld.long 0x0 11. "CHAIN,Analog and digital noise filters chaining enable." "0: When 0 chaining is disabled and only digital..,1: When 1 analog and digital glitch filters are.." bitfld.long 0x0 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0x0 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" bitfld.long 0x0 0.--2. "DGFSEL,Glitch Suppression Pulse Width" "0: Bypass,1: 1 clock,2: 2 clocks,3: 3 clocks,4: 4 clocks,5: 8 clocks,6: 16 clocks,7: 31 clocks" line.long 0x4 "I2C0_TIMEOUT_CTL,I2C Timeout Count Control Register" bitfld.long 0x4 31. "TCNTBEN,Timeout Counter B Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 16.--23. 1. "TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h." newline bitfld.long 0x4 15. "TCNTAEN,Timeout Counter A Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 0.--7. 1. "TCNTLA,Timeout counter A load value" rgroup.long 0x1208++0x3 line.long 0x0 "I2C0_TIMEOUT_CNT,I2C Timeout Count Register" hexmask.long.byte 0x0 16.--23. 1. "TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B" hexmask.long.byte 0x0 0.--7. 1. "TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A" tree "I2C0_CONTROLLER[%s]" base ad:0x400F1210 group.long 0x0++0x7 line.long 0x0 "I2C0_CSA,I2C Controller Target Address Register" bitfld.long 0x0 15. "CMODE,This bit selects the adressing mode to be used in Controller mode" "0: 7-bit addressing mode,1: 10-bit addressing mode" newline hexmask.long.word 0x0 1.--10. 1. "TADDR,I2C Target Address This field specifies bits A9 through A0 of the Target address." newline bitfld.long 0x0 0. "DIR,Receive/Send" "0: The Controller is in transmit mode.,1: The Controller is in receive mode." line.long 0x4 "I2C0_CCTR,I2C Controller Control Register" hexmask.long.word 0x4 16.--27. 1. "CBLEN,I2C transaction length" newline bitfld.long 0x4 5. "RD_ON_TXEMPTY,Read on TX Empty" "0: No special behavior,1: When 1 the Controller will transmit all bytes.." newline bitfld.long 0x4 4. "CACKOEN,Controller ACK overrride Enable" "0: No special behavior,1: When 1 and the Controller is receiving data and.." newline bitfld.long 0x4 3. "ACK,Data Acknowledge Enable." "0: The last received data byte of a transaction is..,1: The last received data byte of a transaction is.." newline bitfld.long 0x4 2. "STOP,Generate STOP" "0: The controller does not generate the STOP..,1: The controller generates the STOP condition." newline bitfld.long 0x4 1. "START,Generate START" "0: The controller does not generate the START..,1: The controller generates the START or repeated.." newline bitfld.long 0x4 0. "BURSTRUN,I2C Controller Enable" "0: In standard mode this encoding means the..,1: The Controller is able to transmit or receive.." rgroup.long 0x8++0x7 line.long 0x0 "I2C0_CSR,I2C Controller Status Register" hexmask.long.word 0x0 16.--27. 1. "CBCNT,I2C Controller Transaction Count" newline bitfld.long 0x0 6. "BUSBSY,I2C Bus is Busy" "0: The I2C bus is idle.,1: 'This Status bit is set on a START or when SCL.." newline bitfld.long 0x0 5. "IDLE,I2C Idle" "0: The I2C controller is not idle.,1: The I2C controller is idle." newline bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0: The I2C controller won arbitration.,1: The I2C controller lost arbitration." newline bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0: The transmitted data was acknowledged,1: The transmitted data was not acknowledged." newline bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0: The transmitted address was acknowledged,1: The transmitted address was not acknowledged." newline bitfld.long 0x0 1. "ERR,Error" "0: No error was detected on the last operation.,1: An error occurred on the last operation." newline bitfld.long 0x0 0. "BUSY,I2C Controller FSM Busy" "0: The controller is idle.,1: The controller is busy." line.long 0x4 "I2C0_CRXDATA,I2C Controller RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x10++0xB line.long 0x0 "I2C0_CTXDATA,I2C Controller TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C0_CTPR,I2C Controller Timer Period" hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period" line.long 0x8 "I2C0_CCR,I2C Controller Configuration" bitfld.long 0x8 8. "LPBK,I2C Loopback" "0: Normal operation.,1: The controller in a test mode loopback.." newline bitfld.long 0x8 2. "CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: Disables the clock stretching detection. This..,1: Enables the clock stretching detection. Enabling.." newline bitfld.long 0x8 1. "MCTL,MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: Disable MultiController mode.,1: Enable MultiController mode." newline bitfld.long 0x8 0. "ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: Disables the I2C Controller operation.,1: Enables the I2C Controller operation." rgroup.long 0x24++0x3 line.long 0x0 "I2C0_CBMON,I2C Controller Bus Monitor" bitfld.long 0x0 1. "SDA,I2C SDA Status" "0: The I2CSDA signal is low.,1: The I2CSDA signal is high. Note: During and.." newline bitfld.long 0x0 0. "SCL,I2C SCL Status" "0: The I2CSCL signal is low.,1: The I2CSCL signal is high. Note: During and.." group.long 0x28++0x3 line.long 0x0 "I2C0_CFIFOCTL,I2C Controller FIFO Control" bitfld.long 0x0 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 8.--10. "RXTRIG,RX FIFO Trigger" "0: Trigger when RX FIFO contains >= 1 byte,1: Trigger when RX FIFO contains >= 2 byte,2: Trigger when RX FIFO contains >= 3 byte,3: Trigger when RX FIFO contains >= 4 byte,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x0 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0: Trigger when the TX FIFO is empty.,1: Trigger when TX FIFO contains 1 byte,2: Trigger when TX FIFO contains 2 byte,3: Trigger when TX FIFO contains 3 byte,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x2C++0x3 line.long 0x0 "I2C0_CFIFOSR,I2C Controller FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x30++0x3 line.long 0x0 "I2C0_CONTROLLER_I2CPECCTL,I2C Controller PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC is disabled in Controller mode,1: PEC is enabled in Controller mode" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,PEC Count" rgroup.long 0x34++0x3 line.long 0x0 "I2C0_CONTROLLER_PECSR,I2C Controller PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates if a PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates if the PEC was checked in the.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,PEC Byte Count" tree.end tree "I2C0_TARGET[%s]" base ad:0x400F1250 group.long 0x0++0xB line.long 0x0 "I2C0_TOAR,I2C Target Own Address" bitfld.long 0x0 15. "TMODE,This bit selects the adressing mode to be used in Target mode." "0: Enable 7-bit addressing,1: Enable 10-bit addressing" newline bitfld.long 0x0 14. "OAREN,I2C Target Own Address Enable" "0: Disable OAR address,1: Enable OAR address" newline hexmask.long.word 0x0 0.--9. 1. "OAR,I2C Target Own Address: This field specifies bits A9 through A0 of the Target address." line.long 0x4 "I2C0_TOAR2,I2C Target Own Address 2" hexmask.long.byte 0x4 16.--22. 1. "OAR2_MASK,I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address." newline bitfld.long 0x4 7. "OAR2EN,I2C Target Own Address 2 Enable" "0: The alternate address is disabled.,1: Enables the use of the alternate address in the.." newline hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Target Own Address 2" line.long 0x8 "I2C0_TCTR,I2C Target Control Register" bitfld.long 0x8 10. "TWUEN,Target Wakeup Enable" "0: When 0 the Target is not allowed to clock..,1: When 1 the Target is allowed to clock stretch on.." newline bitfld.long 0x8 9. "EN_DEFDEVADR,Enable Deault device address" "0: When this bit is 0 the default device address is..,1: When this bit is 1 default device address of.." newline bitfld.long 0x8 8. "EN_ALRESPADR,Enable Alert Response Address" "0: When this bit is 0 the alert response address is..,1: When this bit is 1 alert response address of.." newline bitfld.long 0x8 7. "EN_DEFHOSTADR,Enable Default Host Address" "0: When this bit is 0 the default host address is..,1: When this bit is 1 default host address of.." newline bitfld.long 0x8 6. "RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: When 0 RIS:TRXFULL will be set when only the..,1: When 1 RIS:TRXFULL will be set when the Target.." newline bitfld.long 0x8 5. "TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: When 0 the TX FIFO empty signal to the Target..,1: When 1 the TX FIFO empty signal to the Target.." newline bitfld.long 0x8 4. "TXTRIG_TXMODE,Tx Trigger when Target FSM is in Tx Mode" "0: No special behavior,1: When 1 RIS:TXFIFOTRG will be set when the Target.." newline bitfld.long 0x8 3. "TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: When 0 RIS:TTXEMPTY will be set when only the..,1: When 1 RIS:TTXEMPTY will be set when the Target.." newline bitfld.long 0x8 2. "TCLKSTRETCH,Target Clock Stretch Enable" "0: Target clock stretching is disabled,1: Target clock stretching is enabled" newline bitfld.long 0x8 1. "GENCALL,General call response enable" "0: Do not respond to a general call,1: Respond to a general call" newline bitfld.long 0x8 0. "ACTIVE,Device Active. Setting this bit enables the Target functionality." "0: Disables the I2C Target operation.,1: Enables the I2C Target operation." rgroup.long 0xC++0x7 line.long 0x0 "I2C0_TSR,I2C Target Status Register" hexmask.long.word 0x0 9.--18. 1. "ADDRMATCH,Indicates the address for which Target address match happened" newline bitfld.long 0x0 8. "STALE_TXFIFO,Stale Tx FIFO" "0: Tx FIFO is not stale,1: The TX FIFO is stale. This occurs when the TX.." newline bitfld.long 0x0 7. "TXMODE,Target FSM is in TX MODE" "0: The Target State Machine is not in TX_DATA..,1: The Target State Machine is in TX_DATA TX_WAIT.." newline bitfld.long 0x0 6. "BUSBSY,I2C bus is busy" "0: The I2C Bus is not busy,1: The I2C Bus is busy. This is cleared on a timeout." newline rbitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read" newline rbitfld.long 0x0 4. "QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.." newline rbitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0: Either the OAR2 address is not matched or the..,1: OAR2 address matched and ACKed by the Target." newline bitfld.long 0x0 2. "RXMODE,Target FSM is in Rx MODE" "0: The Target State Machine is not in the RX_DATA..,1: The Target State Machine is in the RX_DATA.." newline rbitfld.long 0x0 1. "TREQ,Transmit Request" "0: No outstanding transmit request.,1: The I2C controller has been addressed as a.." newline rbitfld.long 0x0 0. "RREQ,Receive Request" "0: No outstanding receive data.,1: The I2C controller has outstanding receive data.." line.long 0x4 "I2C0_TRXDATA,I2C Target RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x14++0xB line.long 0x0 "I2C0_TTXDATA,I2C Target TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C0_TACKCTL,I2C Target ACK Control" bitfld.long 0x4 4. "ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 3. "ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 2. "ACKOEN_ON_START,When set this bit will automatically turn on the Target ACKOEN field following a Start Condition." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 1. "ACKOVAL,I2C Target ACK Override Value" "0: An ACK is sent indicating valid data or command.,1: A NACK is sent indicating invalid data or command." newline bitfld.long 0x4 0. "ACKOEN,I2C Target ACK Override Enable" "0: A response in not provided.,1: An ACK or NACK is sent according to the value.." line.long 0x8 "I2C0_TFIFOCTL,I2C Target FIFO Control" bitfld.long 0x8 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 8.--10. "RXTRIG,RX FIFO Trigger" "?,?,?,?,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x8 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 0.--2. "TXTRIG,TX FIFO Trigger" "?,?,?,?,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x20++0x3 line.long 0x0 "I2C0_TFIFOSR,I2C Target FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFOFlush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x24++0x3 line.long 0x0 "I2C0_TARGET_PECCTL,I2C Target PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC transmission and check is disabled,1: PEC transmission and check is enabled" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO." rgroup.long 0x28++0x3 line.long 0x0 "I2C0_TARGET_PECSR,I2C Target PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates PEC was checked in the transaction.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,This is the current PEC Byte Count of the Target State Machine." tree.end tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPM0L222*")) tree "I2C1" base ad:0x400F2000 tree "I2C1_GPRCM[%s]" base ad:0x400F2800 group.long 0x0++0x3 line.long 0x0 "I2C1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "I2C1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "I2C1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "I2C1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400F2000 newline group.long 0x1000++0x7 newline line.long 0x0 "I2C1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "I2C1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "I2C1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "I2C1_CPU_INT[%s]" base ad:0x400F3020 rgroup.long 0x0++0x3 line.long 0x0 "I2C1_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Clear Set Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 26. "TDMA_DONE_RX,Target DMA Done on Event Channel RX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 25. "TDMA_DONE_TX,Target DMA Done on Event Channel TX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 21. "TTXEMPTY,Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an Target RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Interrupt did not occur,1: Interrupt Occured" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt ocuured" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear interrupt,1: Set interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear interrupt,1: Set interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Clear Interrupt,1: Set interrupt" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Clear interrupt,1: Set Interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Interrupt occured" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt Occured" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "I2C1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Clear interrupt mask,1: Set interrupt mask" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 23. "TSTOP,Target STOP Detection Interrupt" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 22. "TSTART,Target START Detection Interrupt" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Interrupt occured" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "I2C1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Set interrupt" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "I2C1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Clear interrupt" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 23. "TSTOP,Target STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 22. "TSTART,Target START Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Clear Interrupt" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "I2C1_DMA_TRIG0[%s]" base ad:0x400F3080 rgroup.long 0x0++0x3 line.long 0x0 "I2C1_DMA_TRIG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C1_DMA_TRIG0_IMASK,Interrupt mask" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C1_DMA_TRIG0_RIS,Raw interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C1_DMA_TRIG0_MIS,Masked interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C1_DMA_TRIG0_ISET,Interrupt set" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C1_DMA_TRIG0_ICLR,Interrupt clear" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end tree "I2C1_DMA_TRIG1[%s]" base ad:0x400F3050 rgroup.long 0x0++0x3 line.long 0x0 "I2C1_DMA_TRIG1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C1_DMA_TRIG1_IMASK,Interrupt mask" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C1_DMA_TRIG1_RIS,Raw interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C1_DMA_TRIG1_MIS,Masked interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C1_DMA_TRIG1_ISET,Interrupt set" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C1_DMA_TRIG1_ICLR,Interrupt clear" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end base ad:0x400F2000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "I2C1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "I2C1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." rgroup.long 0x10FC++0x3 line.long 0x0 "I2C1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1200++0x7 line.long 0x0 "I2C1_GFCTL,I2C Glitch Filter Control" bitfld.long 0x0 11. "CHAIN,Analog and digital noise filters chaining enable." "0: When 0 chaining is disabled and only digital..,1: When 1 analog and digital glitch filters are.." bitfld.long 0x0 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0x0 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" bitfld.long 0x0 0.--2. "DGFSEL,Glitch Suppression Pulse Width" "0: Bypass,1: 1 clock,2: 2 clocks,3: 3 clocks,4: 4 clocks,5: 8 clocks,6: 16 clocks,7: 31 clocks" line.long 0x4 "I2C1_TIMEOUT_CTL,I2C Timeout Count Control Register" bitfld.long 0x4 31. "TCNTBEN,Timeout Counter B Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 16.--23. 1. "TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h." newline bitfld.long 0x4 15. "TCNTAEN,Timeout Counter A Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 0.--7. 1. "TCNTLA,Timeout counter A load value" rgroup.long 0x1208++0x3 line.long 0x0 "I2C1_TIMEOUT_CNT,I2C Timeout Count Register" hexmask.long.byte 0x0 16.--23. 1. "TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B" hexmask.long.byte 0x0 0.--7. 1. "TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A" tree "I2C1_CONTROLLER[%s]" base ad:0x400F3210 group.long 0x0++0x7 line.long 0x0 "I2C1_CSA,I2C Controller Target Address Register" bitfld.long 0x0 15. "CMODE,This bit selects the adressing mode to be used in Controller mode" "0: 7-bit addressing mode,1: 10-bit addressing mode" newline hexmask.long.word 0x0 1.--10. 1. "TADDR,I2C Target Address This field specifies bits A9 through A0 of the Target address." newline bitfld.long 0x0 0. "DIR,Receive/Send" "0: The Controller is in transmit mode.,1: The Controller is in receive mode." line.long 0x4 "I2C1_CCTR,I2C Controller Control Register" hexmask.long.word 0x4 16.--27. 1. "CBLEN,I2C transaction length" newline bitfld.long 0x4 5. "RD_ON_TXEMPTY,Read on TX Empty" "0: No special behavior,1: When 1 the Controller will transmit all bytes.." newline bitfld.long 0x4 4. "CACKOEN,Controller ACK overrride Enable" "0: No special behavior,1: When 1 and the Controller is receiving data and.." newline bitfld.long 0x4 3. "ACK,Data Acknowledge Enable." "0: The last received data byte of a transaction is..,1: The last received data byte of a transaction is.." newline bitfld.long 0x4 2. "STOP,Generate STOP" "0: The controller does not generate the STOP..,1: The controller generates the STOP condition." newline bitfld.long 0x4 1. "START,Generate START" "0: The controller does not generate the START..,1: The controller generates the START or repeated.." newline bitfld.long 0x4 0. "BURSTRUN,I2C Controller Enable" "0: In standard mode this encoding means the..,1: The Controller is able to transmit or receive.." rgroup.long 0x8++0x7 line.long 0x0 "I2C1_CSR,I2C Controller Status Register" hexmask.long.word 0x0 16.--27. 1. "CBCNT,I2C Controller Transaction Count" newline bitfld.long 0x0 6. "BUSBSY,I2C Bus is Busy" "0: The I2C bus is idle.,1: 'This Status bit is set on a START or when SCL.." newline bitfld.long 0x0 5. "IDLE,I2C Idle" "0: The I2C controller is not idle.,1: The I2C controller is idle." newline bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0: The I2C controller won arbitration.,1: The I2C controller lost arbitration." newline bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0: The transmitted data was acknowledged,1: The transmitted data was not acknowledged." newline bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0: The transmitted address was acknowledged,1: The transmitted address was not acknowledged." newline bitfld.long 0x0 1. "ERR,Error" "0: No error was detected on the last operation.,1: An error occurred on the last operation." newline bitfld.long 0x0 0. "BUSY,I2C Controller FSM Busy" "0: The controller is idle.,1: The controller is busy." line.long 0x4 "I2C1_CRXDATA,I2C Controller RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x10++0xB line.long 0x0 "I2C1_CTXDATA,I2C Controller TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C1_CTPR,I2C Controller Timer Period" hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period" line.long 0x8 "I2C1_CCR,I2C Controller Configuration" bitfld.long 0x8 8. "LPBK,I2C Loopback" "0: Normal operation.,1: The controller in a test mode loopback.." newline bitfld.long 0x8 2. "CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: Disables the clock stretching detection. This..,1: Enables the clock stretching detection. Enabling.." newline bitfld.long 0x8 1. "MCTL,MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: Disable MultiController mode.,1: Enable MultiController mode." newline bitfld.long 0x8 0. "ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: Disables the I2C Controller operation.,1: Enables the I2C Controller operation." rgroup.long 0x24++0x3 line.long 0x0 "I2C1_CBMON,I2C Controller Bus Monitor" bitfld.long 0x0 1. "SDA,I2C SDA Status" "0: The I2CSDA signal is low.,1: The I2CSDA signal is high. Note: During and.." newline bitfld.long 0x0 0. "SCL,I2C SCL Status" "0: The I2CSCL signal is low.,1: The I2CSCL signal is high. Note: During and.." group.long 0x28++0x3 line.long 0x0 "I2C1_CFIFOCTL,I2C Controller FIFO Control" bitfld.long 0x0 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 8.--10. "RXTRIG,RX FIFO Trigger" "0: Trigger when RX FIFO contains >= 1 byte,1: Trigger when RX FIFO contains >= 2 byte,2: Trigger when RX FIFO contains >= 3 byte,3: Trigger when RX FIFO contains >= 4 byte,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x0 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0: Trigger when the TX FIFO is empty.,1: Trigger when TX FIFO contains 1 byte,2: Trigger when TX FIFO contains 2 byte,3: Trigger when TX FIFO contains 3 byte,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x2C++0x3 line.long 0x0 "I2C1_CFIFOSR,I2C Controller FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x30++0x3 line.long 0x0 "I2C1_CONTROLLER_I2CPECCTL,I2C Controller PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC is disabled in Controller mode,1: PEC is enabled in Controller mode" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,PEC Count" rgroup.long 0x34++0x3 line.long 0x0 "I2C1_CONTROLLER_PECSR,I2C Controller PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates if a PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates if the PEC was checked in the.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,PEC Byte Count" tree.end tree "I2C1_TARGET[%s]" base ad:0x400F3250 group.long 0x0++0xB line.long 0x0 "I2C1_TOAR,I2C Target Own Address" bitfld.long 0x0 15. "TMODE,This bit selects the adressing mode to be used in Target mode." "0: Enable 7-bit addressing,1: Enable 10-bit addressing" newline bitfld.long 0x0 14. "OAREN,I2C Target Own Address Enable" "0: Disable OAR address,1: Enable OAR address" newline hexmask.long.word 0x0 0.--9. 1. "OAR,I2C Target Own Address: This field specifies bits A9 through A0 of the Target address." line.long 0x4 "I2C1_TOAR2,I2C Target Own Address 2" hexmask.long.byte 0x4 16.--22. 1. "OAR2_MASK,I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address." newline bitfld.long 0x4 7. "OAR2EN,I2C Target Own Address 2 Enable" "0: The alternate address is disabled.,1: Enables the use of the alternate address in the.." newline hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Target Own Address 2" line.long 0x8 "I2C1_TCTR,I2C Target Control Register" bitfld.long 0x8 10. "TWUEN,Target Wakeup Enable" "0: When 0 the Target is not allowed to clock..,1: When 1 the Target is allowed to clock stretch on.." newline bitfld.long 0x8 9. "EN_DEFDEVADR,Enable Deault device address" "0: When this bit is 0 the default device address is..,1: When this bit is 1 default device address of.." newline bitfld.long 0x8 8. "EN_ALRESPADR,Enable Alert Response Address" "0: When this bit is 0 the alert response address is..,1: When this bit is 1 alert response address of.." newline bitfld.long 0x8 7. "EN_DEFHOSTADR,Enable Default Host Address" "0: When this bit is 0 the default host address is..,1: When this bit is 1 default host address of.." newline bitfld.long 0x8 6. "RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: When 0 RIS:TRXFULL will be set when only the..,1: When 1 RIS:TRXFULL will be set when the Target.." newline bitfld.long 0x8 5. "TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: When 0 the TX FIFO empty signal to the Target..,1: When 1 the TX FIFO empty signal to the Target.." newline bitfld.long 0x8 4. "TXTRIG_TXMODE,Tx Trigger when Target FSM is in Tx Mode" "0: No special behavior,1: When 1 RIS:TXFIFOTRG will be set when the Target.." newline bitfld.long 0x8 3. "TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: When 0 RIS:TTXEMPTY will be set when only the..,1: When 1 RIS:TTXEMPTY will be set when the Target.." newline bitfld.long 0x8 2. "TCLKSTRETCH,Target Clock Stretch Enable" "0: Target clock stretching is disabled,1: Target clock stretching is enabled" newline bitfld.long 0x8 1. "GENCALL,General call response enable" "0: Do not respond to a general call,1: Respond to a general call" newline bitfld.long 0x8 0. "ACTIVE,Device Active. Setting this bit enables the Target functionality." "0: Disables the I2C Target operation.,1: Enables the I2C Target operation." rgroup.long 0xC++0x7 line.long 0x0 "I2C1_TSR,I2C Target Status Register" hexmask.long.word 0x0 9.--18. 1. "ADDRMATCH,Indicates the address for which Target address match happened" newline bitfld.long 0x0 8. "STALE_TXFIFO,Stale Tx FIFO" "0: Tx FIFO is not stale,1: The TX FIFO is stale. This occurs when the TX.." newline bitfld.long 0x0 7. "TXMODE,Target FSM is in TX MODE" "0: The Target State Machine is not in TX_DATA..,1: The Target State Machine is in TX_DATA TX_WAIT.." newline bitfld.long 0x0 6. "BUSBSY,I2C bus is busy" "0: The I2C Bus is not busy,1: The I2C Bus is busy. This is cleared on a timeout." newline rbitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read" newline rbitfld.long 0x0 4. "QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.." newline rbitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0: Either the OAR2 address is not matched or the..,1: OAR2 address matched and ACKed by the Target." newline bitfld.long 0x0 2. "RXMODE,Target FSM is in Rx MODE" "0: The Target State Machine is not in the RX_DATA..,1: The Target State Machine is in the RX_DATA.." newline rbitfld.long 0x0 1. "TREQ,Transmit Request" "0: No outstanding transmit request.,1: The I2C controller has been addressed as a.." newline rbitfld.long 0x0 0. "RREQ,Receive Request" "0: No outstanding receive data.,1: The I2C controller has outstanding receive data.." line.long 0x4 "I2C1_TRXDATA,I2C Target RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x14++0xB line.long 0x0 "I2C1_TTXDATA,I2C Target TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C1_TACKCTL,I2C Target ACK Control" bitfld.long 0x4 4. "ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 3. "ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 2. "ACKOEN_ON_START,When set this bit will automatically turn on the Target ACKOEN field following a Start Condition." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 1. "ACKOVAL,I2C Target ACK Override Value" "0: An ACK is sent indicating valid data or command.,1: A NACK is sent indicating invalid data or command." newline bitfld.long 0x4 0. "ACKOEN,I2C Target ACK Override Enable" "0: A response in not provided.,1: An ACK or NACK is sent according to the value.." line.long 0x8 "I2C1_TFIFOCTL,I2C Target FIFO Control" bitfld.long 0x8 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 8.--10. "RXTRIG,RX FIFO Trigger" "?,?,?,?,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x8 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 0.--2. "TXTRIG,TX FIFO Trigger" "?,?,?,?,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x20++0x3 line.long 0x0 "I2C1_TFIFOSR,I2C Target FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFOFlush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x24++0x3 line.long 0x0 "I2C1_TARGET_PECCTL,I2C Target PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC transmission and check is disabled,1: PEC transmission and check is enabled" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO." rgroup.long 0x28++0x3 line.long 0x0 "I2C1_TARGET_PECSR,I2C Target PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates PEC was checked in the transaction.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,This is the current PEC Byte Count of the Target State Machine." tree.end tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "I2C2" base ad:0x400F4000 tree "I2C2_GPRCM[%s]" base ad:0x400F4800 group.long 0x0++0x3 line.long 0x0 "I2C2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "I2C2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "I2C2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "I2C2_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x400F4000 newline group.long 0x1000++0x7 newline line.long 0x0 "I2C2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "I2C2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "I2C2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "I2C2_CPU_INT[%s]" base ad:0x400F5020 rgroup.long 0x0++0x3 line.long 0x0 "I2C2_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C2_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 31. "INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Clear Set Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 26. "TDMA_DONE_RX,Target DMA Done on Event Channel RX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 25. "TDMA_DONE_TX,Target DMA Done on Event Channel TX" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 21. "TTXEMPTY,Target Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an Target RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Transaction completed Interrupt" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C2_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Interrupt did not occur,1: Interrupt Occured" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt ocuured" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear interrupt,1: Set interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear interrupt,1: Set interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Clear Interrupt,1: Set interrupt" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Clear interrupt,1: Set Interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Interrupt occured" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Interrupt did not occur,1: Interrupt Occured" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "I2C2_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Clear interrupt mask,1: Set interrupt mask" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 23. "TSTOP,Target STOP Detection Interrupt" "0: Clear MIS,1: Set MIS" newline bitfld.long 0x0 22. "TSTART,Target START Detection Interrupt" "0: Clear MIS,1: Set MIS" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Interrupt occured" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 14. "TIMEOUTA,Timeout A Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Clear interrupt mask,1: Set interrupt mask" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Interrupt occured" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "I2C2_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Set interrupt" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 23. "TSTOP,Stop Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 22. "TSTART,Start Condition Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Set Interrupt" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "I2C2_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 31. "INTR_OVFL,Interrupt overflow" "0: No effect,1: Clear interrupt" bitfld.long 0x0 30. "TARBLOST,Target Arbitration Lost" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 29. "TRX_OVFL,Target RX FIFO overflow" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 28. "TTX_UNFL,Target TX FIFO underflow" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 27. "TPEC_RX_ERR,Target RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 26. "TDMA_DONE_RX,DMA Done on Event Channel RX" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 25. "TDMA_DONE_TX,DMA Done on Event Channel TX" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 24. "TGENCALL,General Call Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 23. "TSTOP,Target STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 22. "TSTART,Target START Detection Interrupt" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 21. "TTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 20. "TRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: Clear Interrupt Mask,1: Clear Interrupt" newline bitfld.long 0x0 19. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 18. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 17. "TTXDONE,Target Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 16. "TRXDONE,Target Receive Data Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 15. "TIMEOUTB,Timeout B Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 14. "TIMEOUTA,Timeout A interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 13. "CPEC_RX_ERR,Controller RX Pec Error Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "CDMA_DONE_RX,DMA Done on Event Channel RX" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 11. "CDMA_DONE_TX,DMA Done on Event Channel TX" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 10. "CARBLOST,Arbitration Lost Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "CSTOP,STOP Detection Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 8. "CSTART,START Detection Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "CNACK,Address/Data NACK Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "CTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "CRXFIFOFULL,RXFIFO full event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 3. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 2. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Clear Interrupt" bitfld.long 0x0 1. "CTXDONE,Controller Transmit Transaction completed Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 0. "CRXDONE,Controller Receive Data Interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "I2C2_DMA_TRIG0[%s]" base ad:0x400F5080 rgroup.long 0x0++0x3 line.long 0x0 "I2C2_DMA_TRIG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C2_DMA_TRIG0_IMASK,Interrupt mask" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C2_DMA_TRIG0_RIS,Raw interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C2_DMA_TRIG0_MIS,Masked interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C2_DMA_TRIG0_ISET,Interrupt set" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C2_DMA_TRIG0_ICLR,Interrupt clear" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end tree "I2C2_DMA_TRIG1[%s]" base ad:0x400F5050 rgroup.long 0x0++0x3 line.long 0x0 "I2C2_DMA_TRIG1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "I2C2_DMA_TRIG1_IMASK,Interrupt mask" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "I2C2_DMA_TRIG1_RIS,Raw interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "I2C2_DMA_TRIG1_MIS,Masked interrupt status" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "I2C2_DMA_TRIG1_ISET,Interrupt set" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "I2C2_DMA_TRIG1_ICLR,Interrupt clear" bitfld.long 0x0 3. "TTXFIFOTRG,Target Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "TRXFIFOTRG,Target Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "CTXFIFOTRG,Controller Transmit FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "CRXFIFOTRG,Controller Receive FIFO Trigger" "0: Clear Interrupt Mask,1: Set Interrupt Mask" tree.end base ad:0x400F4000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "I2C2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "I2C2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." rgroup.long 0x10FC++0x3 line.long 0x0 "I2C2_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1200++0x7 line.long 0x0 "I2C2_GFCTL,I2C Glitch Filter Control" bitfld.long 0x0 11. "CHAIN,Analog and digital noise filters chaining enable." "0: When 0 chaining is disabled and only digital..,1: When 1 analog and digital glitch filters are.." bitfld.long 0x0 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0x0 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" bitfld.long 0x0 0.--2. "DGFSEL,Glitch Suppression Pulse Width" "0: Bypass,1: 1 clock,2: 2 clocks,3: 3 clocks,4: 4 clocks,5: 8 clocks,6: 16 clocks,7: 31 clocks" line.long 0x4 "I2C2_TIMEOUT_CTL,I2C Timeout Count Control Register" bitfld.long 0x4 31. "TCNTBEN,Timeout Counter B Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 16.--23. 1. "TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h." newline bitfld.long 0x4 15. "TCNTAEN,Timeout Counter A Enable" "0: Disable Timeout Counter B,1: Enable Timeout Counter B" hexmask.long.byte 0x4 0.--7. 1. "TCNTLA,Timeout counter A load value" rgroup.long 0x1208++0x3 line.long 0x0 "I2C2_TIMEOUT_CNT,I2C Timeout Count Register" hexmask.long.byte 0x0 16.--23. 1. "TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B" hexmask.long.byte 0x0 0.--7. 1. "TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A" tree "I2C2_CONTROLLER[%s]" base ad:0x400F5210 group.long 0x0++0x7 line.long 0x0 "I2C2_CSA,I2C Controller Target Address Register" bitfld.long 0x0 15. "CMODE,This bit selects the adressing mode to be used in Controller mode" "0: 7-bit addressing mode,1: 10-bit addressing mode" newline hexmask.long.word 0x0 1.--10. 1. "TADDR,I2C Target Address This field specifies bits A9 through A0 of the Target address." newline bitfld.long 0x0 0. "DIR,Receive/Send" "0: The Controller is in transmit mode.,1: The Controller is in receive mode." line.long 0x4 "I2C2_CCTR,I2C Controller Control Register" hexmask.long.word 0x4 16.--27. 1. "CBLEN,I2C transaction length" newline bitfld.long 0x4 5. "RD_ON_TXEMPTY,Read on TX Empty" "0: No special behavior,1: When 1 the Controller will transmit all bytes.." newline bitfld.long 0x4 4. "CACKOEN,Controller ACK overrride Enable" "0: No special behavior,1: When 1 and the Controller is receiving data and.." newline bitfld.long 0x4 3. "ACK,Data Acknowledge Enable." "0: The last received data byte of a transaction is..,1: The last received data byte of a transaction is.." newline bitfld.long 0x4 2. "STOP,Generate STOP" "0: The controller does not generate the STOP..,1: The controller generates the STOP condition." newline bitfld.long 0x4 1. "START,Generate START" "0: The controller does not generate the START..,1: The controller generates the START or repeated.." newline bitfld.long 0x4 0. "BURSTRUN,I2C Controller Enable" "0: In standard mode this encoding means the..,1: The Controller is able to transmit or receive.." rgroup.long 0x8++0x7 line.long 0x0 "I2C2_CSR,I2C Controller Status Register" hexmask.long.word 0x0 16.--27. 1. "CBCNT,I2C Controller Transaction Count" newline bitfld.long 0x0 6. "BUSBSY,I2C Bus is Busy" "0: The I2C bus is idle.,1: 'This Status bit is set on a START or when SCL.." newline bitfld.long 0x0 5. "IDLE,I2C Idle" "0: The I2C controller is not idle.,1: The I2C controller is idle." newline bitfld.long 0x0 4. "ARBLST,Arbitration Lost" "0: The I2C controller won arbitration.,1: The I2C controller lost arbitration." newline bitfld.long 0x0 3. "DATACK,Acknowledge Data" "0: The transmitted data was acknowledged,1: The transmitted data was not acknowledged." newline bitfld.long 0x0 2. "ADRACK,Acknowledge Address" "0: The transmitted address was acknowledged,1: The transmitted address was not acknowledged." newline bitfld.long 0x0 1. "ERR,Error" "0: No error was detected on the last operation.,1: An error occurred on the last operation." newline bitfld.long 0x0 0. "BUSY,I2C Controller FSM Busy" "0: The controller is idle.,1: The controller is busy." line.long 0x4 "I2C2_CRXDATA,I2C Controller RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x10++0xB line.long 0x0 "I2C2_CTXDATA,I2C Controller TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C2_CTPR,I2C Controller Timer Period" hexmask.long.byte 0x4 0.--6. 1. "TPR,Timer Period" line.long 0x8 "I2C2_CCR,I2C Controller Configuration" bitfld.long 0x8 8. "LPBK,I2C Loopback" "0: Normal operation.,1: The controller in a test mode loopback.." newline bitfld.long 0x8 2. "CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: Disables the clock stretching detection. This..,1: Enables the clock stretching detection. Enabling.." newline bitfld.long 0x8 1. "MCTL,MultiController mode. In MultiController mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: Disable MultiController mode.,1: Enable MultiController mode." newline bitfld.long 0x8 0. "ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: Disables the I2C Controller operation.,1: Enables the I2C Controller operation." rgroup.long 0x24++0x3 line.long 0x0 "I2C2_CBMON,I2C Controller Bus Monitor" bitfld.long 0x0 1. "SDA,I2C SDA Status" "0: The I2CSDA signal is low.,1: The I2CSDA signal is high. Note: During and.." newline bitfld.long 0x0 0. "SCL,I2C SCL Status" "0: The I2CSCL signal is low.,1: The I2CSCL signal is high. Note: During and.." group.long 0x28++0x3 line.long 0x0 "I2C2_CFIFOCTL,I2C Controller FIFO Control" bitfld.long 0x0 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 8.--10. "RXTRIG,RX FIFO Trigger" "0: Trigger when RX FIFO contains >= 1 byte,1: Trigger when RX FIFO contains >= 2 byte,2: Trigger when RX FIFO contains >= 3 byte,3: Trigger when RX FIFO contains >= 4 byte,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x0 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x0 0.--2. "TXTRIG,TX FIFO Trigger" "0: Trigger when the TX FIFO is empty.,1: Trigger when TX FIFO contains 1 byte,2: Trigger when TX FIFO contains 2 byte,3: Trigger when TX FIFO contains 3 byte,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x2C++0x3 line.long 0x0 "I2C2_CFIFOSR,I2C Controller FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x30++0x3 line.long 0x0 "I2C2_CONTROLLER_I2CPECCTL,I2C Controller PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC is disabled in Controller mode,1: PEC is enabled in Controller mode" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,PEC Count" rgroup.long 0x34++0x3 line.long 0x0 "I2C2_CONTROLLER_PECSR,I2C Controller PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates if a PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates if the PEC was checked in the.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,PEC Byte Count" tree.end tree "I2C2_TARGET[%s]" base ad:0x400F5250 group.long 0x0++0xB line.long 0x0 "I2C2_TOAR,I2C Target Own Address" bitfld.long 0x0 15. "TMODE,This bit selects the adressing mode to be used in Target mode." "0: Enable 7-bit addressing,1: Enable 10-bit addressing" newline bitfld.long 0x0 14. "OAREN,I2C Target Own Address Enable" "0: Disable OAR address,1: Enable OAR address" newline hexmask.long.word 0x0 0.--9. 1. "OAR,I2C Target Own Address: This field specifies bits A9 through A0 of the Target address." line.long 0x4 "I2C2_TOAR2,I2C Target Own Address 2" hexmask.long.byte 0x4 16.--22. 1. "OAR2_MASK,I2C Target Own Address 2 Mask: This field specifies bits A6 through A0 of the Target address." newline bitfld.long 0x4 7. "OAR2EN,I2C Target Own Address 2 Enable" "0: The alternate address is disabled.,1: Enables the use of the alternate address in the.." newline hexmask.long.byte 0x4 0.--6. 1. "OAR2,I2C Target Own Address 2" line.long 0x8 "I2C2_TCTR,I2C Target Control Register" bitfld.long 0x8 10. "TWUEN,Target Wakeup Enable" "0: When 0 the Target is not allowed to clock..,1: When 1 the Target is allowed to clock stretch on.." newline bitfld.long 0x8 9. "EN_DEFDEVADR,Enable Deault device address" "0: When this bit is 0 the default device address is..,1: When this bit is 1 default device address of.." newline bitfld.long 0x8 8. "EN_ALRESPADR,Enable Alert Response Address" "0: When this bit is 0 the alert response address is..,1: When this bit is 1 alert response address of.." newline bitfld.long 0x8 7. "EN_DEFHOSTADR,Enable Default Host Address" "0: When this bit is 0 the default host address is..,1: When this bit is 1 default host address of.." newline bitfld.long 0x8 6. "RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: When 0 RIS:TRXFULL will be set when only the..,1: When 1 RIS:TRXFULL will be set when the Target.." newline bitfld.long 0x8 5. "TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: When 0 the TX FIFO empty signal to the Target..,1: When 1 the TX FIFO empty signal to the Target.." newline bitfld.long 0x8 4. "TXTRIG_TXMODE,Tx Trigger when Target FSM is in Tx Mode" "0: No special behavior,1: When 1 RIS:TXFIFOTRG will be set when the Target.." newline bitfld.long 0x8 3. "TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: When 0 RIS:TTXEMPTY will be set when only the..,1: When 1 RIS:TTXEMPTY will be set when the Target.." newline bitfld.long 0x8 2. "TCLKSTRETCH,Target Clock Stretch Enable" "0: Target clock stretching is disabled,1: Target clock stretching is enabled" newline bitfld.long 0x8 1. "GENCALL,General call response enable" "0: Do not respond to a general call,1: Respond to a general call" newline bitfld.long 0x8 0. "ACTIVE,Device Active. Setting this bit enables the Target functionality." "0: Disables the I2C Target operation.,1: Enables the I2C Target operation." rgroup.long 0xC++0x7 line.long 0x0 "I2C2_TSR,I2C Target Status Register" hexmask.long.word 0x0 9.--18. 1. "ADDRMATCH,Indicates the address for which Target address match happened" newline bitfld.long 0x0 8. "STALE_TXFIFO,Stale Tx FIFO" "0: Tx FIFO is not stale,1: The TX FIFO is stale. This occurs when the TX.." newline bitfld.long 0x0 7. "TXMODE,Target FSM is in TX MODE" "0: The Target State Machine is not in TX_DATA..,1: The Target State Machine is in TX_DATA TX_WAIT.." newline bitfld.long 0x0 6. "BUSBSY,I2C bus is busy" "0: The I2C Bus is not busy,1: The I2C Bus is busy. This is cleared on a timeout." newline rbitfld.long 0x0 5. "QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read" newline rbitfld.long 0x0 4. "QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.." newline rbitfld.long 0x0 3. "OAR2SEL,OAR2 Address Matched" "0: Either the OAR2 address is not matched or the..,1: OAR2 address matched and ACKed by the Target." newline bitfld.long 0x0 2. "RXMODE,Target FSM is in Rx MODE" "0: The Target State Machine is not in the RX_DATA..,1: The Target State Machine is in the RX_DATA.." newline rbitfld.long 0x0 1. "TREQ,Transmit Request" "0: No outstanding transmit request.,1: The I2C controller has been addressed as a.." newline rbitfld.long 0x0 0. "RREQ,Receive Request" "0: No outstanding receive data.,1: The I2C controller has outstanding receive data.." line.long 0x4 "I2C2_TRXDATA,I2C Target RXData" hexmask.long.byte 0x4 0.--7. 1. "VALUE,Received Data." group.long 0x14++0xB line.long 0x0 "I2C2_TTXDATA,I2C Target TXData" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Transmit Data" line.long 0x4 "I2C2_TACKCTL,I2C Target ACK Control" bitfld.long 0x4 4. "ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the received PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 3. "ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Target ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 2. "ACKOEN_ON_START,When set this bit will automatically turn on the Target ACKOEN field following a Start Condition." "0: No special behavior,1: When set this bit will automatically turn on the.." newline bitfld.long 0x4 1. "ACKOVAL,I2C Target ACK Override Value" "0: An ACK is sent indicating valid data or command.,1: A NACK is sent indicating invalid data or command." newline bitfld.long 0x4 0. "ACKOEN,I2C Target ACK Override Enable" "0: A response in not provided.,1: An ACK or NACK is sent according to the value.." line.long 0x8 "I2C2_TFIFOCTL,I2C Target FIFO Control" bitfld.long 0x8 15. "RXFLUSH,RX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 8.--10. "RXTRIG,RX FIFO Trigger" "?,?,?,?,4: Trigger when RX FIFO contains >= 5 byte,5: Trigger when RX FIFO contains >= 6 byte,6: Trigger when RX FIFO contains >= 7 byte,7: Trigger when RX FIFO contains >= 8 byte" newline bitfld.long 0x8 7. "TXFLUSH,TX FIFO Flush" "0: Do not Flush FIFO,1: Flush FIFO" newline bitfld.long 0x8 0.--2. "TXTRIG,TX FIFO Trigger" "?,?,?,?,4: Trigger when TX FIFO contains 4 byte,5: Trigger when TX FIFO contains 5 byte,6: Trigger when TX FIFO contains 6 byte,7: Trigger when TX FIFO contains 7 byte" rgroup.long 0x20++0x3 line.long 0x0 "I2C2_TFIFOSR,I2C Target FIFO Status Register" bitfld.long 0x0 15. "TXFLUSH,TX FIFO Flush" "0: FIFO Flush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 8.--11. 1. "TXFIFOCNT,Number of Bytes which could be put into the TX FIFO" newline bitfld.long 0x0 7. "RXFLUSH,RX FIFO Flush" "0: FIFOFlush not active,1: FIFO Flush active" newline hexmask.long.byte 0x0 0.--3. 1. "RXFIFOCNT,Number of Bytes which could be read from the RX FIFO" group.long 0x24++0x3 line.long 0x0 "I2C2_TARGET_PECCTL,I2C Target PEC control register" bitfld.long 0x0 12. "PECEN,PEC Enable" "0: PEC transmission and check is disabled,1: PEC transmission and check is enabled" newline hexmask.long.word 0x0 0.--8. 1. "PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO." rgroup.long 0x28++0x3 line.long 0x0 "I2C2_TARGET_PECSR,I2C Target PEC status register" bitfld.long 0x0 17. "PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC check error did not occurr in the..,1: Indicates PEC check error occurred in the.." newline bitfld.long 0x0 16. "PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: Indicates PEC was not checked in the transaction..,1: Indicates PEC was checked in the transaction.." newline hexmask.long.word 0x0 0.--8. 1. "PECBYTECNT,This is the current PEC Byte Count of the Target State Machine." tree.end tree.end endif tree.end tree "IOMUX (I/O Multiplexer)" base ad:0x40428000 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 61. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hysteresis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,Peripheral Function selection bits" repeat.end tree "IOMUX_LMGMT_DFT_ATRT[%s]" base ad:0x40429900 group.long 0x0++0x3 line.long 0x0 "IOMUX_DTBENA,DTB ENA Register" hexmask.long 0x0 0.--31. 1. "ENABLE,DTB Enable" group.long 0xC++0x3 line.long 0x0 "IOMUX_DTBBUSSEL,DTBBUSSEL Register" hexmask.long 0x0 0.--31. 1. "SEL,DTB bus selector" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "IOMUX_DTBOUTSEL[$1],DTBOUSEL Register" bitfld.long 0x0 7. "PRAIL,PRAIL bit to identify the Power Rail of the selected IP." "0: Selected IP is SVT,1: Selected IP is ULL" hexmask.long.byte 0x0 0.--6. 1. "OUTIPSEL,Select bits to configure the output IP for the selected DTB Lane." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x90)++0x3 line.long 0x0 "IOMUX_DTBDIR[$1],DTBDIR Register" hexmask.long.byte 0x0 0.--5. 1. "DIR,DTB lane direction bit 0: DTB OUTPUT enable 1: DTB INPUT enable" repeat.end group.long 0xB0++0xF line.long 0x0 "IOMUX_IOTBEN0,IOTB ENA Register0" hexmask.long 0x0 0.--31. 1. "SIG32,IOTB Enable Bit for SIG1-32" line.long 0x4 "IOMUX_IOTBEN1,IOTB ENA Register1" hexmask.long 0x4 0.--31. 1. "SIG64,IOTB Enable Bit for SIG33-64" line.long 0x8 "IOMUX_IOTBEN2,IOTB ENA Register2" hexmask.long 0x8 0.--31. 1. "SIG96,IOTB Enable Bit for SIG65-96" line.long 0xC "IOMUX_IOTBEN3,IOTB ENA Register3" hexmask.long 0xC 0.--31. 1. "SIG128,IOTB Enable Bit for SIG97-128" tree.end endif sif (cpuis("MSPM0G110*")) repeat 251. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0G150*")) repeat 251. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0G151*")) repeat 251. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hysteresis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,Peripheral Function selection bits" repeat.end endif sif (cpuis("MSPM0G310*")) repeat 251. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0G350*")) repeat 251. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0G351*")) repeat 251. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hysteresis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,Peripheral Function selection bits" repeat.end endif sif (cpuis("MSPM0L110*")) repeat 61. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0L111*")) repeat 47. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0L122*")) repeat 75. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0L130*")) repeat 61. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0L134*")) repeat 61. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif sif (cpuis("MSPM0L222*")) repeat 75. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "IOMUX_PINCM[$1],Pin Control Management Register in SECCFG region" bitfld.long 0x0 28. "WCOMP,Wakeup Compare Value bit" "0: Wakeup on a match of 0,1: Wakeup on a match of 1" bitfld.long 0x0 27. "WUEN,Wakeup Enable bit" "0: wakeup is disabled.,1: wakeup is enabled" newline bitfld.long 0x0 26. "INV,Data inversion selection" "0: Data inversion is disabled.,1: Data inversion is enabled" bitfld.long 0x0 25. "HIZ1,High output value will tri-state the output when this bit is enabled" "0: open-drain is disabled.,1: open-drain is enabled." newline bitfld.long 0x0 20. "DRV,Drive strength control selection for HS IOCELL only" "0: Drive setting of 0 selected,1: Drive setting of 1 selected" bitfld.long 0x0 19. "HYSTEN,Hystersis Enable Control Selection" "0: hysteresis is disabled.,1: hysteresis is enabled" newline bitfld.long 0x0 18. "INENA,Input Enable Control Selection" "0: Input enable is disabled.,1: Input enable is enabled." bitfld.long 0x0 17. "PIPU,Pull Up control selection" "0: Pull up is disabled.,1: Pull up is enabled" newline bitfld.long 0x0 16. "PIPD,Pull Down control selection" "0: Pull down is disabled.,1: Pull down is enabled" rbitfld.long 0x0 13. "WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: wakeup source is NOT from this IOCELL,1: wakeup source is from this IOCELL" newline bitfld.long 0x0 7. "PC,Peripheral is Connected" "0: The output of the peripheral (and its output..,1: The output latch of the dataflow will be.." hexmask.long.byte 0x0 0.--5. 1. "PF,P channel Function selection bits" repeat.end endif tree.end sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "KEYSTORECTL (Keystore Controller)" base ad:0x400AC000 group.long 0x1100++0xB line.long 0x0 "KEYSTORECTL_CFG,Keystore configuration" hexmask.long.byte 0x0 0.--3. 1. "NK256,Number of 256 bit keys to be held in the key-store." line.long 0x4 "KEYSTORECTL_KEYWR,Key write configuration" hexmask.long.byte 0x4 4.--7. 1. "KEYSLOTSEL,Select the key slot to write the key into." bitfld.long 0x4 0.--2. "KEYSZSEL,Key size selection. Selection of 128 or 256 bit keys" "0: 256 bit key,1: 128 bit key,?,?,?,?,?,?" line.long 0x8 "KEYSTORECTL_KEYRD,Key read configuration" bitfld.long 0x8 8.--9. "CRYPTOSEL,Crypto engine selector" "0: Transfer key to AES,?,?,?" hexmask.long.byte 0x8 4.--7. 1. "KEYSLOTSEL,Select the key slot to read the key from." bitfld.long 0x8 0.--2. "KEYSZSEL,Key size selection. Selection of 128 or 256 bit keys" "0: 256 bit key,1: 128 bit key,?,?,?,?,?,?" rgroup.long 0x110C++0x3 line.long 0x0 "KEYSTORECTL_STATUS,Status" rbitfld.long 0x0 16.--17. "NKEYSLOTS,Size of keystorage: Number of 128-bit key slots" "0: Two slots,1: Three slots,2: Four slots,?" hexmask.long.byte 0x0 4.--11. 1. "VALID,Bitvector of valid bits to indicate which slots have been configured" hexmask.long.byte 0x0 0.--3. 1. "STAT,Status information" wgroup.long 0x1110++0x3 line.long 0x0 "KEYSTORECTL_KEYIN,Input key" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")) group.long 0x1114++0x3 line.long 0x0 "KEYSTORECTL_KEYLOCK,Keylock" hexmask.long.byte 0x0 0.--7. 1. "LOCKBIT,Bitvector of lock bits to lock certain slots from being used by application." endif tree.end endif sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "LCD (LCD Driver)" base ad:0x40070000 group.long 0x800++0x3 line.long 0x0 "LCD_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x804++0x3 line.long 0x0 "LCD_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x814++0x3 line.long 0x0 "LCD_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree "LCD_INT_EVENT0[%s]" base ad:0x40071020 rgroup.long 0x0++0x3 line.long 0x0 "LCD_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,LCD Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "LCD_IMASK,Interrupt mask" bitfld.long 0x0 2. "BLKON,Blinkking segments on." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "BLKOFF,Blinking segments off." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "FRMSTART,Start of new LCD frame." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LCD_RIS,Raw interrupt status" bitfld.long 0x0 2. "BLKON,Blinking segments turned on." "0: Interrupt flag cleared,1: Interrupt flag set" bitfld.long 0x0 1. "BLKOFF,Blinking segments turned off interrupt flag." "0: Interrupt flag cleared,1: Interrupt flag set" bitfld.long 0x0 0. "FRMSTART,Set in start of a new frame." "0: Interrupt flag cleared,1: Interrupt flag set" rgroup.long 0x18++0x3 line.long 0x0 "LCD_MIS,Masked interrupt status" bitfld.long 0x0 2. "BLKON,Masked BLKON interrupt flag" "0: Masked interrupt flag cleared,1: Masked interrupt flag set" bitfld.long 0x0 1. "BLKOFF,Masked BLKOFF interrupt flag" "0: Masked interrupt flag cleared,1: Masked interrupt flag set" bitfld.long 0x0 0. "FRMSTART,Master FRMSTART interrupt flag" "0: Interrupt flag cleared,1: Interrupt flag set" wgroup.long 0x20++0x3 line.long 0x0 "LCD_ISET,Interrupt set" bitfld.long 0x0 2. "BLKON,Set BLKON RIS flag" "0: Writing 0 has no effect,1: Set corresponding RIS flag" bitfld.long 0x0 1. "BLKOFF,Set BLKOFF RIS flag" "0: Writing 0 has no effect,1: Set corresponding RIS flag" bitfld.long 0x0 0. "FRMSTART,Set FRMSTART RIS flag." "0: Writing 0 has no effect,1: Set corresponding RIS flag" wgroup.long 0x28++0x3 line.long 0x0 "LCD_ICLR,Interrupt clear" bitfld.long 0x0 2. "BLKON,Clear BLKON RIS flag" "0: Writing 0 has no effect,1: Clear corresponding RIS flag" bitfld.long 0x0 1. "BLKOFF,Clear BLKOFF RIS flag" "0: Writing 0 has no effect,1: Clear corresponding RIS flag" bitfld.long 0x0 0. "FRMSTART,Clear FRMSTART RIS flag" "0: Writing 0 has no effect,1: Clear corresponding RIS flag" tree.end base ad:0x40070000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "LCD_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" group.long 0x1100++0x3 line.long 0x0 "LCD_LCDCTL0,LCD control register 0" bitfld.long 0x0 24. "LCDSYNCEXT" "0: External eynchronization off.,1: External synchronization on." hexmask.long.byte 0x0 11.--15. 1. "LCDDIVx,LCD frequency divider. Together with LCDMXx the LCD frequency fLCD is calculated as fLCD = fSOURCE / ((LCDDIVx + 1) * Value[LCDMXx]). Change only while LCDON = 0. 00000b = Divide by 1 00001b = Divide by 2 . 11110b = Divide by 31 11111b =.." newline bitfld.long 0x0 3.--5. "LCDMXx,LCD mux rate. These bits select the LCD mode. Change only while LCDON = 0. 000b = Static 001b = 2-mux 010b = 3-mux 011b = 4-mux 100b = 5-mux 101b = 6-mux 110b = 7-mux 111b = 8-mux" "0: Static,1: 2-mux,2: 3-mux,3: 4-mux,4: 5-mux,5: 6-mux,6: 7-mux,7: 8-mux" bitfld.long 0x0 2. "LCDSON,LCD segments on. This bit supports flashing LCD applications by turning off all segment lines while leaving the LCD timing generator and R33 enabled. 0b = All LCD segments are off. 1b = All LCD segments are enabled and on or off according to.." "0: All LCD segments are off.,1: All LCD segments are enabled and on or off.." newline bitfld.long 0x0 1. "LCDLP,LCD low-power waveform. This bit is only applicable for 1/3 bias mode that is for LCDBIASSEL = 0. 0b = Standard LCD waveforms on segment and common lines selected. 1b = Low-power LCD waveforms on segment and common lines selected." "0: Standard LCD waveforms,1: Low power LCD waveforms" bitfld.long 0x0 0. "LCDON,LCD on. This bit turns the LCD module on or off. 0b = LCD module off 1b = LCD module on" "0: LCD module off,1: LCD module on" group.long 0x1108++0x1B line.long 0x0 "LCD_LCDBLKCTL,LCD blicking control register" bitfld.long 0x0 2.--4. "LCDBLKPREx,Clock prescaler for blinking frequency." "0: Divide by 2,1: Divide by 4,2: Divide by 8,3: Divide by 16,4: Divide by 32,5: Divide by 64,6: Divide by 128,7: Divide by 256" bitfld.long 0x0 0.--1. "LCDBLKMODx,Blinking mode 00b = Blinking disabled. 01b = Blinking of individual segments as enabled in blinking memory register LCDBMx. In mux mode >5 blinking is disabled. 10b = Blinking of all segments 11b = Switching between display contents as.." "0: Blinking disabled.,1: Blinking of individual segments as enabled in..,2: Blinking of all segments,3: Switching between display contents as stored in.." line.long 0x4 "LCD_LCDMEMCTL,LCD memory control LCD memory control register" bitfld.long 0x4 2. "LCDCLRBM,Clear LCD blinking memory Clears all blinking memory registers LCDBMx. The bit is automatically reset when the blinking memory is cleared. Setting this bit in 5-mux mode and above has no effect. It is immediately reset again. 0b = Contents of.." "0: Contents of blinking memory registers LCDBMx..,1: Clear content of all blinking memory registers.." bitfld.long 0x4 1. "LCDCLRM,Clear LCD memory Clears all LCD memory registers LCDMx. The bit is automatically reset when the LCD memory is cleared. 0b = Contents of LCD memory registers LCDMx remain unchanged 1b = Clear content of all LCD memory registers LCDMx" "0: Contents of LCD memory registers LCDMx remain..,1: Clear content of all LCD memory registers LCDMx" newline bitfld.long 0x4 0. "LCDDISP,Select LCD memory registers for display When LCDBLKMODx = 00 LCDDISP can be set by software. The bit is cleared in LCDBLKMODx = 01 and LCDBLKMODx = 10 or if a mux mode =5 is selected and cannot be changed by software. When LCDBLKMODx = 11 .." "0: Display content of LCD memory registers LCDMx,1: Display content of LCD blinking memory registers.." line.long 0x8 "LCD_LCDVCTL,LCD voltage control register" bitfld.long 0x8 24. "LCDVBSTEN,Enables the voltage boost circuitry which provides a boosted VDDA voltage. This boosted voltage is to be used in the switch controls when the VDDA supply is less than 1.6V." "0: Disable.,1: Enable." hexmask.long.byte 0x8 12.--15. 1. "LCDCPFSELx,Charge pump frequency selection. 0000b = 32.768 kHz / 1 / 8 = 4.096 kHz 0001b = 32.768 kHz / 2 / 8 = 2.048 kHz 0010b = 32.768 kHz / 3 / 8 = 1.365 kHz 0011b = 32.768 kHz / 4 / 8 = 1.024 kHz 0100b = 32.768 kHz / 5 / 8 = 819 Hz 0101b = 32.768.." newline hexmask.long.byte 0x8 8.--11. 1. "VLCDx,Internal reference voltage select on R13." bitfld.long 0x8 7. "LCDCPEN,Charge pump enable 0b = Charge pump disabled(1) 1b = Charge pump enabled when VLCD is generated internally (VLCDEXT = 0) and VLCDx > 0 or VLCDREFx > 0." "0: Charge pump disabled(1),1: Charge pump enabled when VLCD is generated.." newline bitfld.long 0x8 6. "LCDREFEN,Internal reference voltage enable on R13 0b = Internal reference voltage disabled 1b = Internal reference voltage enabled" "0: Internal reference voltage disabled,1: Internal reference voltage enabled" bitfld.long 0x8 5. "LCDSELVDD,Selects if R33 is supplied either from AVDD internally or from charge pump 0b = R33 connected to external supply 1b = R33 internally connected to AVDD" "0: R33 connected to external supply,1: R33 internally connected to AVDD" newline bitfld.long 0x8 4. "LCD_HP_LP,High-power or Low-power LCD. This bit is only effective when the internal bias voltage resistor divider is used that is when LCDINTBIASEN = 1. It selects the resistor ladder that is used to generate the bias voltages for the LCD. 0b =.." "0: Low-power LCD is used,1: Higher-power LCD is used" bitfld.long 0x8 3. "VLCDSEL_VDD_R33,Selects if the LCD bias voltage V1 is sourced from the R33 pin or from the internal supply voltage AVDD This bit is only effective when the internal bias voltage resistor divider is used that is when LCDINTBIASEN = 1 0b = V1 is sourced.." "0: V1 is sourced from R33,1: V1 is sourced internally from AVDD" newline bitfld.long 0x8 2. "LCDINTBIASEN,Enables the internal bias voltage resistor divider. The actual voltage source used for the resistor divider is selected by the VLCDSEL_VDD_R33 bit configuration. 0b = Internal bias voltage resistor divider is disabled 1b = Internal bias.." "0: Internal bias voltage resistor divider is disabled,1: Internal bias voltage resistor divider is enabled" bitfld.long 0x8 1. "LCDBIASSEL,Bias select. LCDBIASSEL is ignored in static mode as well as for 2-mux 3-mux and 4-mux LCD modes. For 5-mux to 8-mux modes: 0b = 1/3 bias 1b = 1/4 bias" "0: 1/3 bias,1: 1/4 bias" newline bitfld.long 0x8 0. "LCDREFMODE,Selects whether R13 voltage is switched or in static mode 0b = Static mode 1b = Switched mode" "0: Static mode,1: Switched mode" line.long 0xC "LCD_LCDPCTL0,LCD port control register 0" bitfld.long 0xC 15. "LCDS15,LCD pin 15 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 14. "LCDS14,LCD pin 14 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 13. "LCDS13,LCD pin 13 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 12. "LCDS12,LCD pin 12 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 11. "LCDS11,LCD pin 11 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 10. "LCDS10,LCD pin 10 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 9. "LCDS9,LCD pin 9 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 8. "LCDS8,LCD pin 8 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 7. "LCDS7,LCD pin 7 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 6. "LCDS6,LCD pin 6 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 5. "LCDS5,LCD pin 5 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 4. "LCDS4,LCD pin 4 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 3. "LCDS3,LCD pin 3 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 2. "LCDS2,LCD pin 2 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0xC 1. "LCDS1,LCD pin 1 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0xC 0. "LCDS0,LCD pin 0 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." line.long 0x10 "LCD_LCDPCTL1,LCD port control register 1" bitfld.long 0x10 15. "LCDS31,LCD pin 31 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 14. "LCDS30,LCD pin 30 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 13. "LCDS29,LCD pin 29 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 12. "LCDS28,LCD pin 28 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 11. "LCDS27,LCD pin 27 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 10. "LCDS26,LCD pin 26 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 9. "LCDS25,LCD pin 25 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 8. "LCDS24,LCD pin 24 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 7. "LCDS23,LCD segment line 23 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 6. "LCDS22,LCD segment line 22 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 5. "LCDS21,LCD segment line 21 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 4. "LCDS20,LCD segment line 20 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 3. "LCDS19,LCD segment line 19 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 2. "LCDS18,LCD segment line 18 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x10 1. "LCDS17,LCD segment line 17 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x10 0. "LCDS16,LCD segment line 16 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." line.long 0x14 "LCD_LCDPCTL2,LCD port control register 2" bitfld.long 0x14 15. "LCDS47,LCD pin 47 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 14. "LCDS46,LCD pin 46 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 13. "LCDS45,LCD pin 45 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 12. "LCDS44,LCD pin 44 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 11. "LCDS43,LCD pin 43 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 10. "LCDS42,LCD pin 42 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 9. "LCDS41,LCD pin 41 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 8. "LCDS40,LCD pin 40 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 7. "LCDS39,LCD pin 39 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 6. "LCDS38,LCD pin 38 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 5. "LCDS37,LCD pin 37 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 4. "LCDS36,LCD pin 36 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 3. "LCDS35,LCD pin 35 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 2. "LCDS34,LCD pin 34 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x14 1. "LCDS33,LCD pin 33 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x14 0. "LCDS32,LCD pin 32 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." line.long 0x18 "LCD_LCDPCTL3,LCD port control register 3" bitfld.long 0x18 15. "LCDS63,LCD pin 63 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 14. "LCDS62,LCD pin 62 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 13. "LCDS61,LCD pin 61 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 12. "LCDS60,LCD pin 60 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 11. "LCDS59,LCD pin 59 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 10. "LCDS58,LCD pin 58 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 9. "LCDS57,LCD pin 57 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 8. "LCDS56,LCD pin 56 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 7. "LCDS55,LCD pin 55 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 6. "LCDS54,LCD pin 54 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 5. "LCDS53,LCD pin 53 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 4. "LCDS52,LCD pin 52 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 3. "LCDS51,LCD pin 51 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 2. "LCDS50,LCD pin 50 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." newline bitfld.long 0x18 1. "LCDS49,LCD pin 49 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." bitfld.long 0x18 0. "LCDS48,LCD pin 48 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: Multiplexed pins are port functions.,1: Pins are LCD functions." group.long 0x1128++0xF line.long 0x0 "LCD_LCDCSSEL0,LCD common segment select register 0" bitfld.long 0x0 15. "LCDCSS15,Selects pin L15 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 14. "LCDCSS14,Selects pin L14 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 13. "LCDCSS13,Selects pin L13 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 12. "LCDCSS12,Selects pin L12 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 11. "LCDCSS11,Selects pin L11 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 10. "LCDCSS10,Selects pin L10 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 9. "LCDCSS9,Selects pin L9 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 8. "LCDCSS8,Selects pin L8 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 7. "LCDCSS7,Selects pin L7 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 6. "LCDCSS6,Selects pin L6 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 5. "LCDCSS5,Selects pin L5 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 4. "LCDCSS4,Selects pin L4 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 3. "LCDCSS3,Selects pin L3 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 2. "LCDCSS2,Selects pin L2 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x0 1. "LCDCSS1,Selects pin L1 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x0 0. "LCDCSS0,Selects pin L0 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" line.long 0x4 "LCD_LCDCSSEL1,LCD common segment select register 1" bitfld.long 0x4 15. "LCDCSS31,Selects pin L31 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 14. "LCDCSS30,Selects pin L30 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 13. "LCDCSS29,Selects pin L29 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 12. "LCDCSS28,Selects pin L28 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 11. "LCDCSS27,Selects pin L27 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 10. "LCDCSS26,Selects pin L26 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 9. "LCDCSS25,Selects pin L25 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 8. "LCDCSS24,Selects pin L24 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 7. "LCDCSS23,Selects pin L23 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 6. "LCDCSS22,Selects pin L22 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 5. "LCDCSS21,Selects pin L21 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 4. "LCDCSS20,Selects pin L20 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 3. "LCDCSS19,Selects pin L19 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 2. "LCDCSS18,Selects pin L18 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x4 1. "LCDCSS17,Selects pin L17 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x4 0. "LCDCSS16,Selects pin L16 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" line.long 0x8 "LCD_LCDCSSEL2,LCD common segment select register 2" bitfld.long 0x8 15. "LCDCSS47,Selects pin L47 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 14. "LCDCSS46,Selects pin L46 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 13. "LCDCSS45,Selects pin L45 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 12. "LCDCSS44,Selects pin L44 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 11. "LCDCSS43,Selects pin L43 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 10. "LCDCSS42,Selects pin L42 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 9. "LCDCSS41,Selects pin L41 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 8. "LCDCSS40,Selects pin L40 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 7. "LCDCSS39,Selects pin L39 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 6. "LCDCSS38,Selects pin L38 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 5. "LCDCSS37,Selects pin L37 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 4. "LCDCSS36,Selects pin L36 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 3. "LCDCSS35,Selects pin L35 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 2. "LCDCSS34,Selects pin L34 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0x8 1. "LCDCSS33,Selects pin L33 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0x8 0. "LCDCSS32,Selects pin L32 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" line.long 0xC "LCD_LCDCSSEL3,LCD common segment select register 3" bitfld.long 0xC 15. "LCDCSS63,Selects pin L63 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 14. "LCDCSS62,Selects pin L62 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 13. "LCDCSS61,Selects pin L61 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 12. "LCDCSS60,Selects pin L60 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 11. "LCDCSS59,Selects pin L59 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 10. "LCDCSS58,Selects pin L58 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 9. "LCDCSS57,Selects pin L57 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 8. "LCDCSS56,Selects pin L56 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 7. "LCDCSS55,Selects pin L55 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 6. "LCDCSS54,Selects pin L54 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 5. "LCDCSS53,Selects pin L53 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 4. "LCDCSS52,Selects pin L52 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 3. "LCDCSS51,Selects pin L51 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 2. "LCDCSS50,Selects pin L50 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" newline bitfld.long 0xC 1. "LCDCSS49,Selects pin L49 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" bitfld.long 0xC 0. "LCDCSS48,Selects pin L48 as either common or segment line. 0b = Segment line 1b = Common line" "0: Segment line,1: Common line" repeat 64. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x1140)++0x0 line.byte 0x0 "LCD_LCDM[$1],LCD memory index register" bitfld.byte 0x0 7. "MBIT7,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line (LCDCSS[2*index+1] = 1b): 0b = Pin.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 6. "MBIT6,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line (LCDCSS[2*index+1] =.." "0,1" newline bitfld.byte 0x0 5. "MBIT5,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 4. "MBIT4,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000 <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: LCD segment/common off,1: LCD segment/common on" newline bitfld.byte 0x0 3. "MBIT3,If LCD pin L(index) is selected as segment line (LCDCSS(index) = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b): 0b = Pin L[2*index] not.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 2. "MBIT2,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b): 0b.." "0: LCD segment/common off,1: LCD segment/common on" newline bitfld.byte 0x0 1. "MBIT1,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b):.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 0. "MBIT0,If LCD L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000b <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] =.." "0: LCD segment/common off,1: LCD segment/common on" repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x1180)++0x0 line.byte 0x0 "LCD_LCDBM[$1],LCD blinking memory index register" bitfld.byte 0x0 7. "MBIT7,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line (LCDCSS[2*index+1] = 1b): 0b = Pin.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 6. "MBIT6,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line (LCDCSS[2*index+1] =.." "0: LCD segment/common off,1: LCD segment/common on" newline bitfld.byte 0x0 5. "MBIT5,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 4. "MBIT4,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000b <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: LCD segment/common off,1: LCD segment/common on" newline bitfld.byte 0x0 3. "MBIT3,If LCD pin L(index) is selected as segment line (LCDCSS(index) = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b): 0b = Pin L[2*index] not.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 2. "MBIT2,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b): 0b.." "0: LCD segment/common off,1: LCD segment/common on" newline bitfld.byte 0x0 1. "MBIT1,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b):.." "0: LCD segment/common off,1: LCD segment/common on" bitfld.byte 0x0 0. "MBIT0,If LCD L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000b <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] =.." "0: LCD segment/common off,1: LCD segment/common on" repeat.end tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "LFSS (Low Frequency Subsystem)" base ad:0x40094000 group.long 0x444++0x3 line.long 0x0 "LFSS_FPUB_0,Publisher Port 0" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x0 0.--7. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x0 0.--7. 1. "CHANID,0 = disconnected." endif rgroup.long 0x1004++0x3 line.long 0x0 "LFSS_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: LFCLK is disabled,1: LFCLK is enabled" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")) tree "LFSS_CPU_INT[%s]" base ad:0x40095020 rgroup.long 0x0++0x3 line.long 0x0 "LFSS_CPU_INT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "LFSS_CPU_INT_IMASK,Interrupt mask" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LFSS_CPU_INT_RIS,Raw interrupt status" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur,1: Interrupt occurred" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "LFSS_CPU_INT_MIS,Masked interrupt status" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "LFSS_CPU_INT_ISET,Interrupt set" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Set interrupt" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "LFSS_CPU_INT_ICLR,Interrupt clear" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Clear interrupt" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Clear interrupt" tree.end newline group.long 0x400++0x3 newline line.long 0x0 "LFSS_FSUB_0,Subsciber Port 0" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." endif endif sif (cpuis("MSPM0L122*")) tree "LFSS_CPU_INT[%s]" base ad:0x40095020 rgroup.long 0x0++0x3 line.long 0x0 "LFSS_CPU_INT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "LFSS_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LFSS_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "LFSS_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "LFSS_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "LFSS_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0L222*")) tree "LFSS_CPU_INT[%s]" base ad:0x40095020 rgroup.long 0x0++0x3 line.long 0x0 "LFSS_CPU_INT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "LFSS_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LFSS_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "LFSS_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "LFSS_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "LFSS_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")) tree "LFSS_GEN_EVENT[%s]" base ad:0x40095050 rgroup.long 0x0++0x3 line.long 0x0 "LFSS_GEN_EVENT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "LFSS_GEN_EVENT_IMASK,Interrupt mask" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LFSS_GEN_EVENT_RIS,Raw interrupt status" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur,1: Interrupt occurred" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "LFSS_GEN_EVENT_MIS,Masked interrupt status" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "LFSS_GEN_EVENT_ISET,Interrupt set" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Set interrupt" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "LFSS_GEN_EVENT_ICLR,Interrupt clear" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Clear interrupt" endif bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif rgroup.long 0x10E0++0x3 line.long 0x0 "LFSS_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode 1 select" "?,?,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode 0 select" "?,1: The interrupt or event line is in software mode.,?,?" rgroup.long 0x10FC++0x3 line.long 0x0 "LFSS_DESC,LFSS Descriptor Register" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identifier. This ID is unique for each module. 0x2911 = Module ID of the LFSS Module" hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences." newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instantiated version. Describes which instance of the module accessed." hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet)" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet)" group.long 0x1100++0xB line.long 0x0 "LFSS_CLKCTL,RTC Clock Control Register" bitfld.long 0x0 31. "MODCLKEN,This bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module." "0: 32kHz clock is not supplied to the RTC.,1: 32kHz clock is supplied to the RTC." line.long 0x4 "LFSS_DBGCTL,RTC Module Debug Control Register" bitfld.long 0x4 1. "DBGINT,Debug Interrupt Enable." "0: Interrupts of the module will not be captured..,1: Interrupts are enabled in debug mode. Interrupt.." bitfld.long 0x4 0. "DBGRUN,Debug Run." "0: Counter is halted if CPU is in debug state.,1: Continue to operate normally ignoring the debug.." line.long 0x8 "LFSS_CTL,RTC Control Register" bitfld.long 0x8 7. "RTCBCD,Real-time clock BCD select. Selects BCD counting for real-time clock." "0: Binary code selected,1: Binary coded decimal (BCD) code selected" bitfld.long 0x8 0.--1. "RTCTEVTX,Real-time clock time event 0x0 = Minute changed 0x1 = Hour changed 0x2 = Every day at midnight (00:00) 0x3 = Every day at noon (12:00)" "0: 00,1: Hour changed,2: Every day at midnight,3: Every day at noon" rgroup.long 0x110C++0x3 line.long 0x0 "LFSS_STA,RTC Status Register" bitfld.long 0x0 2. "RTCTCOK,Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not." "0: Write to RTCTCMPx is unsuccessful,1: Write to RTCTCMPx is successful" bitfld.long 0x0 1. "RTCTCRDY,Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset." "0: RTC temperature compensation in transition,1: RTC temperature compensation ready" newline bitfld.long 0x0 0. "RTCRDY,Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading." "0: RTC time values in transition,1: RTC time values safe for reading." group.long 0x1110++0x3F line.long 0x0 "LFSS_CAL,RTC Clock Offset Calibration Register" bitfld.long 0x0 16.--17. "RTCCALFX,Real-time clock calibration frequency. Selects frequency output to RTCCLK pin for calibration measurement. The corresponding port must be configured for the peripheral module function." "0: 32 kHz,1: 512 Hz,2: 256 Hz,3: 1 Hz" bitfld.long 0x0 15. "RTCOCALS,Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration." "0: Down calibration. Frequency adjusted down.,1: Up calibration. Frequency adjusted up." newline hexmask.long.byte 0x0 0.--7. 1. "RTCOCALX,Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be.." line.long 0x4 "LFSS_TCMP,RTC Temperature Compensation Register" bitfld.long 0x4 15. "RTCTCMPS,Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation." "0: Down calibration. Frequency adjusted down.,1: Up calibration. Frequency adjusted up." hexmask.long.byte 0x4 0.--7. 1. "RTCTCMPX,Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum effective.." line.long 0x8 "LFSS_SEC,RTC Seconds Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x8 12.--14. "SECHIGHBCD,Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "SECLOWBCD,Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x8 0.--5. 1. "SECBIN,Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0xC "LFSS_MIN,RTC Minutes Register - Calendar Mode With Binary / BCD Format" bitfld.long 0xC 12.--14. "MINHIGHBCD,Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "MINLOWBCD,Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0xC 0.--5. 1. "MINBIN,Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x10 "LFSS_HOUR,RTC Hours Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x10 12.--13. "HOURHIGHBCD,Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "HOURLOWBCD,Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x10 0.--4. 1. "HOURBIN,Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x14 "LFSS_DAY,RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x14 20.--21. "DOMHIGHBCD,Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" hexmask.long.byte 0x14 16.--19. 1. "DOMLOWBCD,Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x14 8.--12. 1. "DOMBIN,Day of month Binary (1 to 28 29 30 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0x14 0.--2. "DOW,Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x18 "LFSS_MON,RTC Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x18 12. "MONHIGHBCD,Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1" hexmask.long.byte 0x18 8.--11. 1. "MONLOWBCD,Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x18 0.--3. 1. "MONBIN,Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x1C "LFSS_YEAR,RTC Year Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x1C 28.--30. "CENTHIGHBCD,Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--27. 1. "CENTLOWBCD,Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x1C 20.--23. 1. "DECADEBCD,Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." hexmask.long.byte 0x1C 16.--19. 1. "YEARLOWESTBCD,Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x1C 8.--11. 1. "YEARHIGHBIN,Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0." hexmask.long.byte 0x1C 0.--7. 1. "YEARLOWBIN,Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x20 "LFSS_A1MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x20 15. "AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x20 12.--14. "AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 8.--11. 1. "AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x20 7. "AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x20 0.--5. 1. "AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x24 "LFSS_A1HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x24 15. "AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x24 12.--13. "AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3" newline hexmask.long.byte 0x24 8.--11. 1. "AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x24 7. "AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x24 0.--4. 1. "AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x28 "LFSS_A1DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x28 23. "ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x28 20.--21. "ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x28 15. "ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x28 8.--12. 1. "ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0x28 7. "ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: No alarm,1: Alarm enabled" newline bitfld.long 0x28 0.--2. "ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x2C "LFSS_A2MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x2C 15. "AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x2C 12.--14. "AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 8.--11. 1. "AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x2C 7. "AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x2C 0.--5. 1. "AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x30 "LFSS_A2HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x30 15. "AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x30 12.--13. "AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3" newline hexmask.long.byte 0x30 8.--11. 1. "AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x30 7. "AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x30 0.--4. 1. "AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x34 "LFSS_A2DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x34 23. "ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x34 20.--21. "ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" newline hexmask.long.byte 0x34 16.--19. 1. "ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x34 15. "ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x34 8.--12. 1. "ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0x34 7. "ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: No alarm,1: Alarm enabled" newline bitfld.long 0x34 0.--2. "ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x38 "LFSS_PSCTL,RTC Prescale Timer 0/1 Control Register" bitfld.long 0x38 18.--20. "RT1IP,Prescale timer 1 interrupt interval" "0: Interval every 15.6 milisecond,1: Interval every 31.3 milisecond,2: Interval every 62.5 milisecond,3: Interval every 125 milisecond,4: Interval every 250 milisecond,5: Interval every 500 milisecond,6: Interval every 1 second,7: Interval every 2 second" bitfld.long 0x38 2.--4. "RT0IP,Prescale timer 0 interrupt interval" "?,?,2: Interval every 244 microsecond,3: Interval every 488 microsecond,4: Interval every 0.98 milisecond,5: Interval every 1.95 milisecond,6: Interval every 3.91 milisecond,7: Interval every 7.81 milisecond" line.long 0x3C "LFSS_EXTPSCTL,RTC Prescale Timer 2 Control Register" bitfld.long 0x3C 2.--3. "RT2PS,Prescale timer 2 interrupt interval" "0: Interval every 4 second,1: Interval every 8 second,2: Interval every 16 second,?" rgroup.long 0x1150++0x1B line.long 0x0 "LFSS_TSSEC,Time Stamp Seconds Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x0 12.--14. "SECHIGHBCD,Time Stamp Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "SECLOWBCD,Time Stamp Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x0 0.--5. 1. "SECBIN,Time Stamp Second Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x4 "LFSS_TSMIN,Time Stamp Minutes Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x4 12.--14. "MINHIGHBCD,Time Stamp Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "MINLOWBCD,Time Stamp Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x4 0.--5. 1. "MINBIN,Time Stamp Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x8 "LFSS_TSHOUR,Time Stamp Hours Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x8 12.--13. "HOURHIGHBCD,Time Stamp Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "HOURLOWBCD,Time Stamp Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x8 0.--4. 1. "HOURBIN,Time Stamp Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0xC "LFSS_TSDAY,Time Stamp Day Of Week / MonthRegister - Calendar Mode With Binary / BCD Format" bitfld.long 0xC 20.--21. "DOMHIGHBCD,Time Stamp Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" hexmask.long.byte 0xC 16.--19. 1. "DOMLOWBCD,Time Stamp Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0xC 8.--12. 1. "DOMBIN,Time Stamp Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0xC 0.--2. "DOW,Time Stamp Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x10 "LFSS_TSMON,Time Stamp Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x10 12. "MONHIGHBCD,Time Stamp Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1" hexmask.long.byte 0x10 8.--11. 1. "MONLOWBCD,Time Stamp Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x10 0.--3. 1. "MONBIN,Time Stamp Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x14 "LFSS_TSYEAR,Time Stamp Years Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x14 28.--30. "CENTHIGHBCD,Time Stamp Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 24.--27. 1. "CENTLOWBCD,Time Stamp Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x14 20.--23. 1. "DECADEBCD,Time Stamp Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." hexmask.long.byte 0x14 16.--19. 1. "YERARLOWESTBCD,Time Stamp Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x14 8.--11. 1. "YEARHIGHBIN,Time Stamp Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0." hexmask.long.byte 0x14 0.--7. 1. "YEARLOWBIN,Time Stamp Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x18 "LFSS_TSSTAT,Time Stamp Status Register" rbitfld.long 0x18 16. "TSVDDEVT,Loss of VDD caused time stamp event" "0: no event detected,1: event detected" newline sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) rbitfld.long 0x18 15. "TSTIOEVT15,Tamper I/O 15 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 14. "TSTIOEVT14,Tamper I/O 14 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 13. "TSTIOEVT13,Tamper I/O 13 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 12. "TSTIOEVT12,Tamper I/O 12 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 11. "TSTIOEVT11,Tamper I/O 11 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 10. "TSTIOEVT10,Tamper I/O 10 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 9. "TSTIOEVT9,Tamper I/O 9 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 8. "TSTIOEVT8,Tamper I/O 8 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 7. "TSTIOEVT7,Tamper I/O 7 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 6. "TSTIOEVT6,Tamper I/O 6 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 5. "TSTIOEVT5,Tamper I/O 5 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 4. "TSTIOEVT4,Tamper I/O 4 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 3. "TSTIOEVT3,Tamper I/O 3 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 2. "TSTIOEVT2,Tamper I/O 2 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 1. "TSTIOEVT1,Tamper I/O 1 caused time stamp event" "0: no event detected,1: event detected" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x18 15. "TSTIOEVT15,Tamper I/O 15 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 14. "TSTIOEVT14,Tamper I/O 14 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 13. "TSTIOEVT13,Tamper I/O 13 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 12. "TSTIOEVT12,Tamper I/O 12 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 11. "TSTIOEVT11,Tamper I/O 11 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 10. "TSTIOEVT10,Tamper I/O 10 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 9. "TSTIOEVT9,Tamper I/O 9 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 8. "TSTIOEVT8,Tamper I/O 8 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 7. "TSTIOEVT7,Tamper I/O 7 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 6. "TSTIOEVT6,Tamper I/O 6 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 5. "TSTIOEVT5,Tamper I/O 5 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 4. "TSTIOEVT4,Tamper I/O 4 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 3. "TSTIOEVT3,Tamper I/O 3 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 2. "TSTIOEVT2,Tamper I/O 2 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 1. "TSTIOEVT1,Tamper I/O 1 caused time stamp event" "0: no event detected,1: event detected" endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x18 15. "TSTIOEVT15,Tamper I/O 15 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 14. "TSTIOEVT14,Tamper I/O 14 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 13. "TSTIOEVT13,Tamper I/O 13 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 12. "TSTIOEVT12,Tamper I/O 12 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 11. "TSTIOEVT11,Tamper I/O 11 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 10. "TSTIOEVT10,Tamper I/O 10 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 9. "TSTIOEVT9,Tamper I/O 9 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 8. "TSTIOEVT8,Tamper I/O 8 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 7. "TSTIOEVT7,Tamper I/O 7 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 6. "TSTIOEVT6,Tamper I/O 6 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 5. "TSTIOEVT5,Tamper I/O 5 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 4. "TSTIOEVT4,Tamper I/O 4 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 3. "TSTIOEVT3,Tamper I/O 3 caused time stamp event" "0: no event detected,1: event detected" newline rbitfld.long 0x18 2. "TSTIOEVT2,Tamper I/O 2 caused time stamp event" "0: no event detected,1: event detected" rbitfld.long 0x18 1. "TSTIOEVT1,Tamper I/O 1 caused time stamp event" "0: no event detected,1: event detected" newline endif rbitfld.long 0x18 0. "TSTIOEVT0,Tamper I/O 0 caused time stamp event" "0: no event detected,1: event detected" group.long 0x116C++0x3 line.long 0x0 "LFSS_TSCTL,Time Stamp Control Register" bitfld.long 0x0 20. "TSCAPTURE,Defines the capture method of the RTC timestamp when a time stamp event occurens." "0: Time stamp holds RTC capture at first occurrence..,1: Time stamp holds RTC capture at last occurrence.." bitfld.long 0x0 16. "TSVDDEN,Time Stamp by VDD Loss detection enable" "0: function disabled,1: function enabled" newline sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 15. "TSTIOEN15,Time Stamp by Tamper I/O 15 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 14. "TSTIOEN14,Time Stamp by Tamper I/O 14 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 13. "TSTIOEN13,Time Stamp by Tamper I/O 13 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 12. "TSTIOEN12,Time Stamp by Tamper I/O 12 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 11. "TSTIOEN11,Time Stamp by Tamper I/O 11 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 10. "TSTIOEN10,Time Stamp by Tamper I/O 10 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 9. "TSTIOEN9,Time Stamp by Tamper I/O 9 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 8. "TSTIOEN8,Time Stamp by Tamper I/O 8 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 7. "TSTIOEN7,Time Stamp by Tamper I/O 7 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 6. "TSTIOEN6,Time Stamp by Tamper I/O 6 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 5. "TSTIOEN5,Time Stamp by Tamper I/O 5 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 4. "TSTIOEN4,Time Stamp by Tamper I/O 4 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 3. "TSTIOEN3,Time Stamp by Tamper I/O 3 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 2. "TSTIOEN2,Time Stamp by Tamper I/O 2 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 1. "TSTIOEN1,Time Stamp by Tamper I/O 1 enable" "0: function disabled,1: function enabled" endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 15. "TSTIOEN15,Time Stamp by Tamper I/O 15 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 14. "TSTIOEN14,Time Stamp by Tamper I/O 14 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 13. "TSTIOEN13,Time Stamp by Tamper I/O 13 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 12. "TSTIOEN12,Time Stamp by Tamper I/O 12 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 11. "TSTIOEN11,Time Stamp by Tamper I/O 11 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 10. "TSTIOEN10,Time Stamp by Tamper I/O 10 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 9. "TSTIOEN9,Time Stamp by Tamper I/O 9 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 8. "TSTIOEN8,Time Stamp by Tamper I/O 8 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 7. "TSTIOEN7,Time Stamp by Tamper I/O 7 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 6. "TSTIOEN6,Time Stamp by Tamper I/O 6 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 5. "TSTIOEN5,Time Stamp by Tamper I/O 5 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 4. "TSTIOEN4,Time Stamp by Tamper I/O 4 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 3. "TSTIOEN3,Time Stamp by Tamper I/O 3 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 2. "TSTIOEN2,Time Stamp by Tamper I/O 2 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 1. "TSTIOEN1,Time Stamp by Tamper I/O 1 enable" "0: function disabled,1: function enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 15. "TSTIOEN15,Time Stamp by Tamper I/O 15 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 14. "TSTIOEN14,Time Stamp by Tamper I/O 14 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 13. "TSTIOEN13,Time Stamp by Tamper I/O 13 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 12. "TSTIOEN12,Time Stamp by Tamper I/O 12 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 11. "TSTIOEN11,Time Stamp by Tamper I/O 11 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 10. "TSTIOEN10,Time Stamp by Tamper I/O 10 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 9. "TSTIOEN9,Time Stamp by Tamper I/O 9 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 8. "TSTIOEN8,Time Stamp by Tamper I/O 8 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 7. "TSTIOEN7,Time Stamp by Tamper I/O 7 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 6. "TSTIOEN6,Time Stamp by Tamper I/O 6 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 5. "TSTIOEN5,Time Stamp by Tamper I/O 5 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 4. "TSTIOEN4,Time Stamp by Tamper I/O 4 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 3. "TSTIOEN3,Time Stamp by Tamper I/O 3 enable" "0: function disabled,1: function enabled" bitfld.long 0x0 2. "TSTIOEN2,Time Stamp by Tamper I/O 2 enable" "0: function disabled,1: function enabled" newline bitfld.long 0x0 1. "TSTIOEN1,Time Stamp by Tamper I/O 1 enable" "0: function disabled,1: function enabled" endif bitfld.long 0x0 0. "TSTIOEN0,Time Stamp by Tamper I/O 0 enable" "0: function disabled,1: function enabled" wgroup.long 0x1170++0x3 line.long 0x0 "LFSS_TSCLR,Time Stamp Clear Register" bitfld.long 0x0 0. "CLR,Clear time stamp and status register." "0: Writing 0 has no effect,1: clear time stamp event" group.long 0x11F0++0x3 line.long 0x0 "LFSS_LFSSRST,Low frequency sub-system reset request" bitfld.long 0x0 0. "VBATPOR,If set the register bit will request a power on reset to the PMU of the LFSS." "0: Writing this value has no effect.,1: Request power on reset to the LFSS." group.long 0x11FC++0x3 line.long 0x0 "LFSS_RTCLOCK,Real time clock lock register" bitfld.long 0x0 0. "PROTECT,If set the register bit will protect the CLKCTL SEC MIN HOUR DAY MON YEAR and LFSSRST from accidental writes." "0: RTC counter is writable.,1: RTC counter is read only access." sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1200)++0x3 line.long 0x0 "LFSS_TIOCTL[$1],Tamper I/O Control Register" bitfld.long 0x0 19. "OUTINV,Output inversion enable" "0: The output inversion is disabled.,1: The output inversion is enabled." bitfld.long 0x0 18. "INENA,input enable" "0: The input path is disabled.,1: The input path is enabled." newline bitfld.long 0x0 17. "PIPU,pull up enable" "0: The pull-up function is disabled.,1: The pull-up function is enabled." bitfld.long 0x0 16. "PIPD,pull down enable" "0: The pull-down function is disabled.,1: The pull-down function is enabled." newline bitfld.long 0x0 12.--13. "FILTEREN,Programmable counter length of digital glitch filter for TIO0" "0: no filter on the tamper I/O beyond CDC..,1: 1 FLCLK minimum sample (30us),2: 3 LFCLK minimum sample (100us),3: 6 LFCLK minimum sample (200us)" bitfld.long 0x0 8.--9. "POLARITY,Enables and configures edge detection polarity for TIO" "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 4.--5. "TOUTSEL,Selects the source for TOUT control" "0: The TOUT register is the source for TOUT,1: The LFCLK is the source for TOUT,2: The heart beat generatore is the source for TOUT,3: The time stamp event status is the source for TOUT" bitfld.long 0x0 0. "IOMUX,tamper I/O is controlled by SoC IOMUX module" "0: The tamper I/O is controlled by the IOMUX of the..,1: The tamper I/O is controlled by the TIOCTL.." repeat.end group.long 0x1284++0xB line.long 0x0 "LFSS_TOUT7_4,Tamper Output 7 to 4" bitfld.long 0x0 24. "TIO7,This bit sets the value of the pin tamper I/O 7 (TIO7) when the output is enabled through TOE7 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "TIO6,This bit sets the value of the pin tamper I/O 2 (TIO6) when the output is enabled through TOE6 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "TIO5,This bit sets the value of the pin tamper I/O 5 (TIO5) when the output is enabled through TOE5 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "TIO4,This bit sets the value of the pin tamper I/O 4 (TIO4) when the output is enabled through TOE4 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "LFSS_TOUT11_8,Tamper Output 11 to 8" bitfld.long 0x4 24. "TIO11,This bit sets the value of the pin tamper I/O 11 (TIO11) when the output is enabled through TOE11 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "TIO10,This bit sets the value of the pin tamper I/O 10 (TIO10) when the output is enabled through TOE10 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "TIO9,This bit sets the value of the pin tamper I/O 9 (TIO9) when the output is enabled through TOE9 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "TIO8,This bit sets the value of the pin tamper I/O 8 (TIO8) when the output is enabled through TOE8 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "LFSS_TOUT15_12,Tamper Output 15 to 12" bitfld.long 0x8 24. "TIO15,This bit sets the value of the pin tamper I/O 15 (TIO15) when the output is enabled through TOE15 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "TIO14,This bit sets the value of the pin tamper I/O 14 (TIO14) when the output is enabled through TOE14 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "TIO13,This bit sets the value of the pin tamper I/O 13 (TIO13) when the output is enabled through TOE13 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "TIO12,This bit sets the value of the pin tamper I/O 12 (TIO12) when the output is enabled through TOE12 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1294++0xB line.long 0x0 "LFSS_TOE7_4,Tamper Output Enable 7 to 4" bitfld.long 0x0 24. "TIO7,Enables data output for tamper I/O 7" "0: output disabled,1: output enabled" bitfld.long 0x0 16. "TIO6,Enables data output for tamper I/O 6" "0: output disabled,1: output enabled" newline bitfld.long 0x0 8. "TIO5,Enables data output for tamper I/O 5" "0: output disabled,1: output enabled" bitfld.long 0x0 0. "TIO4,Enables data output for tamper I/O 4" "0: output disabled,1: output enabled" line.long 0x4 "LFSS_TOE11_8,Tamper Output Enable 7 to 4" bitfld.long 0x4 24. "TIO11,Enables data output for tamper I/O 11" "0: output disabled,1: output enabled" bitfld.long 0x4 16. "TIO10,Enables data output for tamper I/O 10" "0: output disabled,1: output enabled" newline bitfld.long 0x4 8. "TIO9,Enables data output for tamper I/O 9" "0: output disabled,1: output enabled" bitfld.long 0x4 0. "TIO8,Enables data output for tamper I/O 8" "0: output disabled,1: output enabled" line.long 0x8 "LFSS_TOE15_12,Tamper Output Enable 7 to 4" bitfld.long 0x8 24. "TIO15,Enables data output for tamper I/O 15" "0: output disabled,1: output enabled" bitfld.long 0x8 16. "TIO14,Enables data output for tamper I/O 14" "0: output disabled,1: output enabled" newline bitfld.long 0x8 8. "TIO13,Enables data output for tamper I/O 13" "0: output disabled,1: output enabled" bitfld.long 0x8 0. "TIO12,Enables data output for tamper I/O 12" "0: output disabled,1: output enabled" rgroup.long 0x12A4++0xB line.long 0x0 "LFSS_TIN7_4,Tamper Input Register" bitfld.long 0x0 24. "TIO7,This bit reads the data input value of tamper I/O 7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "TIO6,This bit reads the data input value of tamper I/O 6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "TIO5,This bit reads the data input value of tamper I/O 5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "TIO4,This bit reads the data input value of tamper I/O 4." "0: Input value is 0,1: Input value is 1" line.long 0x4 "LFSS_TIN11_8,Tamper Input Register" bitfld.long 0x4 24. "TIO11,This bit reads the data input value of tamper I/O 11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "TIO10,This bit reads the data input value of tamper I/O 10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "TIO9,This bit reads the data input value of tamper I/O 9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "TIO8,This bit reads the data input value of tamper I/O 8." "0: Input value is 0,1: Input value is 1" line.long 0x8 "LFSS_TIN15_12,Tamper Input Register" bitfld.long 0x8 24. "TIO15,This bit reads the data input value of tamper I/O 15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "TIO14,This bit reads the data input value of tamper I/O 14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "TIO13,This bit reads the data input value of tamper I/O 13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "TIO12,This bit reads the data input value of tamper I/O 12." "0: Input value is 0,1: Input value is 1" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1400)++0x3 line.long 0x0 "LFSS_SPMEM[$1],Scratch Pad Memory Data Register" hexmask.long.byte 0x0 24.--31. 1. "DATA3,memory data byte 3" hexmask.long.byte 0x0 16.--23. 1. "DATA2,memory data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "DATA1,memory data byte 1" hexmask.long.byte 0x0 0.--7. 1. "DATA0,memory data byte 0" repeat.end group.long 0x1504++0x1B line.long 0x0 "LFSS_SPMWPROT1,Scratch Pad Memory Write Protect Register 1" bitfld.long 0x0 15. "WP_7_3,write protect SPMEM7 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 14. "WP_7_2,write protect SPMEM7 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 13. "WP_7_1,write protect SPMEM7 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 12. "WP_7_0,write protect SPMEM7 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 11. "WP_6_3,write protect SPMEM6 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 10. "WP_6_2,write protect SPMEM6 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 9. "WP_6_1,write protect SPMEM6 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 8. "WP_6_0,write protect SPMEM6 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 7. "WP_5_3,write protect SPMEM5 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 6. "WP_5_2,write protect SPMEM5 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 5. "WP_5_1,write protect SPMEM5 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 4. "WP_5_0,write protect SPMEM5 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 3. "WP_4_3,write protect SPMEM4 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 2. "WP_4_2,write protect SPMEM4 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 1. "WP_4_1,write protect SPMEM4 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 0. "WP_4_0,write protect SPMEM4 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x4 "LFSS_SPMWPROT2,Scratch Pad Memory Write Protect Register 2" bitfld.long 0x4 15. "WP_11_3,write protect SPMEM11 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 14. "WP_11_2,write protect SPMEM11 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 13. "WP_11_1,write protect SPMEM11 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 12. "WP_11_0,write protect SPMEM11 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 11. "WP_10_3,write protect SPMEM10 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 10. "WP_10_2,write protect SPMEM610- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 9. "WP_10_1,write protect SPMEM10 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 8. "WP_10_0,write protect SPMEM10 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 7. "WP_9_3,write protect SPMEM9 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 6. "WP_9_2,write protect SPMEM9 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 5. "WP_9_1,write protect SPMEM9 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 4. "WP_9_0,write protect SPMEM9 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 3. "WP_8_3,write protect SPMEM8 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 2. "WP_8_2,write protect SPMEM8 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 1. "WP_8_1,write protect SPMEM8 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 0. "WP_8_0,write protect SPMEM8 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x8 "LFSS_SPMWPROT3,Scratch Pad Memory Write Protect Register 3" bitfld.long 0x8 15. "WP_15_3,write protect SPMEM15 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 14. "WP_15_2,write protect SPMEM15 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 13. "WP_15_1,write protect SPMEM15 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 12. "WP_15_0,write protect SPMEM15 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 11. "WP_14_3,write protect SPMEM14 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 10. "WP_14_2,write protect SPMEM14- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 9. "WP_14_1,write protect SPMEM14 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 8. "WP_14_0,write protect SPMEM14 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 7. "WP_13_3,write protect SPMEM13 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 6. "WP_13_2,write protect SPMEM13 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 5. "WP_13_1,write protect SPMEM13 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 4. "WP_13_0,write protect SPMEM13 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 3. "WP_12_3,write protect SPMEM12 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 2. "WP_12_2,write protect SPMEM12 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 1. "WP_12_1,write protect SPMEM12 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 0. "WP_12_0,write protect SPMEM12 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0xC "LFSS_SPMWPROT4,Scratch Pad Memory Write Protect Register 4" bitfld.long 0xC 15. "WP_19_3,write protect SPMEM19 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 14. "WP_19_2,write protect SPMEM19 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 13. "WP_19_1,write protect SPMEM19 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 12. "WP_19_0,write protect SPMEM19 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 11. "WP_18_3,write protect SPMEM18 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 10. "WP_18_2,write protect SPMEM18- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 9. "WP_18_1,write protect SPMEM18 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 8. "WP_18_0,write protect SPMEM18 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 7. "WP_17_3,write protect SPMEM17 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 6. "WP_17_2,write protect SPMEM17 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 5. "WP_17_1,write protect SPMEM17 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 4. "WP_17_0,write protect SPMEM17 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 3. "WP_16_3,write protect SPMEM16 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 2. "WP_16_2,write protect SPMEM16 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 1. "WP_16_1,write protect SPMEM16 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 0. "WP_16_0,write protect SPMEM16 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x10 "LFSS_SPMWPROT5,Scratch Pad Memory Write Protect Register 5" bitfld.long 0x10 15. "WP_23_3,write protect SPMEM23 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 14. "WP_23_2,write protect SPMEM23 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 13. "WP_23_1,write protect SPMEM23 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 12. "WP_23_0,write protect SPMEM23 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 11. "WP_22_3,write protect SPMEM22 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 10. "WP_22_2,write protect SPMEM22- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 9. "WP_22_1,write protect SPMEM22 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 8. "WP_22_0,write protect SPMEM22 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 7. "WP_21_3,write protect SPMEM21 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 6. "WP_21_2,write protect SPMEM21 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 5. "WP_21_1,write protect SPMEM21 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 4. "WP_21_0,write protect SPMEM21 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 3. "WP_20_3,write protect SPMEM20 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 2. "WP_20_2,write protect SPMEM20 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 1. "WP_20_1,write protect SPMEM20 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 0. "WP_20_0,write protect SPMEM20 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x14 "LFSS_SPMWPROT6,Scratch Pad Memory Write Protect Register 6" bitfld.long 0x14 15. "WP_27_3,write protect SPMEM27 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 14. "WP_27_2,write protect SPMEM27 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 13. "WP_27_1,write protect SPMEM27 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 12. "WP_27_0,write protect SPMEM27 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 11. "WP_26_3,write protect SPMEM26 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 10. "WP_26_2,write protect SPMEM26- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 9. "WP_26_1,write protect SPMEM26 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 8. "WP_26_0,write protect SPMEM26 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 7. "WP_25_3,write protect SPMEM25 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 6. "WP_25_2,write protect SPMEM25 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 5. "WP_25_1,write protect SPMEM25 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 4. "WP_25_0,write protect SPMEM25 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 3. "WP_24_3,write protect SPMEM24 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 2. "WP_24_2,write protect SPMEM24 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 1. "WP_24_1,write protect SPMEM24 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 0. "WP_24_0,write protect SPMEM24 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x18 "LFSS_SPMWPROT7,Scratch Pad Memory Write Protect Register 7" bitfld.long 0x18 15. "WP_31_3,write protect SPMEM31 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 14. "WP_31_2,write protect SPMEM31 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 13. "WP_31_1,write protect SPMEM31 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 12. "WP_31_0,write protect SPMEM31 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 11. "WP_30_3,write protect SPMEM30 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 10. "WP_30_2,write protect SPMEM30- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 9. "WP_30_1,write protect SPMEM30 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 8. "WP_30_0,write protect SPMEM30 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 7. "WP_29_3,write protect SPMEM29 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 6. "WP_29_2,write protect SPMEM29 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 5. "WP_29_1,write protect SPMEM29 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 4. "WP_29_0,write protect SPMEM29 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 3. "WP_28_3,write protect SPMEM28 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 2. "WP_28_2,write protect SPMEM28 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 1. "WP_28_1,write protect SPMEM28 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 0. "WP_28_0,write protect SPMEM28 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" group.long 0x1544++0x1B line.long 0x0 "LFSS_SPMTERASE1,Scratch Pad Memory Tamper Erase Register 1" bitfld.long 0x0 15. "TE_7_3,tamper erase enable SPMEM7 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 14. "TE_7_2,tamper erase enable SPMEM7 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 13. "TE_7_1,tamper erase enable SPMEM7 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 12. "TE_7_0,tamper erase enable SPMEM7 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 11. "TE_6_3,tamper erase enable SPMEM6 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 10. "TE_6_2,tamper erase enable SPMEM6 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 9. "TE_6_1,tamper erase enable SPMEM6 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 8. "TE_6_0,tamper erase enable SPMEM6 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 7. "TE_5_3,tamper erase enable SPMEM5 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 6. "TE_5_2,tamper erase enable SPMEM5 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 5. "TE_5_1,tamper erase enable SPMEM5 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 4. "TE_5_0,tamper erase enable SPMEM5 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 3. "TE_4_3,tamper erase enable SPMEM4 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 2. "TE_4_2,tamper erase enable SPMEM4 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 1. "TE_4_1,tamper erase enable SPMEM4 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 0. "TE_4_0,tamper erase enable SPMEM4 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x4 "LFSS_SPMTERASE2,Scratch Pad Memory Tamper Erase Register 2" bitfld.long 0x4 15. "TE_11_3,tamper erase enable SPMEM11 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 14. "TE_11_2,tamper erase enable SPMEM11 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 13. "TE_11_1,tamper erase enable SPMEM11 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 12. "TE_11_0,tamper erase enable SPMEM11 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 11. "TE_10_3,tamper erase enable SPMEM10 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 10. "TE_10_2,tamper erase enable SPMEM10 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 9. "TE_10_1,tamper erase enable SPMEM10 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 8. "TE_10_0,tamper erase enable SPMEM10 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 7. "TE_9_3,tamper erase enable SPMEM9 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 6. "TE_9_2,tamper erase enable SPMEM9 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 5. "TE_9_1,tamper erase enable SPMEM9 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 4. "TE_9_0,tamper erase enable SPMEM9 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 3. "TE_8_3,tamper erase enable SPMEM8 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 2. "TE_8_2,tamper erase enable SPMEM8 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 1. "TE_8_1,tamper erase enable SPMEM8 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 0. "TE_8_0,tamper erase enable SPMEM8 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x8 "LFSS_SPMTERASE3,Scratch Pad Memory Tamper Erase Register 3" bitfld.long 0x8 15. "TE_15_3,tamper erase enable SPMEM15 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 14. "TE_15_2,tamper erase enable SPMEM15 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 13. "TE_15_1,tamper erase enable SPMEM15 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 12. "TE_15_0,tamper erase enable SPMEM15 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 11. "TE_14_3,tamper erase enable SPMEM14 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 10. "TE_14_2,tamper erase enable SPMEM14 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 9. "TE_14_1,tamper erase enable SPMEM14 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 8. "TE_14_0,tamper erase enable SPMEM14 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 7. "TE_13_3,tamper erase enable SPMEM13 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 6. "TE_13_2,tamper erase enable SPMEM13 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 5. "TE_13_1,tamper erase enable SPMEM13 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 4. "TE_13_0,tamper erase enable SPMEM13 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 3. "TE_12_3,tamper erase enable SPMEM12 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 2. "TE_12_2,tamper erase enable SPMEM12 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 1. "TE_12_1,tamper erase enable SPMEM12 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 0. "TE_12_0,tamper erase enable SPMEM12 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0xC "LFSS_SPMTERASE4,Scratch Pad Memory Tamper Erase Register 4" bitfld.long 0xC 15. "TE_19_3,tamper erase enable SPMEM19 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 14. "TE_19_2,tamper erase enable SPMEM19 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 13. "TE_19_1,tamper erase enable SPMEM19 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 12. "TE_19_0,tamper erase enable SPMEM19 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 11. "TE_18_3,tamper erase enable SPMEM18 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 10. "TE_18_2,tamper erase enable SPMEM18 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 9. "TE_18_1,tamper erase enable SPMEM18 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 8. "TE_18_0,tamper erase enable SPMEM18 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 7. "TE_17_3,tamper erase enable SPMEM17 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 6. "TE_17_2,tamper erase enable SPMEM17 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 5. "TE_17_1,tamper erase enable SPMEM17 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 4. "TE_17_0,tamper erase enable SPMEM17 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 3. "TE_16_3,tamper erase enable SPMEM16 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 2. "TE_16_2,tamper erase enable SPMEM16 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 1. "TE_16_1,tamper erase enable SPMEM16 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 0. "TE_16_0,tamper erase enable SPMEM16 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x10 "LFSS_SPMTERASE5,Scratch Pad Memory Tamper Erase Register 5" bitfld.long 0x10 15. "TE_23_3,tamper erase enable SPMEM23 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 14. "TE_23_2,tamper erase enable SPMEM23 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 13. "TE_23_1,tamper erase enable SPMEM23 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 12. "TE_23_0,tamper erase enable SPMEM23 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 11. "TE_22_3,tamper erase enable SPMEM22 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 10. "TE_22_2,tamper erase enable SPMEM22 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 9. "TE_22_1,tamper erase enable SPMEM22 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 8. "TE_22_0,tamper erase enable SPMEM22 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 7. "TE_21_3,tamper erase enable SPMEM21 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 6. "TE_21_2,tamper erase enable SPMEM21 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 5. "TE_21_1,tamper erase enable SPMEM21 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 4. "TE_21_0,tamper erase enable SPMEM21 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 3. "TE_20_3,tamper erase enable SPMEM20 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 2. "TE_20_2,tamper erase enable SPMEM20 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 1. "TE_20_1,tamper erase enable SPMEM20 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 0. "TE_20_0,tamper erase enable SPMEM20 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x14 "LFSS_SPMTERASE6,Scratch Pad Memory Tamper Erase Register 6" bitfld.long 0x14 15. "TE_27_3,tamper erase enable SPMEM27 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 14. "TE_27_2,tamper erase enable SPMEM27 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 13. "TE_27_1,tamper erase enable SPMEM27 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 12. "TE_27_0,tamper erase enable SPMEM27 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 11. "TE_26_3,tamper erase enable SPMEM26 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 10. "TE_26_2,tamper erase enable SPMEM26 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 9. "TE_26_1,tamper erase enable SPMEM26 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 8. "TE_26_0,tamper erase enable SPMEM26 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 7. "TE_25_3,tamper erase enable SPMEM25 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 6. "TE_25_2,tamper erase enable SPMEM25 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 5. "TE_25_1,tamper erase enable SPMEM25 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 4. "TE_25_0,tamper erase enable SPMEM25 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 3. "TE_24_3,tamper erase enable SPMEM24 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 2. "TE_24_2,tamper erase enable SPMEM24 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 1. "TE_24_1,tamper erase enable SPMEM24 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 0. "TE_24_0,tamper erase enable SPMEM24 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x18 "LFSS_SPMTERASE7,Scratch Pad Memory Tamper Erase Register 7" bitfld.long 0x18 15. "TE_31_3,tamper erase enable SPMEM31 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 14. "TE_31_2,tamper erase enable SPMEM31 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 13. "TE_31_1,tamper erase enable SPMEM31 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 12. "TE_31_0,tamper erase enable SPMEM31 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 11. "TE_30_3,tamper erase enable SPMEM30 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 10. "TE_30_2,tamper erase enable SPMEM30 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 9. "TE_30_1,tamper erase enable SPMEM30 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 8. "TE_30_0,tamper erase enable SPMEM30 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 7. "TE_29_3,tamper erase enable SPMEM29 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 6. "TE_29_2,tamper erase enable SPMEM29 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 5. "TE_29_1,tamper erase enable SPMEM29 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 4. "TE_29_0,tamper erase enable SPMEM29 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 3. "TE_28_3,tamper erase enable SPMEM28 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 2. "TE_28_2,tamper erase enable SPMEM28 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 1. "TE_28_1,tamper erase enable SPMEM28 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 0. "TE_28_0,tamper erase enable SPMEM28 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" endif sif (cpuis("MSPM0L111*")) group.long 0x1200++0x3 line.long 0x0 "LFSS_TIOCTL,Tamper I/O Control Register" bitfld.long 0x0 19. "OUTINV,Output inversion enable" "0: The output inversion is disabled.,1: The output inversion is enabled." bitfld.long 0x0 18. "INENA,input enable" "0: The input path is disabled.,1: The input path is enabled." newline bitfld.long 0x0 17. "PIPU,pull up enable" "0: The pull-up function is disabled.,1: The pull-up function is enabled." bitfld.long 0x0 16. "PIPD,pull down enable" "0: The pull-down function is disabled.,1: The pull-down function is enabled." newline bitfld.long 0x0 12.--13. "FILTEREN,Programmable counter length of digital glitch filter for TIO0" "0: no filter on the tamper I/O beyond CDC..,1: 1 FLCLK minimum sample (30us),2: 3 LFCLK minimum sample (100us),3: 6 LFCLK minimum sample (200us)" bitfld.long 0x0 8.--9. "POLARITY,Enables and configures edge detection polarity for TIO" "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 4.--5. "TOUTSEL,Selects the source for TOUT control" "0: The TOUT register is the source for TOUT,1: The LFCLK is the source for TOUT,2: The heart beat generatore is the source for TOUT,3: The time stamp event status is the source for TOUT" bitfld.long 0x0 0. "IOMUX,tamper I/O is controlled by SoC IOMUX module" "0: The tamper I/O is controlled by the IOMUX of the..,1: The tamper I/O is controlled by the TIOCTL.." endif group.long 0x1280++0x3 line.long 0x0 "LFSS_TOUT3_0,Tamper Output 3 to 0" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 24. "TIO3,This bit sets the value of the pin tamper I/O 3 (TIO3) when the output is enabled through TOE3 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 16. "TIO2,This bit sets the value of the pin tamper I/O 2 (TIO0) when the output is enabled through TOE2 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "TIO1,This bit sets the value of the pin tamper I/O 1 (TIO1) when the output is enabled through TOE1 register." "0: Output is set to 0,1: Output is set to 1" endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 24. "TIO3,This bit sets the value of the pin tamper I/O 3 (TIO3) when the output is enabled through TOE3 register." "0: Output is set to 0,1: Output is set to 1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 24. "TIO3,This bit sets the value of the pin tamper I/O 3 (TIO3) when the output is enabled through TOE3 register." "0: Output is set to 0,1: Output is set to 1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 16. "TIO2,This bit sets the value of the pin tamper I/O 2 (TIO0) when the output is enabled through TOE2 register." "0: Output is set to 0,1: Output is set to 1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 16. "TIO2,This bit sets the value of the pin tamper I/O 2 (TIO0) when the output is enabled through TOE2 register." "0: Output is set to 0,1: Output is set to 1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 8. "TIO1,This bit sets the value of the pin tamper I/O 1 (TIO1) when the output is enabled through TOE1 register." "0: Output is set to 0,1: Output is set to 1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 8. "TIO1,This bit sets the value of the pin tamper I/O 1 (TIO1) when the output is enabled through TOE1 register." "0: Output is set to 0,1: Output is set to 1" newline endif bitfld.long 0x0 0. "TIO0,This bit sets the value of the pin tamper I/O 0 (TIO0) when the output is enabled through TOE0 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1290++0x3 line.long 0x0 "LFSS_TOE3_0,Tamper Output Enable 3 to 0" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 24. "TIO3,Enables data output for tamper I/O 3" "0: output disabled,1: output enabled" newline bitfld.long 0x0 16. "TIO2,Enables data output for tamper I/O 2" "0: output disabled,1: output enabled" newline bitfld.long 0x0 8. "TIO1,Enables data output for tamper I/O 1" "0: output disabled,1: output enabled" endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 24. "TIO3,Enables data output for tamper I/O 3" "0: output disabled,1: output enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 24. "TIO3,Enables data output for tamper I/O 3" "0: output disabled,1: output enabled" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 16. "TIO2,Enables data output for tamper I/O 2" "0: output disabled,1: output enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 16. "TIO2,Enables data output for tamper I/O 2" "0: output disabled,1: output enabled" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 8. "TIO1,Enables data output for tamper I/O 1" "0: output disabled,1: output enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 8. "TIO1,Enables data output for tamper I/O 1" "0: output disabled,1: output enabled" newline endif bitfld.long 0x0 0. "TIO0,Enables data output for tamper I/O 0" "0: output disabled,1: output enabled" rgroup.long 0x12A0++0x3 line.long 0x0 "LFSS_TIN3_0,Tamper Input Register" sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) bitfld.long 0x0 24. "TIO3,This bit reads the data input value of tamper I/O 3." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 16. "TIO2,This bit reads the data input value of tamper I/O 2." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "TIO1,This bit reads the data input value of tamper I/O 1." "0: Input value is 0,1: Input value is 1" endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 24. "TIO3,This bit reads the data input value of tamper I/O 3." "0: Input value is 0,1: Input value is 1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 24. "TIO3,This bit reads the data input value of tamper I/O 3." "0: Input value is 0,1: Input value is 1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 16. "TIO2,This bit reads the data input value of tamper I/O 2." "0: Input value is 0,1: Input value is 1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 16. "TIO2,This bit reads the data input value of tamper I/O 2." "0: Input value is 0,1: Input value is 1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 8. "TIO1,This bit reads the data input value of tamper I/O 1." "0: Input value is 0,1: Input value is 1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 8. "TIO1,This bit reads the data input value of tamper I/O 1." "0: Input value is 0,1: Input value is 1" newline endif bitfld.long 0x0 0. "TIO0,This bit reads the data input value of tamper I/O 0." "0: Input value is 0,1: Input value is 1" group.long 0x12C0++0x3 line.long 0x0 "LFSS_HEARTBEAT,Heartbeat Register" bitfld.long 0x0 16.--17. "HBMODE,Heart beat mode" "0: Heart beat disabled,1: Heart beat allways enabled,2: Heart beat enabled when time stamp event detected,3: Heart beat when VDD has fail condition" bitfld.long 0x0 8.--10. "HBWIDTH,Heart beat interval width" "0: Heart beat pulse width 1 msec,1: Heart beat pulse width 2 msec,2: Heart beat pulse width 4 msec,3: Heart beat pulse width 8 msec,4: Heart beat pulse width 16 msec,5: Heart beat pulse width 32 msec,6: Heart beat pulse width 64 msec,7: Heart beat pulse width 128 msec" newline bitfld.long 0x0 0.--2. "HBINTERVAL,Heart beat interval" "0: Heart beat interval 0.125 sec,1: Heart beat interval 0.25 sec,2: Heart beat interval 0.5 sec,3: Heart beat interval 1 sec,4: Heart beat interval 2 sec,5: Heart beat interval 4 sec,6: Heart beat interval 8 sec,7: Heart beat interval 16 sec" group.long 0x12FC++0xF line.long 0x0 "LFSS_TIOLOCK,Tamper I/O lock register" bitfld.long 0x0 0. "PROTECT,If set the register bit will protect the TIOCTL and HEARTBEAT from accidental writes." "0: Tamper I/O control is writable.,1: Tamper I/O control is read only access." line.long 0x4 "LFSS_WDTEN,Watchdog Timer Enable Register" bitfld.long 0x4 0. "ENABLE,Enable bit for the WDT." "0: Disable WDT,1: Enable WDT" line.long 0x8 "LFSS_WDTDBGCTL,Watchdog Timer Debug Control Register" bitfld.long 0x8 0. "FREE,Free run control" "0: The WDT freezes functionality while the CPU is..,1: The WDT ignores the state of the CPU Halted.." line.long 0xC "LFSS_WDTCTL,Watchdog Timer Control Register" bitfld.long 0xC 4.--6. "PER,Timer Period of the WDT. These bits select the total watchdog timer count." "0: Total timer count is 2^25,1: Total timer count is 2^21,2: Total timer count is 2^18,3: Total timer count is 2^15,4: Total timer count is 2^12 (default),5: Total timer count is 2^10,6: Total timer count is 2^8,7: Total timer count is 2^6" bitfld.long 0xC 0.--2. "CLKDIV,Module Clock Divider Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible." "0: Minimum value,?,?,?,?,?,?,7: Maximum value" wgroup.long 0x130C++0x3 line.long 0x0 "LFSS_WDTCNTRST,Watchdog Timer Counter Reset Register" hexmask.long 0x0 0.--31. 1. "RESTART,Writing 03A7h to this register restarts the WDT Counter. Writing any other value causes a POR level reset. Read as 0x0h." rgroup.long 0x1310++0x3 line.long 0x0 "LFSS_WDTSTAT,Watchdog Timer Status Register" bitfld.long 0x0 0. "RUN,Watchdog running status flag." "0: Watchdog counter stopped.,1: Watchdog running." group.long 0x13FC++0x3 line.long 0x0 "LFSS_WDTLOCK,Watchdog timer lock register" bitfld.long 0x0 0. "PROTECT,If set the register bit will protect the WDTEN and WDTCTL from accidental writes." "0: Watchdog timer control is writable.,1: Watchdog timer control is read only access." group.long 0x1500++0x3 line.long 0x0 "LFSS_SPMWPROT0,Scratch Pad Memory Write Protect Register 0" bitfld.long 0x0 15. "WP_3_3,write protect SPMEM3 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 14. "WP_3_2,write protect SPMEM3 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 13. "WP_3_1,write protect SPMEM3 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 12. "WP_3_0,write protect SPMEM3 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 11. "WP_2_3,write protect SPMEM2 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 10. "WP_2_2,write protect SPMEM2 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 9. "WP_2_1,write protect SPMEM2 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 8. "WP_2_0,write protect SPMEM2 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 7. "WP_1_3,write protect SPMEM1 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 6. "WP_1_2,write protect SPMEM1 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 5. "WP_1_1,write protect SPMEM1 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 4. "WP_1_0,write protect SPMEM1 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 3. "WP_0_3,write protect SPMEM0 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 2. "WP_0_2,write protect SPMEM0 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 1. "WP_0_1,write protect SPMEM0 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 0. "WP_0_0,write protect SPMEM0 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" group.long 0x1540++0x3 line.long 0x0 "LFSS_SPMTERASE0,Scratch Pad Memory Tamper Erase Register 0" bitfld.long 0x0 15. "TE_3_3,tamper erase enable SPMEM3 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 14. "TE_3_2,tamper erase enable SPMEM3 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 13. "TE_3_1,tamper erase enable SPMEM3 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 12. "TE_3_0,tamper erase enable SPMEM3 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 11. "TE_2_3,tamper erase enable SPMEM2 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 10. "TE_2_2,tamper erase enable SPMEM2 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 9. "TE_2_1,tamper erase enable SPMEM2 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 8. "TE_2_0,tamper erase enable SPMEM2 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 7. "TE_1_3,tamper erase enable SPMEM1 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 6. "TE_1_2,tamper erase enable SPMEM1 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 5. "TE_1_1,tamper erase enable SPMEM1 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 4. "TE_1_0,tamper erase enable SPMEM1 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 3. "TE_0_3,tamper erase enable SPMEM0 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 2. "TE_0_2,tamper erase enable SPMEM0 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 1. "TE_0_1,tamper erase enable SPMEM0 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 0. "TE_0_0,tamper erase enable SPMEM0 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" sif (cpuis("MSPM0L111*")) repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1400)++0x3 line.long 0x0 "LFSS_SPMEM[$1],Scratch Pad Memory Data Register" hexmask.long.byte 0x0 24.--31. 1. "DATA3,memory data byte 3" hexmask.long.byte 0x0 16.--23. 1. "DATA2,memory data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "DATA1,memory data byte 1" hexmask.long.byte 0x0 0.--7. 1. "DATA0,memory data byte 0" repeat.end endif sif (cpuis("MSPM0L122*")) tree "LFSS_GEN_EVENT[%s]" base ad:0x40095050 rgroup.long 0x0++0x3 line.long 0x0 "LFSS_GEN_EVENT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "LFSS_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LFSS_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "LFSS_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "LFSS_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "LFSS_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0L122*")) repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1200)++0x3 line.long 0x0 "LFSS_TIOCTL[$1],Tamper I/O Control Register" bitfld.long 0x0 19. "OUTINV,Output inversion enable" "0: The output inversion is disabled.,1: The output inversion is enabled." bitfld.long 0x0 18. "INENA,input enable" "0: The input path is disabled.,1: The input path is enabled." newline bitfld.long 0x0 17. "PIPU,pull up enable" "0: The pull-up function is disabled.,1: The pull-up function is enabled." bitfld.long 0x0 16. "PIPD,pull down enable" "0: The pull-down function is disabled.,1: The pull-down function is enabled." newline bitfld.long 0x0 12.--13. "FILTEREN,Programmable counter length of digital glitch filter for TIO0" "0: no filter on the tamper I/O beyond CDC..,1: 1 FLCLK minimum sample (30us),2: 3 LFCLK minimum sample (100us),3: 6 LFCLK minimum sample (200us)" bitfld.long 0x0 8.--9. "POLARITY,Enables and configures edge detection polarity for TIO" "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 4.--5. "TOUTSEL,Selects the source for TOUT control" "0: The TOUT register is the source for TOUT,1: The LFCLK is the source for TOUT,2: The heart beat generatore is the source for TOUT,3: The time stamp event status is the source for TOUT" bitfld.long 0x0 0. "IOMUX,tamper I/O is controlled by SoC IOMUX module" "0: The tamper I/O is controlled by the IOMUX of the..,1: The tamper I/O is controlled by the TIOCTL.." repeat.end group.long 0x1284++0xB line.long 0x0 "LFSS_TOUT7_4,Tamper Output 7 to 4" bitfld.long 0x0 24. "TIO7,This bit sets the value of the pin tamper I/O 7 (TIO7) when the output is enabled through TOE7 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "TIO6,This bit sets the value of the pin tamper I/O 2 (TIO6) when the output is enabled through TOE6 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "TIO5,This bit sets the value of the pin tamper I/O 5 (TIO5) when the output is enabled through TOE5 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "TIO4,This bit sets the value of the pin tamper I/O 4 (TIO4) when the output is enabled through TOE4 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "LFSS_TOUT11_8,Tamper Output 11 to 8" bitfld.long 0x4 24. "TIO11,This bit sets the value of the pin tamper I/O 11 (TIO11) when the output is enabled through TOE11 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "TIO10,This bit sets the value of the pin tamper I/O 10 (TIO10) when the output is enabled through TOE10 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "TIO9,This bit sets the value of the pin tamper I/O 9 (TIO9) when the output is enabled through TOE9 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "TIO8,This bit sets the value of the pin tamper I/O 8 (TIO8) when the output is enabled through TOE8 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "LFSS_TOUT15_12,Tamper Output 15 to 12" bitfld.long 0x8 24. "TIO15,This bit sets the value of the pin tamper I/O 15 (TIO15) when the output is enabled through TOE15 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "TIO14,This bit sets the value of the pin tamper I/O 14 (TIO14) when the output is enabled through TOE14 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "TIO13,This bit sets the value of the pin tamper I/O 13 (TIO13) when the output is enabled through TOE13 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "TIO12,This bit sets the value of the pin tamper I/O 12 (TIO12) when the output is enabled through TOE12 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1294++0xB line.long 0x0 "LFSS_TOE7_4,Tamper Output Enable 7 to 4" bitfld.long 0x0 24. "TIO7,Enables data output for tamper I/O 7" "0: output disabled,1: output enabled" bitfld.long 0x0 16. "TIO6,Enables data output for tamper I/O 6" "0: output disabled,1: output enabled" newline bitfld.long 0x0 8. "TIO5,Enables data output for tamper I/O 5" "0: output disabled,1: output enabled" bitfld.long 0x0 0. "TIO4,Enables data output for tamper I/O 4" "0: output disabled,1: output enabled" line.long 0x4 "LFSS_TOE11_8,Tamper Output Enable 7 to 4" bitfld.long 0x4 24. "TIO11,Enables data output for tamper I/O 11" "0: output disabled,1: output enabled" bitfld.long 0x4 16. "TIO10,Enables data output for tamper I/O 10" "0: output disabled,1: output enabled" newline bitfld.long 0x4 8. "TIO9,Enables data output for tamper I/O 9" "0: output disabled,1: output enabled" bitfld.long 0x4 0. "TIO8,Enables data output for tamper I/O 8" "0: output disabled,1: output enabled" line.long 0x8 "LFSS_TOE15_12,Tamper Output Enable 7 to 4" bitfld.long 0x8 24. "TIO15,Enables data output for tamper I/O 15" "0: output disabled,1: output enabled" bitfld.long 0x8 16. "TIO14,Enables data output for tamper I/O 14" "0: output disabled,1: output enabled" newline bitfld.long 0x8 8. "TIO13,Enables data output for tamper I/O 13" "0: output disabled,1: output enabled" bitfld.long 0x8 0. "TIO12,Enables data output for tamper I/O 12" "0: output disabled,1: output enabled" rgroup.long 0x12A4++0xB line.long 0x0 "LFSS_TIN7_4,Tamper Input Register" bitfld.long 0x0 24. "TIO7,This bit reads the data input value of tamper I/O 7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "TIO6,This bit reads the data input value of tamper I/O 6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "TIO5,This bit reads the data input value of tamper I/O 5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "TIO4,This bit reads the data input value of tamper I/O 4." "0: Input value is 0,1: Input value is 1" line.long 0x4 "LFSS_TIN11_8,Tamper Input Register" bitfld.long 0x4 24. "TIO11,This bit reads the data input value of tamper I/O 11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "TIO10,This bit reads the data input value of tamper I/O 10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "TIO9,This bit reads the data input value of tamper I/O 9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "TIO8,This bit reads the data input value of tamper I/O 8." "0: Input value is 0,1: Input value is 1" line.long 0x8 "LFSS_TIN15_12,Tamper Input Register" bitfld.long 0x8 24. "TIO15,This bit reads the data input value of tamper I/O 15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "TIO14,This bit reads the data input value of tamper I/O 14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "TIO13,This bit reads the data input value of tamper I/O 13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "TIO12,This bit reads the data input value of tamper I/O 12." "0: Input value is 0,1: Input value is 1" endif sif (cpuis("MSPM0L122*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1400)++0x3 line.long 0x0 "LFSS_SPMEM[$1],Scratch Pad Memory Data Register" hexmask.long.byte 0x0 24.--31. 1. "DATA3,memory data byte 3" hexmask.long.byte 0x0 16.--23. 1. "DATA2,memory data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "DATA1,memory data byte 1" hexmask.long.byte 0x0 0.--7. 1. "DATA0,memory data byte 0" repeat.end group.long 0x1504++0x1B line.long 0x0 "LFSS_SPMWPROT1,Scratch Pad Memory Write Protect Register 1" bitfld.long 0x0 15. "WP_7_3,write protect SPMEM7 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 14. "WP_7_2,write protect SPMEM7 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 13. "WP_7_1,write protect SPMEM7 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 12. "WP_7_0,write protect SPMEM7 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 11. "WP_6_3,write protect SPMEM6 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 10. "WP_6_2,write protect SPMEM6 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 9. "WP_6_1,write protect SPMEM6 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 8. "WP_6_0,write protect SPMEM6 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 7. "WP_5_3,write protect SPMEM5 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 6. "WP_5_2,write protect SPMEM5 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 5. "WP_5_1,write protect SPMEM5 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 4. "WP_5_0,write protect SPMEM5 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 3. "WP_4_3,write protect SPMEM4 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 2. "WP_4_2,write protect SPMEM4 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 1. "WP_4_1,write protect SPMEM4 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 0. "WP_4_0,write protect SPMEM4 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x4 "LFSS_SPMWPROT2,Scratch Pad Memory Write Protect Register 2" bitfld.long 0x4 15. "WP_11_3,write protect SPMEM11 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 14. "WP_11_2,write protect SPMEM11 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 13. "WP_11_1,write protect SPMEM11 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 12. "WP_11_0,write protect SPMEM11 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 11. "WP_10_3,write protect SPMEM10 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 10. "WP_10_2,write protect SPMEM610- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 9. "WP_10_1,write protect SPMEM10 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 8. "WP_10_0,write protect SPMEM10 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 7. "WP_9_3,write protect SPMEM9 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 6. "WP_9_2,write protect SPMEM9 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 5. "WP_9_1,write protect SPMEM9 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 4. "WP_9_0,write protect SPMEM9 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 3. "WP_8_3,write protect SPMEM8 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 2. "WP_8_2,write protect SPMEM8 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 1. "WP_8_1,write protect SPMEM8 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 0. "WP_8_0,write protect SPMEM8 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x8 "LFSS_SPMWPROT3,Scratch Pad Memory Write Protect Register 3" bitfld.long 0x8 15. "WP_15_3,write protect SPMEM15 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 14. "WP_15_2,write protect SPMEM15 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 13. "WP_15_1,write protect SPMEM15 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 12. "WP_15_0,write protect SPMEM15 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 11. "WP_14_3,write protect SPMEM14 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 10. "WP_14_2,write protect SPMEM14- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 9. "WP_14_1,write protect SPMEM14 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 8. "WP_14_0,write protect SPMEM14 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 7. "WP_13_3,write protect SPMEM13 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 6. "WP_13_2,write protect SPMEM13 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 5. "WP_13_1,write protect SPMEM13 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 4. "WP_13_0,write protect SPMEM13 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 3. "WP_12_3,write protect SPMEM12 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 2. "WP_12_2,write protect SPMEM12 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 1. "WP_12_1,write protect SPMEM12 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 0. "WP_12_0,write protect SPMEM12 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0xC "LFSS_SPMWPROT4,Scratch Pad Memory Write Protect Register 4" bitfld.long 0xC 15. "WP_19_3,write protect SPMEM19 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 14. "WP_19_2,write protect SPMEM19 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 13. "WP_19_1,write protect SPMEM19 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 12. "WP_19_0,write protect SPMEM19 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 11. "WP_18_3,write protect SPMEM18 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 10. "WP_18_2,write protect SPMEM18- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 9. "WP_18_1,write protect SPMEM18 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 8. "WP_18_0,write protect SPMEM18 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 7. "WP_17_3,write protect SPMEM17 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 6. "WP_17_2,write protect SPMEM17 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 5. "WP_17_1,write protect SPMEM17 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 4. "WP_17_0,write protect SPMEM17 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 3. "WP_16_3,write protect SPMEM16 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 2. "WP_16_2,write protect SPMEM16 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 1. "WP_16_1,write protect SPMEM16 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 0. "WP_16_0,write protect SPMEM16 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x10 "LFSS_SPMWPROT5,Scratch Pad Memory Write Protect Register 5" bitfld.long 0x10 15. "WP_23_3,write protect SPMEM23 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 14. "WP_23_2,write protect SPMEM23 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 13. "WP_23_1,write protect SPMEM23 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 12. "WP_23_0,write protect SPMEM23 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 11. "WP_22_3,write protect SPMEM22 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 10. "WP_22_2,write protect SPMEM22- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 9. "WP_22_1,write protect SPMEM22 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 8. "WP_22_0,write protect SPMEM22 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 7. "WP_21_3,write protect SPMEM21 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 6. "WP_21_2,write protect SPMEM21 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 5. "WP_21_1,write protect SPMEM21 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 4. "WP_21_0,write protect SPMEM21 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 3. "WP_20_3,write protect SPMEM20 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 2. "WP_20_2,write protect SPMEM20 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 1. "WP_20_1,write protect SPMEM20 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 0. "WP_20_0,write protect SPMEM20 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x14 "LFSS_SPMWPROT6,Scratch Pad Memory Write Protect Register 6" bitfld.long 0x14 15. "WP_27_3,write protect SPMEM27 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 14. "WP_27_2,write protect SPMEM27 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 13. "WP_27_1,write protect SPMEM27 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 12. "WP_27_0,write protect SPMEM27 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 11. "WP_26_3,write protect SPMEM26 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 10. "WP_26_2,write protect SPMEM26- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 9. "WP_26_1,write protect SPMEM26 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 8. "WP_26_0,write protect SPMEM26 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 7. "WP_25_3,write protect SPMEM25 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 6. "WP_25_2,write protect SPMEM25 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 5. "WP_25_1,write protect SPMEM25 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 4. "WP_25_0,write protect SPMEM25 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 3. "WP_24_3,write protect SPMEM24 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 2. "WP_24_2,write protect SPMEM24 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 1. "WP_24_1,write protect SPMEM24 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 0. "WP_24_0,write protect SPMEM24 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x18 "LFSS_SPMWPROT7,Scratch Pad Memory Write Protect Register 7" bitfld.long 0x18 15. "WP_31_3,write protect SPMEM31 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 14. "WP_31_2,write protect SPMEM31 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 13. "WP_31_1,write protect SPMEM31 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 12. "WP_31_0,write protect SPMEM31 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 11. "WP_30_3,write protect SPMEM30 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 10. "WP_30_2,write protect SPMEM30- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 9. "WP_30_1,write protect SPMEM30 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 8. "WP_30_0,write protect SPMEM30 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 7. "WP_29_3,write protect SPMEM29 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 6. "WP_29_2,write protect SPMEM29 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 5. "WP_29_1,write protect SPMEM29 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 4. "WP_29_0,write protect SPMEM29 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 3. "WP_28_3,write protect SPMEM28 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 2. "WP_28_2,write protect SPMEM28 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 1. "WP_28_1,write protect SPMEM28 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 0. "WP_28_0,write protect SPMEM28 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" group.long 0x1544++0x1B line.long 0x0 "LFSS_SPMTERASE1,Scratch Pad Memory Tamper Erase Register 1" bitfld.long 0x0 15. "TE_7_3,tamper erase enable SPMEM7 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 14. "TE_7_2,tamper erase enable SPMEM7 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 13. "TE_7_1,tamper erase enable SPMEM7 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 12. "TE_7_0,tamper erase enable SPMEM7 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 11. "TE_6_3,tamper erase enable SPMEM6 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 10. "TE_6_2,tamper erase enable SPMEM6 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 9. "TE_6_1,tamper erase enable SPMEM6 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 8. "TE_6_0,tamper erase enable SPMEM6 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 7. "TE_5_3,tamper erase enable SPMEM5 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 6. "TE_5_2,tamper erase enable SPMEM5 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 5. "TE_5_1,tamper erase enable SPMEM5 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 4. "TE_5_0,tamper erase enable SPMEM5 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 3. "TE_4_3,tamper erase enable SPMEM4 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 2. "TE_4_2,tamper erase enable SPMEM4 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 1. "TE_4_1,tamper erase enable SPMEM4 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 0. "TE_4_0,tamper erase enable SPMEM4 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x4 "LFSS_SPMTERASE2,Scratch Pad Memory Tamper Erase Register 2" bitfld.long 0x4 15. "TE_11_3,tamper erase enable SPMEM11 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 14. "TE_11_2,tamper erase enable SPMEM11 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 13. "TE_11_1,tamper erase enable SPMEM11 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 12. "TE_11_0,tamper erase enable SPMEM11 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 11. "TE_10_3,tamper erase enable SPMEM10 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 10. "TE_10_2,tamper erase enable SPMEM10 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 9. "TE_10_1,tamper erase enable SPMEM10 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 8. "TE_10_0,tamper erase enable SPMEM10 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 7. "TE_9_3,tamper erase enable SPMEM9 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 6. "TE_9_2,tamper erase enable SPMEM9 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 5. "TE_9_1,tamper erase enable SPMEM9 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 4. "TE_9_0,tamper erase enable SPMEM9 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 3. "TE_8_3,tamper erase enable SPMEM8 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 2. "TE_8_2,tamper erase enable SPMEM8 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 1. "TE_8_1,tamper erase enable SPMEM8 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 0. "TE_8_0,tamper erase enable SPMEM8 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x8 "LFSS_SPMTERASE3,Scratch Pad Memory Tamper Erase Register 3" bitfld.long 0x8 15. "TE_15_3,tamper erase enable SPMEM15 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 14. "TE_15_2,tamper erase enable SPMEM15 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 13. "TE_15_1,tamper erase enable SPMEM15 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 12. "TE_15_0,tamper erase enable SPMEM15 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 11. "TE_14_3,tamper erase enable SPMEM14 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 10. "TE_14_2,tamper erase enable SPMEM14 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 9. "TE_14_1,tamper erase enable SPMEM14 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 8. "TE_14_0,tamper erase enable SPMEM14 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 7. "TE_13_3,tamper erase enable SPMEM13 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 6. "TE_13_2,tamper erase enable SPMEM13 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 5. "TE_13_1,tamper erase enable SPMEM13 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 4. "TE_13_0,tamper erase enable SPMEM13 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 3. "TE_12_3,tamper erase enable SPMEM12 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 2. "TE_12_2,tamper erase enable SPMEM12 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 1. "TE_12_1,tamper erase enable SPMEM12 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 0. "TE_12_0,tamper erase enable SPMEM12 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0xC "LFSS_SPMTERASE4,Scratch Pad Memory Tamper Erase Register 4" bitfld.long 0xC 15. "TE_19_3,tamper erase enable SPMEM19 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 14. "TE_19_2,tamper erase enable SPMEM19 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 13. "TE_19_1,tamper erase enable SPMEM19 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 12. "TE_19_0,tamper erase enable SPMEM19 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 11. "TE_18_3,tamper erase enable SPMEM18 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 10. "TE_18_2,tamper erase enable SPMEM18 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 9. "TE_18_1,tamper erase enable SPMEM18 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 8. "TE_18_0,tamper erase enable SPMEM18 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 7. "TE_17_3,tamper erase enable SPMEM17 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 6. "TE_17_2,tamper erase enable SPMEM17 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 5. "TE_17_1,tamper erase enable SPMEM17 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 4. "TE_17_0,tamper erase enable SPMEM17 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 3. "TE_16_3,tamper erase enable SPMEM16 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 2. "TE_16_2,tamper erase enable SPMEM16 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 1. "TE_16_1,tamper erase enable SPMEM16 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 0. "TE_16_0,tamper erase enable SPMEM16 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x10 "LFSS_SPMTERASE5,Scratch Pad Memory Tamper Erase Register 5" bitfld.long 0x10 15. "TE_23_3,tamper erase enable SPMEM23 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 14. "TE_23_2,tamper erase enable SPMEM23 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 13. "TE_23_1,tamper erase enable SPMEM23 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 12. "TE_23_0,tamper erase enable SPMEM23 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 11. "TE_22_3,tamper erase enable SPMEM22 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 10. "TE_22_2,tamper erase enable SPMEM22 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 9. "TE_22_1,tamper erase enable SPMEM22 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 8. "TE_22_0,tamper erase enable SPMEM22 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 7. "TE_21_3,tamper erase enable SPMEM21 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 6. "TE_21_2,tamper erase enable SPMEM21 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 5. "TE_21_1,tamper erase enable SPMEM21 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 4. "TE_21_0,tamper erase enable SPMEM21 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 3. "TE_20_3,tamper erase enable SPMEM20 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 2. "TE_20_2,tamper erase enable SPMEM20 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 1. "TE_20_1,tamper erase enable SPMEM20 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 0. "TE_20_0,tamper erase enable SPMEM20 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x14 "LFSS_SPMTERASE6,Scratch Pad Memory Tamper Erase Register 6" bitfld.long 0x14 15. "TE_27_3,tamper erase enable SPMEM27 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 14. "TE_27_2,tamper erase enable SPMEM27 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 13. "TE_27_1,tamper erase enable SPMEM27 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 12. "TE_27_0,tamper erase enable SPMEM27 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 11. "TE_26_3,tamper erase enable SPMEM26 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 10. "TE_26_2,tamper erase enable SPMEM26 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 9. "TE_26_1,tamper erase enable SPMEM26 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 8. "TE_26_0,tamper erase enable SPMEM26 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 7. "TE_25_3,tamper erase enable SPMEM25 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 6. "TE_25_2,tamper erase enable SPMEM25 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 5. "TE_25_1,tamper erase enable SPMEM25 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 4. "TE_25_0,tamper erase enable SPMEM25 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 3. "TE_24_3,tamper erase enable SPMEM24 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 2. "TE_24_2,tamper erase enable SPMEM24 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 1. "TE_24_1,tamper erase enable SPMEM24 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 0. "TE_24_0,tamper erase enable SPMEM24 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x18 "LFSS_SPMTERASE7,Scratch Pad Memory Tamper Erase Register 7" bitfld.long 0x18 15. "TE_31_3,tamper erase enable SPMEM31 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 14. "TE_31_2,tamper erase enable SPMEM31 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 13. "TE_31_1,tamper erase enable SPMEM31 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 12. "TE_31_0,tamper erase enable SPMEM31 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 11. "TE_30_3,tamper erase enable SPMEM30 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 10. "TE_30_2,tamper erase enable SPMEM30 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 9. "TE_30_1,tamper erase enable SPMEM30 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 8. "TE_30_0,tamper erase enable SPMEM30 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 7. "TE_29_3,tamper erase enable SPMEM29 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 6. "TE_29_2,tamper erase enable SPMEM29 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 5. "TE_29_1,tamper erase enable SPMEM29 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 4. "TE_29_0,tamper erase enable SPMEM29 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 3. "TE_28_3,tamper erase enable SPMEM28 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 2. "TE_28_2,tamper erase enable SPMEM28 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 1. "TE_28_1,tamper erase enable SPMEM28 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 0. "TE_28_0,tamper erase enable SPMEM28 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" endif sif (cpuis("MSPM0L222*")) tree "LFSS_GEN_EVENT[%s]" base ad:0x40095050 rgroup.long 0x0++0x3 line.long 0x0 "LFSS_GEN_EVENT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "LFSS_GEN_EVENT_IMASK,Interrupt mask" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "LFSS_GEN_EVENT_RIS,Raw interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "LFSS_GEN_EVENT_MIS,Masked interrupt status" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Interrupt did not occur or is masked out,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "LFSS_GEN_EVENT_ISET,Interrupt set" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Set interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Set interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Set interrupt" wgroup.long 0x28++0x3 line.long 0x0 "LFSS_GEN_EVENT_ICLR,Interrupt clear" bitfld.long 0x0 23. "TIO15,Tamper I/O 15 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 22. "TIO14,Tamper I/O 14 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 21. "TIO13,Tamper I/O 13 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 20. "TIO12,Tamper I/O 12 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 19. "TIO11,Tamper I/O 11 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 18. "TIO10,Tamper I/O 10 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 17. "TIO9,Tamper I/O 9 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 16. "TIO8,Tamper I/O 8 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 15. "TIO7,Tamper I/O 7 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 14. "TIO6,Tamper I/O 6 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 13. "TIO5,Tamper I/O 5 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 12. "TIO4,Tamper I/O 4 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 11. "TIO3,Tamper I/O 3 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 10. "TIO2,Tamper I/O 2 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 9. "TIO1,Tamper I/O 1 event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 8. "TIO0,Tamper I/O 0 event" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 7. "TSEVT,Time stamp event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 6. "RT2PS,RTC prescale timer 2" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 5. "RT1PS,RTC prescale timer 1" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 4. "RT0PS,RTC prescale timer 0" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 3. "RTCA2,RTC alarm 2" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 2. "RTCA1,RTC alarm 1" "0: Writing 0 has no effect,1: Clear interrupt" newline bitfld.long 0x0 1. "RTCTEV,RTC time event" "0: Writing 0 has no effect,1: Clear interrupt" bitfld.long 0x0 0. "RTCRDY,RTC ready" "0: Writing 0 has no effect,1: Clear interrupt" tree.end endif sif (cpuis("MSPM0L222*")) repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1200)++0x3 line.long 0x0 "LFSS_TIOCTL[$1],Tamper I/O Control Register" bitfld.long 0x0 19. "OUTINV,Output inversion enable" "0: The output inversion is disabled.,1: The output inversion is enabled." bitfld.long 0x0 18. "INENA,input enable" "0: The input path is disabled.,1: The input path is enabled." newline bitfld.long 0x0 17. "PIPU,pull up enable" "0: The pull-up function is disabled.,1: The pull-up function is enabled." bitfld.long 0x0 16. "PIPD,pull down enable" "0: The pull-down function is disabled.,1: The pull-down function is enabled." newline bitfld.long 0x0 12.--13. "FILTEREN,Programmable counter length of digital glitch filter for TIO0" "0: no filter on the tamper I/O beyond CDC..,1: 1 FLCLK minimum sample (30us),2: 3 LFCLK minimum sample (100us),3: 6 LFCLK minimum sample (200us)" bitfld.long 0x0 8.--9. "POLARITY,Enables and configures edge detection polarity for TIO" "0: Edge detection disabled,1: Detects rising edge of input event,2: Detects falling edge of input event,3: Detects both rising and falling edge of input.." newline bitfld.long 0x0 4.--5. "TOUTSEL,Selects the source for TOUT control" "0: The TOUT register is the source for TOUT,1: The LFCLK is the source for TOUT,2: The heart beat generatore is the source for TOUT,3: The time stamp event status is the source for TOUT" bitfld.long 0x0 0. "IOMUX,tamper I/O is controlled by SoC IOMUX module" "0: The tamper I/O is controlled by the IOMUX of the..,1: The tamper I/O is controlled by the TIOCTL.." repeat.end group.long 0x1284++0xB line.long 0x0 "LFSS_TOUT7_4,Tamper Output 7 to 4" bitfld.long 0x0 24. "TIO7,This bit sets the value of the pin tamper I/O 7 (TIO7) when the output is enabled through TOE7 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 16. "TIO6,This bit sets the value of the pin tamper I/O 2 (TIO6) when the output is enabled through TOE6 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x0 8. "TIO5,This bit sets the value of the pin tamper I/O 5 (TIO5) when the output is enabled through TOE5 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x0 0. "TIO4,This bit sets the value of the pin tamper I/O 4 (TIO4) when the output is enabled through TOE4 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x4 "LFSS_TOUT11_8,Tamper Output 11 to 8" bitfld.long 0x4 24. "TIO11,This bit sets the value of the pin tamper I/O 11 (TIO11) when the output is enabled through TOE11 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 16. "TIO10,This bit sets the value of the pin tamper I/O 10 (TIO10) when the output is enabled through TOE10 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x4 8. "TIO9,This bit sets the value of the pin tamper I/O 9 (TIO9) when the output is enabled through TOE9 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x4 0. "TIO8,This bit sets the value of the pin tamper I/O 8 (TIO8) when the output is enabled through TOE8 register." "0: Output is set to 0,1: Output is set to 1" line.long 0x8 "LFSS_TOUT15_12,Tamper Output 15 to 12" bitfld.long 0x8 24. "TIO15,This bit sets the value of the pin tamper I/O 15 (TIO15) when the output is enabled through TOE15 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 16. "TIO14,This bit sets the value of the pin tamper I/O 14 (TIO14) when the output is enabled through TOE14 register." "0: Output is set to 0,1: Output is set to 1" newline bitfld.long 0x8 8. "TIO13,This bit sets the value of the pin tamper I/O 13 (TIO13) when the output is enabled through TOE13 register." "0: Output is set to 0,1: Output is set to 1" bitfld.long 0x8 0. "TIO12,This bit sets the value of the pin tamper I/O 12 (TIO12) when the output is enabled through TOE12 register." "0: Output is set to 0,1: Output is set to 1" group.long 0x1294++0xB line.long 0x0 "LFSS_TOE7_4,Tamper Output Enable 7 to 4" bitfld.long 0x0 24. "TIO7,Enables data output for tamper I/O 7" "0: output disabled,1: output enabled" bitfld.long 0x0 16. "TIO6,Enables data output for tamper I/O 6" "0: output disabled,1: output enabled" newline bitfld.long 0x0 8. "TIO5,Enables data output for tamper I/O 5" "0: output disabled,1: output enabled" bitfld.long 0x0 0. "TIO4,Enables data output for tamper I/O 4" "0: output disabled,1: output enabled" line.long 0x4 "LFSS_TOE11_8,Tamper Output Enable 7 to 4" bitfld.long 0x4 24. "TIO11,Enables data output for tamper I/O 11" "0: output disabled,1: output enabled" bitfld.long 0x4 16. "TIO10,Enables data output for tamper I/O 10" "0: output disabled,1: output enabled" newline bitfld.long 0x4 8. "TIO9,Enables data output for tamper I/O 9" "0: output disabled,1: output enabled" bitfld.long 0x4 0. "TIO8,Enables data output for tamper I/O 8" "0: output disabled,1: output enabled" line.long 0x8 "LFSS_TOE15_12,Tamper Output Enable 7 to 4" bitfld.long 0x8 24. "TIO15,Enables data output for tamper I/O 15" "0: output disabled,1: output enabled" bitfld.long 0x8 16. "TIO14,Enables data output for tamper I/O 14" "0: output disabled,1: output enabled" newline bitfld.long 0x8 8. "TIO13,Enables data output for tamper I/O 13" "0: output disabled,1: output enabled" bitfld.long 0x8 0. "TIO12,Enables data output for tamper I/O 12" "0: output disabled,1: output enabled" rgroup.long 0x12A4++0xB line.long 0x0 "LFSS_TIN7_4,Tamper Input Register" bitfld.long 0x0 24. "TIO7,This bit reads the data input value of tamper I/O 7." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 16. "TIO6,This bit reads the data input value of tamper I/O 6." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x0 8. "TIO5,This bit reads the data input value of tamper I/O 5." "0: Input value is 0,1: Input value is 1" bitfld.long 0x0 0. "TIO4,This bit reads the data input value of tamper I/O 4." "0: Input value is 0,1: Input value is 1" line.long 0x4 "LFSS_TIN11_8,Tamper Input Register" bitfld.long 0x4 24. "TIO11,This bit reads the data input value of tamper I/O 11." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 16. "TIO10,This bit reads the data input value of tamper I/O 10." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x4 8. "TIO9,This bit reads the data input value of tamper I/O 9." "0: Input value is 0,1: Input value is 1" bitfld.long 0x4 0. "TIO8,This bit reads the data input value of tamper I/O 8." "0: Input value is 0,1: Input value is 1" line.long 0x8 "LFSS_TIN15_12,Tamper Input Register" bitfld.long 0x8 24. "TIO15,This bit reads the data input value of tamper I/O 15." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 16. "TIO14,This bit reads the data input value of tamper I/O 14." "0: Input value is 0,1: Input value is 1" newline bitfld.long 0x8 8. "TIO13,This bit reads the data input value of tamper I/O 13." "0: Input value is 0,1: Input value is 1" bitfld.long 0x8 0. "TIO12,This bit reads the data input value of tamper I/O 12." "0: Input value is 0,1: Input value is 1" endif sif (cpuis("MSPM0L222*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1400)++0x3 line.long 0x0 "LFSS_SPMEM[$1],Scratch Pad Memory Data Register" hexmask.long.byte 0x0 24.--31. 1. "DATA3,memory data byte 3" hexmask.long.byte 0x0 16.--23. 1. "DATA2,memory data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "DATA1,memory data byte 1" hexmask.long.byte 0x0 0.--7. 1. "DATA0,memory data byte 0" repeat.end group.long 0x1504++0x1B line.long 0x0 "LFSS_SPMWPROT1,Scratch Pad Memory Write Protect Register 1" bitfld.long 0x0 15. "WP_7_3,write protect SPMEM7 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 14. "WP_7_2,write protect SPMEM7 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 13. "WP_7_1,write protect SPMEM7 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 12. "WP_7_0,write protect SPMEM7 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 11. "WP_6_3,write protect SPMEM6 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 10. "WP_6_2,write protect SPMEM6 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 9. "WP_6_1,write protect SPMEM6 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 8. "WP_6_0,write protect SPMEM6 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 7. "WP_5_3,write protect SPMEM5 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 6. "WP_5_2,write protect SPMEM5 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 5. "WP_5_1,write protect SPMEM5 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 4. "WP_5_0,write protect SPMEM5 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 3. "WP_4_3,write protect SPMEM4 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 2. "WP_4_2,write protect SPMEM4 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x0 1. "WP_4_1,write protect SPMEM4 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x0 0. "WP_4_0,write protect SPMEM4 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x4 "LFSS_SPMWPROT2,Scratch Pad Memory Write Protect Register 2" bitfld.long 0x4 15. "WP_11_3,write protect SPMEM11 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 14. "WP_11_2,write protect SPMEM11 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 13. "WP_11_1,write protect SPMEM11 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 12. "WP_11_0,write protect SPMEM11 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 11. "WP_10_3,write protect SPMEM10 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 10. "WP_10_2,write protect SPMEM610- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 9. "WP_10_1,write protect SPMEM10 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 8. "WP_10_0,write protect SPMEM10 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 7. "WP_9_3,write protect SPMEM9 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 6. "WP_9_2,write protect SPMEM9 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 5. "WP_9_1,write protect SPMEM9 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 4. "WP_9_0,write protect SPMEM9 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 3. "WP_8_3,write protect SPMEM8 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 2. "WP_8_2,write protect SPMEM8 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x4 1. "WP_8_1,write protect SPMEM8 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x4 0. "WP_8_0,write protect SPMEM8 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x8 "LFSS_SPMWPROT3,Scratch Pad Memory Write Protect Register 3" bitfld.long 0x8 15. "WP_15_3,write protect SPMEM15 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 14. "WP_15_2,write protect SPMEM15 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 13. "WP_15_1,write protect SPMEM15 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 12. "WP_15_0,write protect SPMEM15 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 11. "WP_14_3,write protect SPMEM14 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 10. "WP_14_2,write protect SPMEM14- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 9. "WP_14_1,write protect SPMEM14 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 8. "WP_14_0,write protect SPMEM14 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 7. "WP_13_3,write protect SPMEM13 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 6. "WP_13_2,write protect SPMEM13 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 5. "WP_13_1,write protect SPMEM13 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 4. "WP_13_0,write protect SPMEM13 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 3. "WP_12_3,write protect SPMEM12 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 2. "WP_12_2,write protect SPMEM12 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x8 1. "WP_12_1,write protect SPMEM12 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x8 0. "WP_12_0,write protect SPMEM12 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0xC "LFSS_SPMWPROT4,Scratch Pad Memory Write Protect Register 4" bitfld.long 0xC 15. "WP_19_3,write protect SPMEM19 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 14. "WP_19_2,write protect SPMEM19 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 13. "WP_19_1,write protect SPMEM19 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 12. "WP_19_0,write protect SPMEM19 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 11. "WP_18_3,write protect SPMEM18 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 10. "WP_18_2,write protect SPMEM18- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 9. "WP_18_1,write protect SPMEM18 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 8. "WP_18_0,write protect SPMEM18 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 7. "WP_17_3,write protect SPMEM17 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 6. "WP_17_2,write protect SPMEM17 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 5. "WP_17_1,write protect SPMEM17 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 4. "WP_17_0,write protect SPMEM17 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 3. "WP_16_3,write protect SPMEM16 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 2. "WP_16_2,write protect SPMEM16 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0xC 1. "WP_16_1,write protect SPMEM16 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0xC 0. "WP_16_0,write protect SPMEM16 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x10 "LFSS_SPMWPROT5,Scratch Pad Memory Write Protect Register 5" bitfld.long 0x10 15. "WP_23_3,write protect SPMEM23 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 14. "WP_23_2,write protect SPMEM23 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 13. "WP_23_1,write protect SPMEM23 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 12. "WP_23_0,write protect SPMEM23 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 11. "WP_22_3,write protect SPMEM22 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 10. "WP_22_2,write protect SPMEM22- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 9. "WP_22_1,write protect SPMEM22 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 8. "WP_22_0,write protect SPMEM22 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 7. "WP_21_3,write protect SPMEM21 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 6. "WP_21_2,write protect SPMEM21 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 5. "WP_21_1,write protect SPMEM21 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 4. "WP_21_0,write protect SPMEM21 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 3. "WP_20_3,write protect SPMEM20 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 2. "WP_20_2,write protect SPMEM20 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x10 1. "WP_20_1,write protect SPMEM20 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x10 0. "WP_20_0,write protect SPMEM20 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x14 "LFSS_SPMWPROT6,Scratch Pad Memory Write Protect Register 6" bitfld.long 0x14 15. "WP_27_3,write protect SPMEM27 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 14. "WP_27_2,write protect SPMEM27 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 13. "WP_27_1,write protect SPMEM27 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 12. "WP_27_0,write protect SPMEM27 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 11. "WP_26_3,write protect SPMEM26 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 10. "WP_26_2,write protect SPMEM26- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 9. "WP_26_1,write protect SPMEM26 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 8. "WP_26_0,write protect SPMEM26 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 7. "WP_25_3,write protect SPMEM25 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 6. "WP_25_2,write protect SPMEM25 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 5. "WP_25_1,write protect SPMEM25 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 4. "WP_25_0,write protect SPMEM25 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 3. "WP_24_3,write protect SPMEM24 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 2. "WP_24_2,write protect SPMEM24 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x14 1. "WP_24_1,write protect SPMEM24 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x14 0. "WP_24_0,write protect SPMEM24 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" line.long 0x18 "LFSS_SPMWPROT7,Scratch Pad Memory Write Protect Register 7" bitfld.long 0x18 15. "WP_31_3,write protect SPMEM31 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 14. "WP_31_2,write protect SPMEM31 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 13. "WP_31_1,write protect SPMEM31 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 12. "WP_31_0,write protect SPMEM31 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 11. "WP_30_3,write protect SPMEM30 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 10. "WP_30_2,write protect SPMEM30- DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 9. "WP_30_1,write protect SPMEM30 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 8. "WP_30_0,write protect SPMEM30 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 7. "WP_29_3,write protect SPMEM29 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 6. "WP_29_2,write protect SPMEM29 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 5. "WP_29_1,write protect SPMEM29 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 4. "WP_29_0,write protect SPMEM29 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 3. "WP_28_3,write protect SPMEM28 - DATA3" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 2. "WP_28_2,write protect SPMEM28 - DATA2" "0: SPMEM is read and write access,1: SPMEM is read only access" newline bitfld.long 0x18 1. "WP_28_1,write protect SPMEM28 - DATA1" "0: SPMEM is read and write access,1: SPMEM is read only access" bitfld.long 0x18 0. "WP_28_0,write protect SPMEM28 - DATA0" "0: SPMEM is read and write access,1: SPMEM is read only access" group.long 0x1544++0x1B line.long 0x0 "LFSS_SPMTERASE1,Scratch Pad Memory Tamper Erase Register 1" bitfld.long 0x0 15. "TE_7_3,tamper erase enable SPMEM7 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 14. "TE_7_2,tamper erase enable SPMEM7 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 13. "TE_7_1,tamper erase enable SPMEM7 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 12. "TE_7_0,tamper erase enable SPMEM7 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 11. "TE_6_3,tamper erase enable SPMEM6 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 10. "TE_6_2,tamper erase enable SPMEM6 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 9. "TE_6_1,tamper erase enable SPMEM6 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 8. "TE_6_0,tamper erase enable SPMEM6 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 7. "TE_5_3,tamper erase enable SPMEM5 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 6. "TE_5_2,tamper erase enable SPMEM5 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 5. "TE_5_1,tamper erase enable SPMEM5 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 4. "TE_5_0,tamper erase enable SPMEM5 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 3. "TE_4_3,tamper erase enable SPMEM4 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 2. "TE_4_2,tamper erase enable SPMEM4 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x0 1. "TE_4_1,tamper erase enable SPMEM4 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x0 0. "TE_4_0,tamper erase enable SPMEM4 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x4 "LFSS_SPMTERASE2,Scratch Pad Memory Tamper Erase Register 2" bitfld.long 0x4 15. "TE_11_3,tamper erase enable SPMEM11 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 14. "TE_11_2,tamper erase enable SPMEM11 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 13. "TE_11_1,tamper erase enable SPMEM11 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 12. "TE_11_0,tamper erase enable SPMEM11 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 11. "TE_10_3,tamper erase enable SPMEM10 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 10. "TE_10_2,tamper erase enable SPMEM10 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 9. "TE_10_1,tamper erase enable SPMEM10 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 8. "TE_10_0,tamper erase enable SPMEM10 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 7. "TE_9_3,tamper erase enable SPMEM9 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 6. "TE_9_2,tamper erase enable SPMEM9 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 5. "TE_9_1,tamper erase enable SPMEM9 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 4. "TE_9_0,tamper erase enable SPMEM9 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 3. "TE_8_3,tamper erase enable SPMEM8 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 2. "TE_8_2,tamper erase enable SPMEM8 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x4 1. "TE_8_1,tamper erase enable SPMEM8 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x4 0. "TE_8_0,tamper erase enable SPMEM8 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x8 "LFSS_SPMTERASE3,Scratch Pad Memory Tamper Erase Register 3" bitfld.long 0x8 15. "TE_15_3,tamper erase enable SPMEM15 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 14. "TE_15_2,tamper erase enable SPMEM15 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 13. "TE_15_1,tamper erase enable SPMEM15 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 12. "TE_15_0,tamper erase enable SPMEM15 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 11. "TE_14_3,tamper erase enable SPMEM14 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 10. "TE_14_2,tamper erase enable SPMEM14 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 9. "TE_14_1,tamper erase enable SPMEM14 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 8. "TE_14_0,tamper erase enable SPMEM14 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 7. "TE_13_3,tamper erase enable SPMEM13 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 6. "TE_13_2,tamper erase enable SPMEM13 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 5. "TE_13_1,tamper erase enable SPMEM13 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 4. "TE_13_0,tamper erase enable SPMEM13 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 3. "TE_12_3,tamper erase enable SPMEM12 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 2. "TE_12_2,tamper erase enable SPMEM12 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x8 1. "TE_12_1,tamper erase enable SPMEM12 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x8 0. "TE_12_0,tamper erase enable SPMEM12 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0xC "LFSS_SPMTERASE4,Scratch Pad Memory Tamper Erase Register 4" bitfld.long 0xC 15. "TE_19_3,tamper erase enable SPMEM19 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 14. "TE_19_2,tamper erase enable SPMEM19 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 13. "TE_19_1,tamper erase enable SPMEM19 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 12. "TE_19_0,tamper erase enable SPMEM19 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 11. "TE_18_3,tamper erase enable SPMEM18 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 10. "TE_18_2,tamper erase enable SPMEM18 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 9. "TE_18_1,tamper erase enable SPMEM18 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 8. "TE_18_0,tamper erase enable SPMEM18 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 7. "TE_17_3,tamper erase enable SPMEM17 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 6. "TE_17_2,tamper erase enable SPMEM17 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 5. "TE_17_1,tamper erase enable SPMEM17 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 4. "TE_17_0,tamper erase enable SPMEM17 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 3. "TE_16_3,tamper erase enable SPMEM16 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 2. "TE_16_2,tamper erase enable SPMEM16 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0xC 1. "TE_16_1,tamper erase enable SPMEM16 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0xC 0. "TE_16_0,tamper erase enable SPMEM16 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x10 "LFSS_SPMTERASE5,Scratch Pad Memory Tamper Erase Register 5" bitfld.long 0x10 15. "TE_23_3,tamper erase enable SPMEM23 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 14. "TE_23_2,tamper erase enable SPMEM23 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 13. "TE_23_1,tamper erase enable SPMEM23 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 12. "TE_23_0,tamper erase enable SPMEM23 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 11. "TE_22_3,tamper erase enable SPMEM22 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 10. "TE_22_2,tamper erase enable SPMEM22 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 9. "TE_22_1,tamper erase enable SPMEM22 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 8. "TE_22_0,tamper erase enable SPMEM22 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 7. "TE_21_3,tamper erase enable SPMEM21 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 6. "TE_21_2,tamper erase enable SPMEM21 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 5. "TE_21_1,tamper erase enable SPMEM21 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 4. "TE_21_0,tamper erase enable SPMEM21 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 3. "TE_20_3,tamper erase enable SPMEM20 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 2. "TE_20_2,tamper erase enable SPMEM20 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x10 1. "TE_20_1,tamper erase enable SPMEM20 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x10 0. "TE_20_0,tamper erase enable SPMEM20 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x14 "LFSS_SPMTERASE6,Scratch Pad Memory Tamper Erase Register 6" bitfld.long 0x14 15. "TE_27_3,tamper erase enable SPMEM27 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 14. "TE_27_2,tamper erase enable SPMEM27 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 13. "TE_27_1,tamper erase enable SPMEM27 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 12. "TE_27_0,tamper erase enable SPMEM27 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 11. "TE_26_3,tamper erase enable SPMEM26 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 10. "TE_26_2,tamper erase enable SPMEM26 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 9. "TE_26_1,tamper erase enable SPMEM26 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 8. "TE_26_0,tamper erase enable SPMEM26 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 7. "TE_25_3,tamper erase enable SPMEM25 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 6. "TE_25_2,tamper erase enable SPMEM25 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 5. "TE_25_1,tamper erase enable SPMEM25 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 4. "TE_25_0,tamper erase enable SPMEM25 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 3. "TE_24_3,tamper erase enable SPMEM24 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 2. "TE_24_2,tamper erase enable SPMEM24 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x14 1. "TE_24_1,tamper erase enable SPMEM24 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x14 0. "TE_24_0,tamper erase enable SPMEM24 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" line.long 0x18 "LFSS_SPMTERASE7,Scratch Pad Memory Tamper Erase Register 7" bitfld.long 0x18 15. "TE_31_3,tamper erase enable SPMEM31 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 14. "TE_31_2,tamper erase enable SPMEM31 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 13. "TE_31_1,tamper erase enable SPMEM31 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 12. "TE_31_0,tamper erase enable SPMEM31 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 11. "TE_30_3,tamper erase enable SPMEM30 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 10. "TE_30_2,tamper erase enable SPMEM30 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 9. "TE_30_1,tamper erase enable SPMEM30 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 8. "TE_30_0,tamper erase enable SPMEM30 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 7. "TE_29_3,tamper erase enable SPMEM29 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 6. "TE_29_2,tamper erase enable SPMEM29 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 5. "TE_29_1,tamper erase enable SPMEM29 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 4. "TE_29_0,tamper erase enable SPMEM29 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 3. "TE_28_3,tamper erase enable SPMEM28 - DATA3" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 2. "TE_28_2,tamper erase enable SPMEM28 - DATA2" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" newline bitfld.long 0x18 1. "TE_28_1,tamper erase enable SPMEM28 - DATA1" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" bitfld.long 0x18 0. "TE_28_0,tamper erase enable SPMEM28 - DATA0" "0: SPMEM is unmodified during tamper event,1: SPMEM will be erased with tamper event" endif tree.end endif sif (cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")) tree "MATHACL (Math Accelerator)" base ad:0x40410000 tree "MATHACL_GPRCM[%s]" base ad:0x40410800 group.long 0x0++0x3 line.long 0x0 "MATHACL_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "MATHACL_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "MATHACL_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40410000 newline group.long 0x1100++0x3 newline line.long 0x0 "MATHACL_CTL,Control Register" hexmask.long.byte 0x0 24.--28. 1. "NUMITER,Number of iterations applicable if the function does the computations iteratively for example sine/cosine/atan2/sqrt." bitfld.long 0x0 22. "SATEN,Saturation enable" "0: Saturation is disabled,1: Saturation is enabled" hexmask.long.byte 0x0 16.--21. 1. "SFACTOR,Scaling factor. In case of SQRT function the input operand needs to be in a range. If not it has to be scaled to 2^(+/-n). This field should be written with the value 'n'." newline hexmask.long.byte 0x0 8.--12. 1. "QVAL,Indicates the fractional bits in the operands ranges from 0 to 31. Applicable to DIV function." bitfld.long 0x0 5. "OPTYPE,Operand type could signed or unsigned. applicable to DIV function." "0: Unsigned operands,1: Signed operands." hexmask.long.byte 0x0 0.--4. 1. "FUNC,ULP_ADCHP Enable Conversions." group.long 0x1118++0xF line.long 0x0 "MATHACL_OP2,Operand 2 register." line.long 0x4 "MATHACL_OP1,Operand 1 register." line.long 0x8 "MATHACL_RES1,Result 1 register." line.long 0xC "MATHACL_RES2,Result 2 register." rgroup.long 0x1130++0x3 line.long 0x0 "MATHACL_STATUS,Status Register" bitfld.long 0x0 8. "BUSY,MATHACL busy bit." "0: Compute has completed.,1: Compute ongoing" bitfld.long 0x0 2.--3. "ERR,Incorrect inputs/outputs." "0: No Error in computation.,1: DIVBY0 error,?,?" bitfld.long 0x0 1. "OVF,Overflow bit for MPY32 SQUARE32 DIV MAC and SAC functions" "0,1" newline bitfld.long 0x0 0. "UF,Underflow Flag" "0: No undreflow error.,1: Underflow error." wgroup.long 0x1140++0x3 line.long 0x0 "MATHACL_STATUSCLR,Status flag clear register" bitfld.long 0x0 2. "CLR_ERR,Write 1 to this bit to clear STATUS.ERR field" "0: Writing 0 has no effect,1: Clear STATUS.ERR" bitfld.long 0x0 1. "CLR_OVF,Write 1 to this bit to clear STATUS.OVF bit" "0: Writing 0 has no effect,1: Clear STATUS.OVF" bitfld.long 0x0 0. "CLR_UF,Write 1 to this bit to clear STATUS.UF bit" "0: Writing 0 has no effect,1: Clear STATUS.UF" tree.end endif sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")) tree "OPA (Operational Aplifier)" base ad:0x0 tree "OPA0" base ad:0x40020000 tree "OPA0_GPRCM[%s]" base ad:0x40020800 group.long 0x0++0x3 line.long 0x0 "OPA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "OPA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "OPA0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40020000 newline group.long 0x1010++0x3 newline line.long 0x0 "OPA0_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x101C++0x3 line.long 0x0 "OPA0_PWRCTL,Power Control" bitfld.long 0x0 0. "AUTO_OFF,When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled." "0: Disable automatic power off function,1: Enable automatic power off function" group.long 0x1100++0xB line.long 0x0 "OPA0_CTL,Control Register" bitfld.long 0x0 0. "ENABLE,OAxn Enable." "0: OAxn OFF,1: OAxn ON" line.long 0x4 "OPA0_CFGBASE,Configuration Base Register" bitfld.long 0x4 2. "RRI,Rail-to-rail input enable. Can only be modified when STAT.BUSY=0" "0: Rail-to-rail input disable.,1: Rail-to-rail input enable." bitfld.long 0x4 0. "GBW,Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0." "0: Low gain bandwidth. See device specific..,1: High gain bandwidth. See device specific.." line.long 0x8 "OPA0_CFG,Configuration Register" bitfld.long 0x8 13.--15. "GAIN,Gain setting. Refer to TRM for enumeration information." "0,1,2,3,4,5,6,7" bitfld.long 0x8 10.--12. "MSEL,MSEL Mux selection." "0: no connect,1: external pin OAn-1,2: VSS,3: DAC12 Output,4: OA[n-1]Rtop,?,?,?" newline bitfld.long 0x8 7.--9. "NSEL,Negative OA input selection." "0: no connect,1: external pin OAn-0,2: external pin OAn-1,3: OA[n+1]Rbot,4: OA[n]Rtap,5: OA[n]Rtop,6: Spare input,?" hexmask.long.byte 0x8 3.--6. 1. "PSEL,Positive OA input selection." newline bitfld.long 0x8 2. "OUTPIN,Enable output pin" "0: Output pin disabled,1: Output pin enabled" bitfld.long 0x8 0.--1. "CHOP,Chopping enable." "0: Chopping disable.,1: Standard chopping enable.,2: Chop with post average on. Requires output to be..,?" rgroup.long 0x1118++0x3 line.long 0x0 "OPA0_STAT,Status Register" bitfld.long 0x0 0. "RDY,OA ready status." "0: OAxn is not ready.,1: OAxn is ready." tree.end tree "OPA1" base ad:0x40022000 tree "OPA1_GPRCM[%s]" base ad:0x40022800 group.long 0x0++0x3 line.long 0x0 "OPA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "OPA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "OPA1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40022000 newline group.long 0x1010++0x3 newline line.long 0x0 "OPA1_CLKOVR,Clock Override" bitfld.long 0x0 1. "RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: Run/ungate functional clock,1: Stop/gate functional clock" bitfld.long 0x0 0. "OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: Override disabled,1: Override enabled" group.long 0x101C++0x3 line.long 0x0 "OPA1_PWRCTL,Power Control" bitfld.long 0x0 0. "AUTO_OFF,When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled." "0: Disable automatic power off function,1: Enable automatic power off function" group.long 0x1100++0xB line.long 0x0 "OPA1_CTL,Control Register" bitfld.long 0x0 0. "ENABLE,OAxn Enable." "0: OAxn OFF,1: OAxn ON" line.long 0x4 "OPA1_CFGBASE,Configuration Base Register" bitfld.long 0x4 2. "RRI,Rail-to-rail input enable. Can only be modified when STAT.BUSY=0" "0: Rail-to-rail input disable.,1: Rail-to-rail input enable." bitfld.long 0x4 0. "GBW,Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0." "0: Low gain bandwidth. See device specific..,1: High gain bandwidth. See device specific.." line.long 0x8 "OPA1_CFG,Configuration Register" bitfld.long 0x8 13.--15. "GAIN,Gain setting. Refer to TRM for enumeration information." "0,1,2,3,4,5,6,7" bitfld.long 0x8 10.--12. "MSEL,MSEL Mux selection." "0: no connect,1: external pin OAn-1,2: VSS,3: DAC12 Output,4: OA[n-1]Rtop,?,?,?" newline bitfld.long 0x8 7.--9. "NSEL,Negative OA input selection." "0: no connect,1: external pin OAn-0,2: external pin OAn-1,3: OA[n+1]Rbot,4: OA[n]Rtap,5: OA[n]Rtop,6: Spare input,?" hexmask.long.byte 0x8 3.--6. 1. "PSEL,Positive OA input selection." newline bitfld.long 0x8 2. "OUTPIN,Enable output pin" "0: Output pin disabled,1: Output pin enabled" bitfld.long 0x8 0.--1. "CHOP,Chopping enable." "0: Chopping disable.,1: Standard chopping enable.,2: Chop with post average on. Requires output to be..,?" rgroup.long 0x1118++0x3 line.long 0x0 "OPA1_STAT,Status Register" bitfld.long 0x0 0. "RDY,OA ready status." "0: OAxn is not ready.,1: OAxn is ready." tree.end tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "RTC (Real Time Clock)" base ad:0x40094000 group.long 0x444++0x3 line.long 0x0 "RTC_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." tree "RTC_GPRCM[%s]" base ad:0x40094800 group.long 0x0++0x3 line.long 0x0 "RTC_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "RTC_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "RTC_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "RTC_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40094000 newline rgroup.long 0x1004++0x3 newline line.long 0x0 "RTC_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: LFCLK is disabled as clock source,1: LFCLK is enabled as clock source" tree "RTC_INT_EVENT0[%s]" base ad:0x40095020 rgroup.long 0x0++0x3 line.long 0x0 "RTC_INT_EVENT0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "RTC_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 5. "RT1PS,Enable Prescaler-1 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,Enable Prescaler-0 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "RTCA2,Enable Alarm-2 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "RTCA1,Enable Alarm-1 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "RTCTEV,Enable Time-Event interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,Enable RTC-Ready interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "RTC_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 5. "RT1PS,Raw Prescaler-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "RT0PS,Raw Prescaler-0 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "RTCA2,Raw Alarm-2 interrupts status" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "RTCA1,Raw Alarm-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "RTCTEV,Raw Time-Event interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTCRDY,Raw RTC-Ready interrupts status" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "RTC_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 5. "RT1PS,Masked Prescaler-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "RT0PS,Masked Prescaler-0 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "RTCA2,Masked Alarm-2 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "RTCA1,Masked Alarm-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "RTCTEV,Masked Time-Event interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTCRDY,Masked RTC-Ready interrupt status" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "RTC_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 5. "RT1PS,Set Prescaler-1 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "RT0PS,Set Prescaler-0 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RTCA2,Set Alarm-2 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "RTCA1,Set Alarm-1 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "RTCTEV,Set Time-Event interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTCRDY,Set RTC-Ready interrupt" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "RTC_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 5. "RT1PS,Clear Prescaler-1 interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "RT0PS,Clear Prescaler-0 interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RTCA2,Clear Alarm-2 interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "RTCA1,Clear Alarm-1 interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "RTCTEV,Clear Time-Event interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTCRDY,Clear RTC-Ready interrupt" "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "RTC_INT_EVENT1[%s]" base ad:0x40095050 rgroup.long 0x0++0x3 line.long 0x0 "RTC_INT_EVENT1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "RTC_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 5. "RT1PS,Enable Prescaler-1 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,Enable Prescaler-0 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "RTCA2,Enable Alarm-2 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "RTCA1,Enable Alarm-1 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "RTCTEV,Enable Time-Event interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,Enable RTC-Ready interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "RTC_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 5. "RT1PS,Raw Prescaler-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "RT0PS,Raw Prescaler-0 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "RTCA2,Raw Alarm-2 interrupts status" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "RTCA1,Raw Alarm-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "RTCTEV,Raw Time-Event interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTCRDY,Raw RTC-Ready interrupts status" "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "RTC_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 5. "RT1PS,Masked Prescaler-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "RT0PS,Masked Prescaler-0 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "RTCA2,Masked Alarm-2 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "RTCA1,Masked Alarm-1 interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "RTCTEV,Masked Time-Event interrupt status" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTCRDY,Masked RTC-Ready interrupt status" "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "RTC_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 5. "RT1PS,Set Prescaler-1 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "RT0PS,Set Prescaler-0 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RTCA2,Set Alarm-2 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "RTCA1,Set Alarm-1 interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "RTCTEV,Set Time-Event interrupt" "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTCRDY,Set RTC-Ready interrupt" "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "RTC_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 5. "RT1PS,Clear Prescaler-1 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "RT0PS,Clear Prescaler-0 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "RTCA2,Clear Alarm-2 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "RTCA1,Clear Alarm-1 interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "RTCTEV,Clear Time-Event interrupt" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTCRDY,Clear RTC-Ready interrupt" "0: Clear Interrupt Mask,1: Clear Interrupt" tree.end base ad:0x40094000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "RTC_EVT_MODE,Event Mode" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode 1 select" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode 0 select" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "RTC_DESC,RTC Descriptor Register" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identifier. This ID is unique for each module. 0x0911 = Module ID of the RTC Module" hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences." newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instantiated version. Describes which instance of the module accessed." hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet)" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet)" group.long 0x1100++0xB line.long 0x0 "RTC_CLKCTL,RTC Clock Control Register" bitfld.long 0x0 31. "MODCLKEN,This bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module." "0: 32kHz clock is not supplied to the RTC.,1: 32kHz clock is supplied to the RTC." line.long 0x4 "RTC_DBGCTL,RTC Module Debug Control Register" bitfld.long 0x4 1. "DBGINT,Debug Interrupt Enable." "0: Interrupts of the module will not be captured..,1: Interrupts are enabled in debug mode. Interrupt.." bitfld.long 0x4 0. "DBGRUN,Debug Run." "0: Counter is halted if CPU is in debug state.,1: Continue to operate normally ignoring the debug.." line.long 0x8 "RTC_CTL,RTC Control Register" bitfld.long 0x8 7. "RTCBCD,Real-time clock BCD select. Selects BCD counting for real-time clock." "0: Binary code selected,1: Binary coded decimal (BCD) code selected" bitfld.long 0x8 0.--1. "RTCTEVTX,Real-time clock time event." "0: Minute changed.,1: Hour changed.,2: Every day at midnight (00:00).,3: Every day at noon (12:00)." rgroup.long 0x110C++0x3 line.long 0x0 "RTC_STA,RTC Status Register" bitfld.long 0x0 2. "RTCTCOK,Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not." "0: Write to RTCTCMPx is unsuccessful,1: Write to RTCTCMPx is successful" bitfld.long 0x0 1. "RTCTCRDY,Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset." "0: Real-time clock temperature compensation not ready,1: Real-time clock temperature compensation ready" newline bitfld.long 0x0 0. "RTCRDY,Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading." "0: RTC time values in transition,1: RTC time values safe for reading" group.long 0x1110++0x3B line.long 0x0 "RTC_CAL,RTC Clock Offset Calibration Register" bitfld.long 0x0 16.--17. "RTCCALFX,Real-time clock calibration frequency. Selects frequency output to RTC_OUT pin for calibration measurement. The corresponding port must be configured for the peripheral module function." "0: No frequency output to RTC_OUT pin,1: 512 Hz,2: 256 Hz,3: 1 Hz" bitfld.long 0x0 15. "RTCOCALS,Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration." "0: Down calibration. Frequency adjusted down.,1: Up calibration. Frequency adjusted up." newline hexmask.long.byte 0x0 0.--7. 1. "RTCOCALX,Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be.." line.long 0x4 "RTC_TCMP,RTC Temperature Compensation Register" bitfld.long 0x4 15. "RTCTCMPS,Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation." "0: Down calibration. Frequency adjusted down.,1: Up calibration. Frequency adjusted up." hexmask.long.byte 0x4 0.--7. 1. "RTCTCMPX,Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum effective.." line.long 0x8 "RTC_SEC,RTC Seconds Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x8 12.--14. "SECHIGHBCD,Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--11. 1. "SECLOWBCD,Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x8 0.--5. 1. "SECBIN,Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0xC "RTC_MIN,RTC Minutes Register - Calendar Mode With Binary / BCD Format" bitfld.long 0xC 12.--14. "MINHIGHBCD,Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 8.--11. 1. "MINLOWBCD,Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0xC 0.--5. 1. "MINBIN,Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x10 "RTC_HOUR,RTC Hours Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x10 12.--13. "HOURHIGHBCD,Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "HOURLOWBCD,Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x10 0.--4. 1. "HOURBIN,Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x14 "RTC_DAY,RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x14 20.--21. "DOMHIGHBCD,Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" hexmask.long.byte 0x14 16.--19. 1. "DOMLOWBCD,Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x14 8.--12. 1. "DOMBIN,Day of month Binary (1 to 28 29 30 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0x14 0.--2. "DOW,Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x18 "RTC_MON,RTC Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x18 12. "MONHIGHBCD,Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1" hexmask.long.byte 0x18 8.--11. 1. "MONLOWBCD,Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x18 0.--3. 1. "MONBIN,Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x1C "RTC_YEAR,RTC Year Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x1C 28.--30. "CENTHIGHBCD,Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 24.--27. 1. "CENTLOWBCD,Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x1C 20.--23. 1. "DECADEBCD,Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." hexmask.long.byte 0x1C 16.--19. 1. "YEARLOWESTBCD,Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." newline hexmask.long.byte 0x1C 8.--11. 1. "YEARHIGHBIN,Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0." hexmask.long.byte 0x1C 0.--7. 1. "YEARLOWBIN,Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x20 "RTC_A1MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x20 15. "AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x20 12.--14. "AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 8.--11. 1. "AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x20 7. "AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x20 0.--5. 1. "AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x24 "RTC_A1HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x24 15. "AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x24 12.--13. "AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3" newline hexmask.long.byte 0x24 8.--11. 1. "AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x24 7. "AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x24 0.--4. 1. "AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x28 "RTC_A1DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x28 23. "ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x28 20.--21. "ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" newline hexmask.long.byte 0x28 16.--19. 1. "ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x28 15. "ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x28 8.--12. 1. "ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0x28 7. "ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: Alarm disabled,1: Alarm enabled" newline bitfld.long 0x28 0.--2. "ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x2C "RTC_A2MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x2C 15. "AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x2C 12.--14. "AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 8.--11. 1. "AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x2C 7. "AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x2C 0.--5. 1. "AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x30 "RTC_A2HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x30 15. "AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x30 12.--13. "AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3" newline hexmask.long.byte 0x30 8.--11. 1. "AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x30 7. "AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x30 0.--4. 1. "AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0." line.long 0x34 "RTC_A2DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format" bitfld.long 0x34 23. "ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" bitfld.long 0x34 20.--21. "ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3" newline hexmask.long.byte 0x34 16.--19. 1. "ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0." bitfld.long 0x34 15. "ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: Alarm disabled,1: Alarm enabled" newline hexmask.long.byte 0x34 8.--12. 1. "ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0." bitfld.long 0x34 7. "ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: Alarm disabled,1: Alarm enabled" newline bitfld.long 0x34 0.--2. "ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7" line.long 0x38 "RTC_PSCTL,RTC Prescale Timer 0/1 Control Register" bitfld.long 0x38 18.--20. "RT1IP,Prescale timer 1 interrupt interval" "0: Divide by 2 - 15.6 millisecond interval,1: Divide by 4 - 31.2 millisecond interval,2: Divide by 8 - 62.5 millisecond interval,3: Divide by 16 - 125 millisecond interval,4: Divide by 32 - 250 millisecond interval,5: Divide by 64 - 500 millisecond interval,6: Divide by 128 - 1 second interval,7: Divide by 256 - 2 second interval" bitfld.long 0x38 2.--4. "RT0IP,Prescale timer 0 interrupt interval" "?,?,2: Divide by 8 - 244 microsecond interval,3: Divide by 16 - 488 microsecond interval,4: Divide by 32 - 976 microsecond interval,5: Divide by 64 - 1.95 millisecond interval,6: Divide by 128 - 3.90 millisecond interval,7: Divide by 256 - 7.81 millisecond interval" tree.end endif tree "SPI (Serial Peripheral Interface)" base ad:0x0 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) tree "SPI0" base ad:0x40468000 tree "SPI0_GPRCM[%s]" base ad:0x40468800 group.long 0x0++0x3 line.long 0x0 "SPI0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40468000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "SPI0_INT_EVENT0[%s]" base ad:0x40469020 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40468000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "SPI0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "SPI0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0xF line.long 0x0 "SPI0_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI0_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" newline bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" newline bitfld.long 0x4 3. "POD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." bitfld.long 0x4 2. "CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" newline bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI0_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI0_IFLS,Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI0_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI0_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI0_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "SPI1" base ad:0x4046A000 tree "SPI1_GPRCM[%s]" base ad:0x4046A800 group.long 0x0++0x3 line.long 0x0 "SPI1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4046A000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "SPI1_INT_EVENT0[%s]" base ad:0x4046B020 rgroup.long 0x0++0x3 line.long 0x0 "SPI1_INT_EVENT0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI1_INT_EVENT1[%s]" base ad:0x4046B050 rgroup.long 0x0++0x3 line.long 0x0 "SPI1_INT_EVENT1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out Event." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "SPI1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "SPI1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "SPI1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "SPI1_INT_EVENT2[%s]" base ad:0x4046B080 rgroup.long 0x0++0x3 line.long 0x0 "SPI1_INT_EVENT2_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 4. "TX,Transmit FIFO event:" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 4. "TX,Masked Transmit FIFO event" "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x4046A000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "SPI1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "SPI1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0xF line.long 0x0 "SPI1_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI1_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 7. "PBS,Parity Bit Select" "0: Bit 0 is used for Parity,1: Bit 1 is used for Parity Bit 0 is ignored" newline bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" newline bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" bitfld.long 0x4 3. "SOD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." newline bitfld.long 0x4 2. "MS,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" newline bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI1_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI1_IFLS,UART Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI1_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI1_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI1_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")) tree "SPI0" base ad:0x40468000 tree "SPI0_GPRCM[%s]" base ad:0x40468800 group.long 0x0++0x3 line.long 0x0 "SPI0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40468000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "SPI0_INT_EVENT0[%s]" base ad:0x40469020 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_INT_EVENT0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI0_INT_EVENT1[%s]" base ad:0x40469050 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_INT_EVENT1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out Event." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "SPI0_INT_EVENT2[%s]" base ad:0x40469080 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_INT_EVENT2_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 4. "TX,Transmit FIFO event:" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 4. "TX,Masked Transmit FIFO event" "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40468000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "SPI0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "SPI0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0xF line.long 0x0 "SPI0_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI0_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 7. "PBS,Parity Bit Select" "0: Bit 0 is used for Parity,1: Bit 1 is used for Parity Bit 0 is ignored" newline bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" newline bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" bitfld.long 0x4 3. "SOD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." newline bitfld.long 0x4 2. "MS,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" newline bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI0_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI0_IFLS,UART Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI0_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI0_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI0_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "SPI0" base ad:0x40468000 tree "SPI0_CPU_INT[%s]" base ad:0x40469020 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_CPU_INT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI0_DMA_TRIG_RX[%s]" base ad:0x40469050 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_DMA_TRIG_RX_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out Event." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "SPI0_DMA_TRIG_TX[%s]" base ad:0x40469080 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_DMA_TRIG_TX_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 4. "TX,Transmit FIFO event:" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 4. "TX,Masked Transmit FIFO event" "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI0_GPRCM[%s]" base ad:0x40468800 group.long 0x0++0x3 line.long 0x0 "SPI0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40468000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." rgroup.long 0x10E0++0x3 line.long 0x0 "SPI0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "SPI0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0xF line.long 0x0 "SPI0_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI0_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" newline bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" newline bitfld.long 0x4 3. "POD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." bitfld.long 0x4 2. "CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" newline bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI0_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI0_IFLS,Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI0_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI0_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI0_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "SPI1" base ad:0x4046A000 tree "SPI1_CPU_INT[%s]" base ad:0x4046B020 rgroup.long 0x0++0x3 line.long 0x0 "SPI1_CPU_INT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI1_DMA_TRIG_RX[%s]" base ad:0x4046B050 rgroup.long 0x0++0x3 line.long 0x0 "SPI1_DMA_TRIG_RX_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI1_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI1_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out Event." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "SPI1_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "SPI1_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "SPI1_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "SPI1_DMA_TRIG_TX[%s]" base ad:0x4046B080 rgroup.long 0x0++0x3 line.long 0x0 "SPI1_DMA_TRIG_TX_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI1_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI1_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 4. "TX,Transmit FIFO event:" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI1_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 4. "TX,Masked Transmit FIFO event" "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI1_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI1_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI1_GPRCM[%s]" base ad:0x4046A800 group.long 0x0++0x3 line.long 0x0 "SPI1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4046A000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." rgroup.long 0x10E0++0x3 line.long 0x0 "SPI1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "SPI1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0xF line.long 0x0 "SPI1_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI1_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" newline bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" newline bitfld.long 0x4 3. "POD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." bitfld.long 0x4 2. "CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" newline bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI1_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI1_IFLS,Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI1_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI1_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI1_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif sif (cpuis("MSPM0G151*")||cpuis("MSPM0G351*")) tree "SPI2" base ad:0x4046C000 tree "SPI2_CPU_INT[%s]" base ad:0x4046D020 rgroup.long 0x0++0x3 line.long 0x0 "SPI2_CPU_INT_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI2_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI2_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI2_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI2_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI2_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI2_DMA_TRIG_RX[%s]" base ad:0x4046D050 rgroup.long 0x0++0x3 line.long 0x0 "SPI2_DMA_TRIG_RX_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI2_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI2_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out Event." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "SPI2_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "SPI2_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "SPI2_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "SPI2_DMA_TRIG_TX[%s]" base ad:0x4046D080 rgroup.long 0x0++0x3 line.long 0x0 "SPI2_DMA_TRIG_TX_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI2_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI2_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 4. "TX,Transmit FIFO event:" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI2_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 4. "TX,Masked Transmit FIFO event" "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI2_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI2_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI2_GPRCM[%s]" base ad:0x4046C800 group.long 0x0++0x3 line.long 0x0 "SPI2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4046C000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." rgroup.long 0x10E0++0x3 line.long 0x0 "SPI2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "SPI2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0xF line.long 0x0 "SPI2_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI2_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" newline bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" newline bitfld.long 0x4 3. "POD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." bitfld.long 0x4 2. "CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" newline bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI2_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI2_IFLS,Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI2_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI2_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI2_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")) tree "SPI0" base ad:0x40468000 tree "SPI0_GPRCM[%s]" base ad:0x40468800 group.long 0x0++0x3 line.long 0x0 "SPI0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "SPI0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "SPI0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: Not block async clock request,1: Block async clock request" rgroup.long 0x14++0x3 line.long 0x0 "SPI0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40468000 newline group.long 0x1000++0x7 newline line.long 0x0 "SPI0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" line.long 0x4 "SPI0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x4 3. "SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x4 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x4 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "SPI0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "SPI0_INT_EVENT0[%s]" base ad:0x40469020 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_INT_EVENT0_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt Mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "IDLE,SPI Idle event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,Enable SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Parity error event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 1. "PER,Parity error event: this bit is set if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXFULL,RX FIFO Full Interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 9. "TXFIFO_UNF,TX FIFO underflow interrupt" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 8. "DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 7. "DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 6. "IDLE,Masked SPI IDLE mode event." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 5. "TXEMPTY,Masked Transmit FIFO Empty event." "0: Interrupt did not occur,1: Interrupt occurred" newline bitfld.long 0x0 4. "TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 3. "RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,Masked SPI Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Masked Parity error event: this bit if a Parity error has been detected" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 0. "RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 10. "RXFULL,Set RX FIFO Full Event" "0: Writing has no effect,1: Set Interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Set TX FIFO Underflow Event" "0: Writing has no effect,1: Set interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Set DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Set DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "IDLE,Set SPI IDLE mode event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 5. "TXEMPTY,Set Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Set Parity error event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Set RXFIFO overflow event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXFULL,Clear RX FIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 9. "TXFIFO_UNF,Clear TXFIFO underflow event" "0: Writing has no effect,1: Clear interrupt" bitfld.long 0x0 8. "DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "IDLE,Clear SPI IDLE mode event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 5. "TXEMPTY,Clear Transmit FIFO Empty event." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out Event." "0: Writing 0 has no effect,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "PER,Clear Parity error event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RXFIFO_OVF,Clear RXFIFO overflow event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "SPI0_INT_EVENT1[%s]" base ad:0x40469050 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_INT_EVENT1_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out Event." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 3. "RX,Receive FIFO event mask." "0: Interrupt did not occur,1: Interrupt occurred" bitfld.long 0x0 2. "RTOUT,SPI Receive Time-Out event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 3. "RX,Set Receive FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "RTOUT,Set SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 3. "RX,Clear Receive FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "RTOUT,Clear SPI Receive Time-Out event." "0: Writing 0 has no effect,1: Set Interrupt Mask" tree.end tree "SPI0_INT_EVENT2[%s]" base ad:0x40469080 rgroup.long 0x0++0x3 line.long 0x0 "SPI0_INT_EVENT2_IIDX,Interrupt Index Register" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "SPI0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 4. "TX,Transmit FIFO event mask." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "SPI0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 4. "TX,Transmit FIFO event:" "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "SPI0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 4. "TX,Masked Transmit FIFO event" "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "SPI0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 4. "TX,Set Transmit FIFO event." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "SPI0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 4. "TX,Clear Transmit FIFO event." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40468000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "SPI0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" group.long 0x1100++0xF line.long 0x0 "SPI0_CTL0,SPI control register 0" bitfld.long 0x0 14. "CSCLR,Clear shift register counter on CS inactive" "0: Disable automatic clear of shift register when..,1: Enable automatic clear of shift register when CS.." bitfld.long 0x0 12.--13. "CSSEL,Select the CS line to control on data transfer" "0: CS line select: 0,1: CS line select: 1,2: CS line select: 2,3: CS line select: 3" newline bitfld.long 0x0 9. "SPH,CLKOUT phase (Motorola SPI frame format only)" "0: Data is captured on the first clock edge..,1: Data is captured on the second clock edge.." bitfld.long 0x0 8. "SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: SPI produces a steady state LOW value on the..,1: SPI produces a steady state HIGH value on the.." newline bitfld.long 0x0 7. "PACKEN,Packing Enable." "0: Packing feature disabled,1: Packing feature enabled" bitfld.long 0x0 5.--6. "FRF,Frame format Select" "0: Motorola SPI frame format (3 wire mode),1: Motorola SPI frame format (4 wire mode),2: TI synchronous serial frame format,3: National Microwire frame format" newline hexmask.long.byte 0x0 0.--4. 1. "DSS,Data Size Select." line.long 0x4 "SPI0_CTL1,SPI control register 1" hexmask.long.byte 0x4 24.--29. 1. "RXTIMEOUT,Receive Timeout (only for Peripheral mode)" hexmask.long.byte 0x4 16.--23. 1. "REPEATTX,Counter to repeat last transfer" newline hexmask.long.byte 0x4 12.--15. 1. "CDMODE,Command/Data Mode Value" bitfld.long 0x4 11. "CDENABLE,Command/Data Mode enable" "0: CS3 is used for Chip Select,1: CS3 is used as CD signal" newline bitfld.long 0x4 8. "PTEN,Parity transmit enable" "0: Parity transmission is disabled,1: Parity transmission is enabled" bitfld.long 0x4 7. "PBS,Parity Bit Select" "0: Bit 0 is used for Parity,1: Bit 1 is used for Parity Bit 0 is ignored" newline bitfld.long 0x4 6. "PES,Even Parity Select" "0: Odd Parity mode,1: Even Parity mode" bitfld.long 0x4 5. "PREN,Parity receive enable" "0: Disable Parity receive function,1: Enable Parity receive function" newline bitfld.long 0x4 4. "MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: LSB first,1: MSB first" bitfld.long 0x4 3. "SOD,Peripheral-mode: Data output disabled" "0: SPI can drive the MISO output in peripheral mode.,1: SPI cannot drive the MISO output in peripheral.." newline bitfld.long 0x4 2. "MS,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: Select Peripheral mode,1: Select Controller Mode" bitfld.long 0x4 1. "LBM,Loop back mode" "0: Disable loopback mode,1: Enable loopback mode" newline bitfld.long 0x4 0. "ENABLE,SPI enable" "0: Disable module function,1: Enable module function" line.long 0x8 "SPI0_CLKCTL,Clock prescaler and divider register." hexmask.long.byte 0x8 28.--31. 1. "DSAMPLE,Delayed sampling value." hexmask.long.word 0x8 0.--9. 1. "SCR,Serial clock divider:" line.long 0xC "SPI0_IFLS,UART Interrupt FIFO Level Select Register" bitfld.long 0xC 3.--5. "RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: Reserved,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: Reserved,5: RX FIFO is full,6: Reserved,7: Trigger when RX FIFO contains >= 1 frame" bitfld.long 0xC 0.--2. "TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: Reserved,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,4: Reserved,5: TX FIFO is empty,6: Reserved,7: Trigger when TX FIFO has >= 1 frame free Should.." rgroup.long 0x1110++0x3 line.long 0x0 "SPI0_STAT,Status Register" bitfld.long 0x0 4. "BUSY,Busy" "0: SPI is in idle mode.,1: SPI is currently transmitting and/or receiving.." bitfld.long 0x0 3. "RNF,Receive FIFO not full" "0: Receive FIFO is full.,1: Receive FIFO is not full." newline bitfld.long 0x0 2. "RFE,Receive FIFO empty." "0: Receive FIFO is not empty.,1: Receive FIFO is empty." bitfld.long 0x0 1. "TNF,Transmit FIFO not full" "0: Transmit FIFO is full.,1: Transmit FIFO is not full." newline bitfld.long 0x0 0. "TFE,Transmit FIFO empty." "0: Transmit FIFO is not empty.,1: Transmit FIFO is empty." rgroup.long 0x1130++0x3 line.long 0x0 "SPI0_RXDATA,RXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Received Data" group.long 0x1140++0x3 line.long 0x0 "SPI0_TXDATA,TXDATA Register" hexmask.long.word 0x0 0.--15. 1. "DATA,Transmit Data" tree.end endif tree.end tree "SYSCTL (System Controller)" base ad:0x400AF000 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) tree "SYSCTL_PINCM[%s]" base ad:0x400AF004 group.long 0x0++0x17 line.long 0x0 "SYSCTL_CLK_OUT,CLK_OUT" bitfld.long 0x0 30. "GFLT,Glitch Filter Enable" "0: No internal glitch filter,1: Use internal glitch filter" bitfld.long 0x0 29. "SLEW,Reserved Slew Rate Control" "0: No Slew Rate Control,1: Use Slew Rate Control" newline bitfld.long 0x0 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x0 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x0 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x0 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x0 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x0 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x0 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x0 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x0 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x0 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x0 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x0 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." line.long 0x4 "SYSCTL_BSL_INVOKE,BSL Invoke" bitfld.long 0x4 30. "GFLT,Glitch Filter Enable" "0: No internal glitch filter,1: Use internal glitch filter" bitfld.long 0x4 29. "SLEW,Reserved Slew Rate Control" "0: No Slew Rate Control,1: Use Slew Rate Control" newline bitfld.long 0x4 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x4 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x4 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x4 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x4 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x4 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x4 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x4 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x4 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x4 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x4 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x4 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." line.long 0x8 "SYSCTL_LFCLKIN,BSL Invoke" bitfld.long 0x8 30. "GFLT,Glitch Filter Enable" "0: No internal glitch filter,1: Use internal glitch filter" bitfld.long 0x8 29. "SLEW,Reserved Slew Rate Control" "0: No Slew Rate Control,1: Use Slew Rate Control" newline bitfld.long 0x8 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x8 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x8 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x8 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x8 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x8 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x8 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x8 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x8 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x8 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x8 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x8 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." line.long 0xC "SYSCTL_HFCLKIN,BSL Invoke" bitfld.long 0xC 30. "GFLT,Glitch Filter Enable" "0: No internal glitch filter,1: Use internal glitch filter" bitfld.long 0xC 29. "SLEW,Reserved Slew Rate Control" "0: No Slew Rate Control,1: Use Slew Rate Control" newline bitfld.long 0xC 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0xC 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0xC 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0xC 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0xC 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0xC 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0xC 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0xC 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0xC 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0xC 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0xC 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0xC 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." line.long 0x10 "SYSCTL_FCC_IN,BSL Invoke" bitfld.long 0x10 30. "GFLT,Glitch Filter Enable" "0: No internal glitch filter,1: Use internal glitch filter" bitfld.long 0x10 29. "SLEW,Reserved Slew Rate Control" "0: No Slew Rate Control,1: Use Slew Rate Control" newline bitfld.long 0x10 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x10 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x10 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x10 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x10 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x10 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x10 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x10 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x10 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x10 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x10 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x10 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." line.long 0x14 "SYSCTL_BEEPER,BEEPER" bitfld.long 0x14 30. "GFLT,Glitch Filter Enable" "0: No internal glitch filter,1: Use internal glitch filter" bitfld.long 0x14 29. "SLEW,Reserved Slew Rate Control" "0: No Slew Rate Control,1: Use Slew Rate Control" newline bitfld.long 0x14 28. "WCOMP,Wake up compare value" "0: Match 0 will wake,1: Match 1 will wake" bitfld.long 0x14 27. "WUEN,Wake up enable" "0: Wake up not enabled,1: Wake up enabled" newline bitfld.long 0x14 26. "INV,Invert digital input/output relative to peripheral/GPIO" "0: Input and output are non-inverted,1: Input and output are inverted" bitfld.long 0x14 25. "HIGHZ1,High-Z instead of high output" "0: Pin can be driven high,1: Pin is tri-stated instead of driven high" newline bitfld.long 0x14 24. "HIGHZ0,High-Z instead of low output" "0: Pin can be driven low,1: Pin is tri-stated instead of driven low" bitfld.long 0x14 20.--22. "DRV,Drive strength options" "0: Lowest drive strength,1: Drive strength 2/8,2: Drive strength 3/8,3: Drive strength 4/8,4: Drive strength 5/8,5: Drive strength 6/8,6: Drive strength 7/8,7: Highest drive strength" newline bitfld.long 0x14 19. "HYSTEN,Hysteresis enable" "0: No hysteresis,1: Hysteresis on" bitfld.long 0x14 18. "INENA,Input enable" "0: Inputs 0 to connected core,1: Inputs IO pad value to connected core" newline bitfld.long 0x14 17. "PIPU,Pull up enable" "0: No pull up,1: Pull up" bitfld.long 0x14 16. "PIPD,Pull down enable" "0: No pull down,1: Pull down" newline bitfld.long 0x14 14.--15. "GSTATE,GPIO Channel State" "0: G-Channel is in Unassigned State,1: G-Channel is in Handover State,2: G-Channel is in Connected State and not Locked..,3: G-Channel is in Connected State and Locked (That.." bitfld.long 0x14 6.--7. "PSTATE,Peripheral-Analog Channel State" "0: P-Channel is in Unassigned State,1: P-Channel is in Handover State,2: P-Channel is in Connected State and not Locked..,3: P-Channel is in Connected State and Locked (That.." tree.end newline rgroup.long 0x1168++0x3 newline line.long 0x0 "SYSCTL_SOCLOCK_FLBANKSWAP,Flash Bank Swap" bitfld.long 0x0 0. "USEUPPER,1: SWAP upper banks to lower 0: Normal Memory Map" "0: Normal Memory Map,1: SWAP upper banks to lower" group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SYSMEMWEPROT,SRAM Write Protect" group.long 0x2000++0x7 line.long 0x0 "SYSCTL_LIFECYCLE,Device Lifecycle" hexmask.long.byte 0x0 0.--7. 1. "VALUE,Device Lifecycle set by BOOTCODE READY=0x69(105) ATTEST=0x55(85) PREPROBE=0x96(150)" line.long 0x4 "SYSCTL_BOOTCFG,Configuration of CPURESET Vector" bitfld.long 0x4 16. "BSLREQ,0: Full Bringup 1: TRIM already loaded requesting BSL" "0: Full Bringup,1: TRIM already loaded" newline bitfld.long 0x4 8. "WAITINRESET,0: Normal operation 1: CPU held in reset for debugger to control release" "0: Normal operation,1: CPU held in reset for debugger to control release" newline bitfld.long 0x4 4. "NONMAINWEPROT,0: NonMain Flash area can be modified 1: Program-Erase will be ignored" "0: NonMain Flash area can be modified,1: Program-Erase will be ignored" bitfld.long 0x4 0.--1. "STARTVEC,Reset Vector target location at next reset" "0: Reset to BOOTCODE,1: Reset to BOOTLOADER,2: Reset to FLASH 0x0,3: Reset to SRAM 0x0" wgroup.long 0x2008++0xB line.long 0x0 "SYSCTL_BOOTDONE,BOOTCODE PASS" bitfld.long 0x0 0. "PASS,BOOTCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: BOOTCODE PASS" line.long 0x4 "SYSCTL_BOOTTIMEOUT,BOOT TIMEOUT Control" bitfld.long 0x4 1. "STOP,BOOTCODE writes 1 for STOPPING BOOT TIMEOUT Counter" "?,1: STOP Bootcode Timeout Counter" bitfld.long 0x4 0. "PET,BOOTCODE writes 1 for reloading BOOT TIMEOUT Counter" "?,1: Restart Bootcode Timeout Counter" line.long 0x8 "SYSCTL_BCTRIMUNLOCK,BootCode TRIM Unlock" rgroup.long 0x2014++0x3 line.long 0x0 "SYSCTL_INFRASTATUS,Infrastructure Status" bitfld.long 0x0 24. "READY1T,Flash 1T Read mode is available" "0,1" bitfld.long 0x0 16. "SRAMREPAIRDONE,SRAM repair is completed or not supported on this SOC" "0,1" newline bitfld.long 0x0 8. "TRIMUNLOCK,TRIM MMRs are UNLOCKED" "0,1" bitfld.long 0x0 0. "DMATRIMSIGFAIL,DMA TRIM signiture fail" "0,1" group.long 0x2018++0x3 line.long 0x0 "SYSCTL_BOOTDIAG,8 bit boot diagnostic to Debugss" hexmask.long.byte 0x0 0.--7. 1. "DATA,8 bit boot diagnostic to Debugss" rgroup.long 0x201C++0x3 line.long 0x0 "SYSCTL_INFRASTATUS1,Infrastructure Status 2" bitfld.long 0x0 0. "CRPAD,Customer Return Pad" "0,1" group.long 0x2020++0x7 line.long 0x0 "SYSCTL_FWEPROTMAINA,1 Sector Write-Erase per bit starting at address 0x0 of flash" line.long 0x4 "SYSCTL_FWEPROTMAINB0,8xSector Write-Erase per bit starting at address 0x0 of flash" hexmask.long.word 0x4 0.--15. 1. "DATA,8xSector Write Erase protection 1: prohibits write-erase 0: allows" group.long 0x2040++0x3 line.long 0x0 "SYSCTL_JTAGUSERCODE,JTAG USERCODE" wgroup.long 0x2400++0x3 line.long 0x0 "SYSCTL_DMATRIMUNLOCK,DMA TRIM Unlock" group.long 0x2404++0xAF line.long 0x0 "SYSCTL_SYSOSCTRIMBASE,SYSOSC Trim Values for frequency when change from disable to enable. generally 32MHz" bitfld.long 0x0 31. "TRIMVALID,TRIM Data Valid- used to trigger FSM" "0,1" bitfld.long 0x0 28. "ALLOWTURBO,SYSOSC 48MHz (TURBO) TI trim can be used" "0,1" newline bitfld.long 0x0 27. "VCTRLSEL,VCTRL SEL used potentially needed for FCL mode. Default 0" "0,1" bitfld.long 0x0 24.--26. "ILDO,ILDO TRIM -- Only 1 value Not frequency dependent" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "RESFINE,Resister Coarse TRIM - Changes per frequency target" hexmask.long.byte 0x0 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" newline bitfld.long 0x0 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "IBIAS,IBIAS TRIM - Only 1 value not frequency dependent" line.long 0x4 "SYSCTL_PMUTRIM0,PMU TRIM 0" hexmask.long.word 0x4 0.--9. 1. "DATA,SEE PMU definition for usage" line.long 0x8 "SYSCTL_PMUTRIM1,PMU TRIM 1" hexmask.long.word 0x8 0.--9. 1. "DATA,SEE PMU definition for usage" line.long 0xC "SYSCTL_PMUTRIM2,PMU TRIM 2" hexmask.long.word 0xC 0.--9. 1. "DATA,SEE PMU definition for usage" line.long 0x10 "SYSCTL_PMUTRIM3,PMU TRIM 3" hexmask.long.word 0x10 0.--9. 1. "DATA,SEE PMU definition for usage" line.long 0x14 "SYSCTL_PMUTRIM4,PMU TRIM 4" hexmask.long.word 0x14 0.--9. 1. "DATA,SEE PMU definition for usage" line.long 0x18 "SYSCTL_PMUTRIM5,PMU TRIM 5" hexmask.long.word 0x18 0.--9. 1. "DATA,SEE PMU definition for usage" line.long 0x1C "SYSCTL_FLASHPUMPTRIM,Flash Pump TRIM-CFG" line.long 0x20 "SYSCTL_FLASHBANK0TRIM,btname TRIM-CFG" line.long 0x24 "SYSCTL_FLASHBANK0REPAIR,brname Flash Repair" hexmask.long.word 0x24 0.--13. 1. "DATA,Repair Bits" line.long 0x28 "SYSCTL_FLASHSRAMCFG,Flash and SRAM Configuration" bitfld.long 0x28 31. "FLTRIMDONE,1: Flash TRIM bits loaded 0: TRIM unwritten" "0: TRIM unwritten,1: Flash TRIM bits loaded" bitfld.long 0x28 8. "MAIN2T,1: Main (nonmain) are 2T access 0: Main (nonmain) are 1T access" "0: Main,1: Main" newline bitfld.long 0x28 4.--5. "SRSIZE,SRAM Paper Spin 0: Full size 1: 1/2 2: 1/4" "0: Full size,1: 1/2,2: 1/4,?" bitfld.long 0x28 0.--1. "FLSIZE,Flash Paper Spin 0: Full size 1: 1/2 2: 1/4" "0: Full size,1: 1/2,2: 1/4,?" line.long 0x2C "SYSCTL_SRAMTIMING,SRAM timing MMR for ESRAM controller. based on 4MHz" hexmask.long.byte 0x2C 12.--15. 1. "TISOGOODFALL2CLKRISE,ISO GOOD FALL to CLKRISE spec 250ns (boot 500ns)" hexmask.long.byte 0x2C 8.--11. 1. "TPGOODRISE2ISOFALL,PGOOD RISE to ISO FALL spec 750ns (boot 1500ns)" newline hexmask.long.byte 0x2C 4.--7. 1. "TSTRONG,Driver Weak to Stong timing spec 1000ns (boot 1500ns)" hexmask.long.byte 0x2C 0.--3. 1. "TISORISE2XONFALL,ISO Rise to any ON FALL spec 500ns (boot 750ns)" line.long 0x30 "SYSCTL_SYSOSCTRIM4MHZ,SYSOSC Trim Values for 4MHz target" hexmask.long.byte 0x30 16.--19. 1. "RESFINE,Resister Coarse TRIM - Changes per frequency target" hexmask.long.byte 0x30 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" newline bitfld.long 0x30 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" line.long 0x34 "SYSCTL_SYSOSCTRIM4MHZFCL,SYSOSC Trim Values for 4MHz target with FCL enabled" hexmask.long.word 0x34 20.--28. 1. "RDIV,FCL RDIV TRIM - Changes per frequency target" hexmask.long.byte 0x34 16.--19. 1. "RESFINE,Resister Coarse TRIM - Changes per frequency target" newline hexmask.long.byte 0x34 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" bitfld.long 0x34 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" line.long 0x38 "SYSCTL_SYSOSCTRIMBASEFCL,SYSOSC Trim Values for 32MHz target with FCL enabled" hexmask.long.word 0x38 20.--28. 1. "RDIV,FCL RDIV TRIM - Changes per frequency target" hexmask.long.byte 0x38 16.--19. 1. "RESFINE,Resister Fine TRIM - Changes per frequency target" newline hexmask.long.byte 0x38 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" bitfld.long 0x38 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--1. "FCLOTAIBIAS,FCL IBIAS TRIM Not frequency dependent" "0,1,2,3" line.long 0x3C "SYSCTL_LFOSCTRIM0,LFOSC TRIM values" hexmask.long.byte 0x3C 8.--12. 1. "CCODE,LFOSC Cap Frequency Trim" hexmask.long.byte 0x3C 0.--4. 1. "RCODE,LFOSC Res Frequency Trim" line.long 0x40 "SYSCTL_LFOSCTRIM1,LFOSC TRIM values" hexmask.long.byte 0x40 24.--28. 1. "RTN,LFOSC Noise Trim" bitfld.long 0x40 21. "CLKSEL,0: divide LFOSC by 2 to give 32KHz 1: pass through 64KHz" "0: divide LFOSC by 2 to give 32KHz,1: pass through 64KHz" newline bitfld.long 0x40 20. "RSHIFT,LFOSC RSHIFT Trim" "0,1" hexmask.long.byte 0x40 16.--19. 1. "MUXCFG,LFOSC Mux CFG Trim" newline hexmask.long.word 0x40 0.--14. 1. "CFG,LFOSC CFG Trim" line.long 0x44 "SYSCTL_LFXTTRIM,LFXT TRIM values" bitfld.long 0x44 30.--31. "MONITOROFFTIME,XT Monitor Off Time Trim" "0,1,2,3" bitfld.long 0x44 28.--29. "MAININV,LFXT Main Inverter Strength" "0,1,2,3" newline bitfld.long 0x44 27. "GLITCHFILTER,Glitch Filter Enable" "0,1" bitfld.long 0x44 26. "SWSUPPLYEN,LFXT SW Supply Enable" "0,1" newline bitfld.long 0x44 25. "LKCOMPDISABLE,LFXT Leakage Comp Disable" "0,1" bitfld.long 0x44 24. "GFCFG,LFXT GFCFG" "0,1" newline bitfld.long 0x44 23. "FASTSTARTUP,LFXT Fast Startup Select" "0,1" bitfld.long 0x44 20.--22. "STARTUPTIME,LFXT Startup Time" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x44 16.--19. 1. "HYSCFG,LFXT Hysterisys Config" hexmask.long.byte 0x44 12.--15. 1. "MANTRIMHIGHEST,LFXT Man Reg Trim Highest Power" newline hexmask.long.byte 0x44 8.--11. 1. "MANTRIMHIGHER,LFXT Man Reg Trim Higher Power" hexmask.long.byte 0x44 4.--7. 1. "MANTRIMLOWER,LFXT Man Reg Trim Lower Power" newline hexmask.long.byte 0x44 0.--3. 1. "MANTRIMLOWEST,LFXT Man Reg Trim Lowest Power" line.long 0x48 "SYSCTL_HFXTTRIM0,HFXT TRIM and Override" bitfld.long 0x48 31. "KICKSTARTDISABLE,DISABLE Kickstart" "0,1" bitfld.long 0x48 30. "MAGOVERRIDE,Use this TRIM value instead of hardwired" "0,1" newline hexmask.long.byte 0x48 24.--29. 1. "MAGR3,Value for MAG TRIM Range 3" hexmask.long.byte 0x48 16.--21. 1. "MAGR2,Value for MAG TRIM Range 2" newline hexmask.long.byte 0x48 8.--13. 1. "MAGR1,Value for MAG TRIM Range 1" hexmask.long.byte 0x48 0.--5. 1. "MAGR0,Value for MAG TRIM Range 0" line.long 0x4C "SYSCTL_HFXTTRIM1,HFXT TRIM and Override" hexmask.long.byte 0x4C 24.--31. 1. "DRVR3,Value for DRV TRIM Range 3" hexmask.long.byte 0x4C 16.--23. 1. "DRVR2,Value for DRV TRIM Range 2" newline hexmask.long.byte 0x4C 8.--15. 1. "DRVR1,Value for DRV TRIM Range 1" hexmask.long.byte 0x4C 0.--7. 1. "DRVR0,Value for DRV TRIM Range 0" line.long 0x50 "SYSCTL_PLLTRIM0,PLL TRIM and Override" hexmask.long.byte 0x50 16.--20. 1. "LPFVCOVTUNE,LPF VCOVTUNE NOM Value" hexmask.long.byte 0x50 8.--13. 1. "VCOSTARTTIME,VCO Start Settling Time in SYSOSC BASE clocks generally 32MHz - this comes before STARTTIME-STARTTIMELP" newline hexmask.long.byte 0x50 4.--7. 1. "VCOJUMPTIME,VCO Freq Jump Settling Time" bitfld.long 0x50 2.--3. "SEARCHITER,Search iterations to perform" "0,1,2,3" newline bitfld.long 0x50 1. "SEARCHALGO,Select Search Mode Algorithm" "0,1" bitfld.long 0x50 0. "SEARCHALWAYS,Force Freq Search to ALWAYS be performed" "0,1" line.long 0x54 "SYSCTL_PLLTRIM1,PLL TRIM and Override" bitfld.long 0x54 25. "EXCHG1X2X,Exchange 1X and 2X clock paths - Experimental" "0,1" bitfld.long 0x54 24. "VCOIDACOVRDEN,VCO Feq IDAC mcode override enable" "0,1" newline hexmask.long.byte 0x54 16.--22. 1. "VCOIDACOVRDVAL,VCO Feq IDAC mcode override val" hexmask.long.byte 0x54 8.--14. 1. "IDACOFFSET,IDAC Offset Value" newline hexmask.long.byte 0x54 0.--6. 1. "IDACSTART,IDAC Start Value" line.long 0x58 "SYSCTL_ADC12B0TRIM0,Bits 31..0 of CDAC" line.long 0x5C "SYSCTL_ADC12B0TRIM1,Bits 63..32 of CDAC" line.long 0x60 "SYSCTL_ADC12B0TRIM2,Bits 65..64 of CDAC. and other ADC12B0 always trims" hexmask.long.byte 0x60 16.--22. 1. "LATCH,LATCH TRIM" hexmask.long.word 0x60 4.--15. 1. "OFFSET,OFFSET TRIM" newline bitfld.long 0x60 2.--3. "RESISTOR,RESISTOR TRIM" "0,1,2,3" bitfld.long 0x60 0.--1. "CDACUPPER,Bits 65..64 of CDAC" "0,1,2,3" line.long 0x64 "SYSCTL_ADC12B0TRIM3,Additional ADC trims for 12B 4MSPS" hexmask.long.byte 0x64 4.--9. 1. "OSC,Oscillator" hexmask.long.byte 0x64 0.--3. 1. "PERIOD,Period" line.long 0x68 "SYSCTL_ADC12B1TRIM0,Bits 31..0 of CDAC" line.long 0x6C "SYSCTL_ADC12B1TRIM1,Bits 63..32 of CDAC" line.long 0x70 "SYSCTL_ADC12B1TRIM2,Bits 65..64 of CDAC. and other ADC12B1 always trims" hexmask.long.byte 0x70 16.--22. 1. "LATCH,LATCH TRIM" hexmask.long.word 0x70 4.--15. 1. "OFFSET,OFFSET TRIM" newline bitfld.long 0x70 2.--3. "RESISTOR,RESISTOR TRIM" "0,1,2,3" bitfld.long 0x70 0.--1. "CDACUPPER,Bits 65..64 of CDAC" "0,1,2,3" line.long 0x74 "SYSCTL_ADC12B1TRIM3,Additional ADC trims for 12B 4MSPS" hexmask.long.byte 0x74 4.--9. 1. "OSC,Oscillator" hexmask.long.byte 0x74 0.--3. 1. "PERIOD,Period" line.long 0x78 "SYSCTL_DAC12B0TRIM,Trims for 12B DAC" hexmask.long.byte 0x78 8.--13. 1. "RDYCNT,Ready Count in 1 usec resolution" bitfld.long 0x78 7. "SPARE,SPARE bit" "0,1" newline bitfld.long 0x78 5.--6. "CALIBCLKDIV,Calibration Clock Divide Conrol" "0,1,2,3" bitfld.long 0x78 4. "TRIMENOVRD,Trim Enable Override" "0,1" newline bitfld.long 0x78 2.--3. "OFFSETRNG,Offset Range" "0,1,2,3" bitfld.long 0x78 0.--1. "IBIAS,IBIAS" "0,1,2,3" line.long 0x7C "SYSCTL_OPAMP0TRIM,Trims for Opamp0" hexmask.long.byte 0x7C 26.--31. 1. "RDYGBW1GAIN32,Common Opamp Ready time (in usec)for GBW 1 GAIN 32" hexmask.long.byte 0x7C 20.--25. 1. "RDYGBW1GAIN1,Common Opamp Ready time (in usec)for GBW 1 GAIN 1" newline hexmask.long.byte 0x7C 14.--19. 1. "RDYGBW0GAIN32,Common Opamp Ready time (in usec)for GBW 0 GAIN 32" hexmask.long.byte 0x7C 8.--13. 1. "RDYGBW0GAIN1,Common Opamp Ready time (in usec) for GBW 0 GAIN 1" newline hexmask.long.byte 0x7C 0.--5. 1. "DATA,Opamp0 Trim" line.long 0x80 "SYSCTL_OPAMP1TRIM,Trims for Opamp1" hexmask.long.byte 0x80 0.--5. 1. "DATA,Opamp1 Trim" line.long 0x84 "SYSCTL_ANACOMPTRIM,Common Trims for Anacomp" hexmask.long.byte 0x84 24.--29. 1. "TSRDYCNT,TempSense Ready Count in 1 usec resolution" hexmask.long.byte 0x84 16.--21. 1. "DACMODE1RDYCNT,DAC Ready Count in 1 usec resolution" newline hexmask.long.byte 0x84 8.--13. 1. "DACMODE0RDYCNT,DAC Ready Count in 250ns usec resolution" hexmask.long.byte 0x84 0.--5. 1. "RDYCNT,Ready Count in 1 usec resolution" line.long 0x88 "SYSCTL_TRNGTRIM,Trim for TRNG" bitfld.long 0x88 24.--25. "VCMNOISE,TRNG VCM Noise TRIM" "0,1,2,3" bitfld.long 0x88 20.--22. "CPCURRENT,TRNG CP Current TRIM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 16.--18. "IREF,TRNG IREF TRIM" "0,1,2,3,4,5,6,7" bitfld.long 0x88 14.--15. "V2ICURRENT,TRNG V2i Current TRIM" "0,1,2,3" newline bitfld.long 0x88 12.--13. "PULSEDELAY,TRNG Pulse Delay TRIM" "0,1,2,3" bitfld.long 0x88 8.--10. "AMPCURRENT,TRNG Amp Current TRIM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x88 6.--7. "PULSERES,TRNG Pulse Res TRIM" "0,1,2,3" bitfld.long 0x88 4.--5. "LDOCURRENT,TRNG LDO Current TRIM" "0,1,2,3" newline bitfld.long 0x88 2.--3. "VCMPUMP,TRNG VCM Pump TRIM" "0,1,2,3" bitfld.long 0x88 0.--1. "VLDO,TRNG VLDO TRIM" "0,1,2,3" line.long 0x8C "SYSCTL_MISCTRIM,Various Small TRIM" hexmask.long.byte 0x8C 24.--28. 1. "ANAFLTRIS,Analog GlitchFilter Rising Trim" hexmask.long.byte 0x8C 16.--20. 1. "ANAFLTFALL,Analog GlitchFilter Falling Trim" newline hexmask.long.byte 0x8C 8.--13. 1. "AFEVREFRDYCNT,VREF Ready Count Nano is in 1 usec Micro in 8 usec resolution" bitfld.long 0x8C 0.--2. "AFEVREF,VREF TRIM" "0,1,2,3,4,5,6,7" line.long 0x90 "SYSCTL_PADEXIST0,PAD Exist for IOMUX" line.long 0x94 "SYSCTL_PADEXIST1,PAD Exist for IOMUX" hexmask.long 0x94 0.--27. 1. "DATA,Padexists Vector bits" line.long 0x98 "SYSCTL_IPAVAIL0,IP Available Paper Spin" bitfld.long 0x98 31. "mcan0,Peripheral Instance Available" "0,1" bitfld.long 0x98 30. "gptimer24bp0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 29. "gptimer16bsp2,Peripheral Instance Available" "0,1" bitfld.long 0x98 28. "gptimer16bsp1,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 27. "gptimer16bsp0,Peripheral Instance Available" "0,1" bitfld.long 0x98 26. "wwdtlp1,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 25. "aes,Peripheral Instance Available" "0,1" bitfld.long 0x98 24. "trng,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 23. "spi1,Peripheral Instance Available" "0,1" bitfld.long 0x98 22. "gpio1,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 21. "adc12b4msps1,Peripheral Instance Available" "0,1" bitfld.long 0x98 20. "anacomp2,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 19. "anacomp1,Peripheral Instance Available" "0,1" bitfld.long 0x98 18. "opamp1,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 17. "uart0,Peripheral Instance Available" "0,1" bitfld.long 0x98 16. "uartlp1,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 15. "gptimer16bqei0,Peripheral Instance Available" "0,1" bitfld.long 0x98 14. "crc0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 13. "spi0,Peripheral Instance Available" "0,1" bitfld.long 0x98 12. "uartadvlp0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 11. "gpio0,Peripheral Instance Available" "0,1" bitfld.long 0x98 10. "adc12b4msps0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 9. "anacomp0,Peripheral Instance Available" "0,1" bitfld.long 0x98 8. "dac12b0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 7. "opamp0,Peripheral Instance Available" "0,1" bitfld.long 0x98 6. "gptimer16b1,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 5. "gptimer16b0,Peripheral Instance Available" "0,1" bitfld.long 0x98 4. "uartlp0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 3. "i2c1,Peripheral Instance Available" "0,1" bitfld.long 0x98 2. "i2c0,Peripheral Instance Available" "0,1" newline bitfld.long 0x98 1. "rtc,Peripheral Instance Available" "0,1" bitfld.long 0x98 0. "wwdtlp0,Peripheral Instance Available" "0,1" line.long 0x9C "SYSCTL_IPAVAIL1,IP Available Paper Spin" bitfld.long 0x9C 2. "vref,Peripheral Instance Available" "0,1" bitfld.long 0x9C 1. "tmalite1,Peripheral Instance Available" "0,1" newline bitfld.long 0x9C 0. "matcacl,Peripheral Instance Available" "0,1" line.long 0xA0 "SYSCTL_FUNCPSPIN,Functional Paper Spin Options" bitfld.long 0xA0 0. "MCANFD,MCAN FD enabled" "0,1" line.long 0xA4 "SYSCTL_SYSOSCTRIMTURBO,SYSOSC Trim Values for R&D Maximum target. likely 48MHz" hexmask.long.byte 0xA4 16.--19. 1. "RESFINE,Resister Coarse TRIM - Changes per frequency target" hexmask.long.byte 0xA4 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" newline bitfld.long 0xA4 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" line.long 0xA8 "SYSCTL_SYSOSCTRIMTURBOFCL,SYSOSC Trim Values for TURBO target with FCL enabled" hexmask.long.word 0xA8 20.--28. 1. "RDIV,FCL RDIV TRIM - Changes per frequency target" hexmask.long.byte 0xA8 16.--19. 1. "RESFINE,Resister Coarse TRIM - Changes per frequency target" newline hexmask.long.byte 0xA8 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" bitfld.long 0xA8 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" line.long 0xAC "SYSCTL_TRIMCRC,FINAL 16 bit CRC of the TRIM load" hexmask.long.word 0xAC 0.--15. 1. "DATA,final 16 bit CRC value" group.long 0x2C00++0xB line.long 0x0 "SYSCTL_DFTSYSOSC,DFT Control for HFXT" bitfld.long 0x0 17. "FCLVAL,Override Value for the FCL Enable into the hard macro" "0,1" bitfld.long 0x0 16. "FCLOVRRIDE,Override the FCL Enable into the hard macro" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "ATBCTL,ATB Control" bitfld.long 0x0 8.--9. "DBUGCTL,Debug Control" "0,1,2,3" newline bitfld.long 0x0 4. "DTBEN,Enable DTB Structure" "0,1" bitfld.long 0x0 0.--1. "ATBEN,Enable ATB Structure" "0,1,2,3" line.long 0x4 "SYSCTL_DFTLFCLK,DFT Control for LFCLK Hard Macro" hexmask.long.byte 0x4 16.--19. 1. "DLYTESTCTL,Delay Cell Test CTL" bitfld.long 0x4 13. "DLYTESTEN,Delay Cell Test Enable" "0,1" newline bitfld.long 0x4 12. "DLYTRIMEN,Delay Cell Trim Enable" "0,1" bitfld.long 0x4 11. "DLYTRIMBP,Delay Cell Trim Bypass" "0,1" newline bitfld.long 0x4 10. "DTBSELUPPER,DTB Select for Upper 4 bits of DTBO[11:0] of hard macro" "0,1" bitfld.long 0x4 8.--9. "ATBUNBUFSEL,ATB Buffered Signal Select" "0,1,2,3" newline bitfld.long 0x4 4.--6. "ATBBUFSEL,ATB Buffered Signal Select" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "DTBSEL,DTB Select at hard macro" "0,1,2,3" newline bitfld.long 0x4 0.--1. "ATB,Bit1: enables buffered path Bit0 enables unbuffered path" "0,1,2,3" line.long 0x8 "SYSCTL_DFTVBSTCP,DFT for VBOOST Charge Pump" bitfld.long 0x8 9. "TESTOUT,Not conditioned with Bypass. Creates weak test output" "0,1" bitfld.long 0x8 8. "ATBEN,This must be enabled for ATB muxing to operate" "0,1" newline bitfld.long 0x8 5. "BYPFILTER,No filter makes power up faster" "0,1" bitfld.long 0x8 4. "BYPCLKMUL,Multiply CP clk by 8" "0,1" newline bitfld.long 0x8 2.--3. "BYPCLKSEL,CP Clock Select" "0,1,2,3" bitfld.long 0x8 1. "BYPEN,EN to Hard Macro" "0,1" newline bitfld.long 0x8 0. "BYPASS,BYPASS ALL Normal Control" "0,1" group.long 0x2C10++0x3 line.long 0x0 "SYSCTL_DFTHFXT,DFT Control for HFXT" bitfld.long 0x0 22. "USEDTBI0,Use DTBI[0] as the HFCLK output" "0,1" bitfld.long 0x0 21. "SUP2ULLISO,Isolate HFXT analog from 3V PAD" "0,1" newline bitfld.long 0x0 20. "SLICERDISABLE,Turn off slicer" "0,1" bitfld.long 0x0 19. "ICG,Override Turn HFCLK related ICGs ON qualified with HFCLKSEL" "0,1" newline bitfld.long 0x0 18. "HFXTEN,Override value for HFXT ENABLE to Hard Macro" "0,1" bitfld.long 0x0 17. "HFCLKSEL,Use External Pin as High Frequency Oscillator Source(HFCLK)" "0,1" newline bitfld.long 0x0 16. "FSMOVERRIDE,Override outputs of HFCLK FSM" "0,1" bitfld.long 0x0 8.--10. "ATBUNBUFSEL,ATB Buffered Signal Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "ATBBUFSEL,ATB Buffered Signal Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "ATB,Enable ATB Structure" "0,1" group.long 0x2C20++0x7 line.long 0x0 "SYSCTL_DFTSYSPLL0,DFT Control for SYSPLL" hexmask.long.byte 0x0 20.--25. 1. "VCOIDACVAL,Override Value For VCO Freq Idac Code" bitfld.long 0x0 16. "VCOIDACOVERRIDE,Override Enable For VCO Freq Idac Code" "0,1" newline bitfld.long 0x0 12.--14. "DTBSEL,DTB Signal Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "ATBUNBUFSEL,ATB UnBuffered Signal Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "ATBBUFSEL,ATB Buffered Signal Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "DTB,Enable DTB Structure" "0,1" newline bitfld.long 0x0 0. "ATB,Enable ATB Structure" "0,1" line.long 0x4 "SYSCTL_DFTSYSPLL1,DFT Control for SYSPLL" bitfld.long 0x4 8.--9. "REFCLKSEL,Override value to select Ref Clk" "0,1,2,3" bitfld.long 0x4 7. "ICG2X,Override value to turn PLL ICGCLK2X ON" "0,1" newline bitfld.long 0x4 6. "ICG1,Override value to turn PLL ICGCLK1 ON" "0,1" bitfld.long 0x4 5. "ICG0,Override value to turn PLL ICGCLK0 ON" "0,1" newline bitfld.long 0x4 4. "PDISO,Assert ISO PD to the hard macro" "0,1" bitfld.long 0x4 3. "PDRST,Assert RST PD to the hard macro" "0,1" newline bitfld.long 0x4 2. "ONDOMAINRST,Assert ONDOMAIN RST to the hard macro" "0,1" bitfld.long 0x4 1. "PLLEN,Override value for PLL ENABLE to PLL" "0,1" newline bitfld.long 0x4 0. "FSMOVERRIDE,Override outputs of PLL FSM" "0,1" group.long 0x2C40++0xB line.long 0x0 "SYSCTL_DFTPMUATB,DFT Control for PMU ATB" bitfld.long 0x0 21. "UNBUFOUTSWEN" "0,1" bitfld.long 0x0 20. "BUFOUTSWEN" "0,1" newline bitfld.long 0x0 19. "UBUF2BUFPADEN" "0,1" bitfld.long 0x0 18. "UBUF2BUFEN" "0,1" newline bitfld.long 0x0 17. "UBUFMUXSEL" "0,1" bitfld.long 0x0 16. "BUFMUXSEL" "0,1" newline bitfld.long 0x0 12.--13. "BUFFERFB" "0,1,2,3" bitfld.long 0x0 8.--10. "BUFFERMDSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "BUFFEREN" "0,1" bitfld.long 0x0 4. "BYPASSSWEN" "0,1" newline bitfld.long 0x0 3. "SENSEMUXSEL" "0,1" bitfld.long 0x0 2. "SENSEEN" "0,1" newline bitfld.long 0x0 1. "UBUFEN,ATB UnBuffered Output Enable" "0,1" bitfld.long 0x0 0. "BUFEN,ATB Buffered Output Enable" "0,1" line.long 0x4 "SYSCTL_DFTPMUCTL,DFT Control for PMU CTL" bitfld.long 0x4 24.--26. "DTBOSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x4 22. "PARDIS" "0,1" newline bitfld.long 0x4 21. "PARBYPASS" "0,1" bitfld.long 0x4 20. "DFTPORREQ" "0,1" newline bitfld.long 0x4 19. "LDOCOMPEN" "0,1" bitfld.long 0x4 18. "LDODISLDO" "0,1" newline bitfld.long 0x4 17. "LDOENCLAMP" "0,1" bitfld.long 0x4 16. "LDODISPD" "0,1" newline bitfld.long 0x4 15. "BORDISRST" "0,1" bitfld.long 0x4 14. "BORDISHYS" "0,1" newline bitfld.long 0x4 13. "BORCTOPFLIP" "0,1" bitfld.long 0x4 12. "BORRDIVPD" "0,1" newline bitfld.long 0x4 11. "REFEXTBGSEL" "0,1" bitfld.long 0x4 10. "REFCHOPCFG" "0,1" newline hexmask.long.byte 0x4 6.--9. 1. "PMUUBUFCTRL" hexmask.long.byte 0x4 2.--5. 1. "PMUBUFCTRL" newline bitfld.long 0x4 1. "PMUUBUFEN,ATB UnBuffered Output Enable" "0,1" bitfld.long 0x4 0. "PMUBUFEN,ATB Buffered Output Enable" "0,1" line.long 0x8 "SYSCTL_DFTPMULPM,DFT Control for PMU LPM" bitfld.long 0x8 5. "CPEN" "0,1" bitfld.long 0x8 4. "LOADRNG" "0,1" newline bitfld.long 0x8 3. "SMPLEN" "0,1" bitfld.long 0x8 2. "SMPL" "0,1" newline bitfld.long 0x8 1. "MODE" "0,1" bitfld.long 0x8 0. "OVRDEN" "0,1" group.long 0x2C60++0x3 line.long 0x0 "SYSCTL_DFTPMCU,Overall PMCU DFT Controls" bitfld.long 0x0 8. "EXTCLKOVRD,External Clock Override for DFT SEL" "0,1" hexmask.long.byte 0x0 4.--7. 1. "EXTCLKSEL,External Clock DFT Selections" newline hexmask.long.byte 0x0 0.--3. 1. "DTBOSEL,Major DTB Output Select" group.long 0x3000++0x3 line.long 0x0 "SYSCTL_FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash" hexmask.long.word 0x0 0.--15. 1. "DATA,1 Sector Write Erase protection 1: prohibits write-erase 0: allows" group.long 0x3014++0x13 line.long 0x0 "SYSCTL_FRWPROTMAINDATA,1KB sector based RW protection of first 4KB of data bank" hexmask.long.byte 0x0 0.--7. 1. "DATA,Each 1KB is configured for protection with 2 bits:" line.long 0x4 "SYSCTL_FRXPROTMAIN_START,Customer programmable RX firewall." hexmask.long 0x4 6.--31. 1. "ADDR,Higher order bits of start of RX protected MAIN flash bank address (ignoring least 6 bits" hexmask.long.byte 0x4 0.--5. 1. "RSVD" line.long 0x8 "SYSCTL_FRXPROTMAIN_END,Customer programmable RX firewall." hexmask.long 0x8 6.--31. 1. "ADDR,Higher order bits of start of RX protected MAIN flash bank address (ignoring least 6 bits" hexmask.long.byte 0x8 0.--5. 1. "RSVD" line.long 0xC "SYSCTL_FIPPROT_START,Customer programmable IP prorection firewall." hexmask.long 0xC 6.--31. 1. "ADDR,Higher order bits of start of RX protected MAIN flash bank address (ignoring least 6 bits" hexmask.long.byte 0xC 0.--5. 1. "RSVD" line.long 0x10 "SYSCTL_FIPPROT_END,Customer programmable IP prorection firewall." hexmask.long 0x10 6.--31. 1. "ADDR,Higher order bits of start of RX protected MAIN flash bank address (ignoring least 6 bits" hexmask.long.byte 0x10 0.--5. 1. "RSVD" wgroup.long 0x3038++0x3 line.long 0x0 "SYSCTL_FLBANKSWP_POLICY,Bank Swap Policy" bitfld.long 0x0 0. "POLICY,Flash Bank Swap Policy Intent." "0: No Effect,1: Bank Swap" rgroup.long 0x303C++0x3 line.long 0x0 "SYSCTL_SECCFG_FLBANKSWAP,Flash Bank Swap" bitfld.long 0x0 0. "USEUPPER,1: SWAP upper banks to lower 0: Normal Memory Map" "0: Normal Memory Map,1: SWAP upper banks to lower" wgroup.long 0x3044++0x3 line.long 0x0 "SYSCTL_FWENABLE,Firewall lock enable register" bitfld.long 0x0 8. "SRAMBOUNDARY_LOCK,SRAM Boundary Lock set" "0,1" bitfld.long 0x0 6. "FLIPPROT" "0,1" newline bitfld.long 0x0 4. "FLRXPROT" "0,1" rgroup.long 0x3048++0x3 line.long 0x0 "SYSCTL_SECSTAT,Firewall status register" bitfld.long 0x0 10. "FLBANK_SWAP" "?,1: System has a CSC." bitfld.long 0x0 8. "SRBNDRY_LOCK,SRAM Boundary Lock. 0 -- > not locked 1 -- > locked" "0,1" newline bitfld.long 0x0 6. "FLIPPROT_VALID,Firewall validity. 0 -- > not valid 1 -- > valid" "0,1" bitfld.long 0x0 4. "FLRXPROT_VALID,Firewall validity. 0 -- > not valid 1 -- > valid" "0,1" newline bitfld.long 0x0 2. "CSC_EXISTS" "0: No system does not have a CSC,1: System has a CSC." bitfld.long 0x0 0. "INITDONE" "0: INIT is not yet done,1: INIT is Done" group.long 0x304C++0x7 line.long 0x0 "SYSCTL_APSTART,Application Reset Handler address" hexmask.long.tbyte 0x0 2.--21. 1. "ADDR" line.long 0x4 "SYSCTL_APPSP,Application Stack Pointer" hexmask.long.tbyte 0x4 0.--19. 1. "ADDR" wgroup.long 0x3060++0x3 line.long 0x0 "SYSCTL_INITDONE,INITDONE PASS" bitfld.long 0x0 0.--1. "PASS,Customer Startup Code writes 3 for PASS No timeout enforcement." "?,?,?,3: BOOTCODE PASS" endif sif (cpuis("MSPM0G110*")) group.long 0x800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" endif sif (cpuis("MSPM0G150*")) group.long 0x800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x2800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x2804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x2808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x2814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xA808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xA814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xC800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xC804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xC808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xC814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x18800++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x18804++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x18814++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x82800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x82804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x82814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94800++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x94804++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x94814++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x102800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x102804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x102808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x102814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x410800++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x410804++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x410814++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x500800++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x500804++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x500808++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x500814++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x50E800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x50E804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x50E814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x862800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x862804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x862814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x868800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x868804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x868814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86A800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86A804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86A814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x900800++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x900804++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" endif sif (cpuis("MSPM0G151*")) group.long 0x800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x7 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." line.long 0x4 "SYSCTL_SRAMBOUNDARYHIGH,SRAM Write Boundary High" hexmask.long.word 0x4 5.--19. 1. "ADDR,SRAM boundary high configuration. The value configured into this acts such that: SRAM accesses to greater than value will be RW only. SRAM accesses to addresses less than or equal to value will be RX until meeting SRAMBOUNDARY MMR Value. Value of 0.." group.long 0x1184++0x3 line.long 0x0 "SYSCTL_SRAMCFG,System SRAM configuration" bitfld.long 0x0 9. "BANKSTOP1,SRAM BANK1 power level for STOP mode" "0: SRAM BANK1 power OFF for STOP mode,1: SRAM BANK1 power RETAIN for STOP mode" bitfld.long 0x0 1. "BANKOFF1,SRAM BANK1 power level for RUN mode" "0: SRAM BANK1 power ON for RUN mode,1: SRAM BANK1 power OFF for RUN mode" rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x2800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x2804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x2808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x2814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x3000++0x3 line.long 0x0 "SYSCTL_FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash" group.long 0x3014++0x13 line.long 0x0 "SYSCTL_FWPROTMAINDATA,Read-Write Protection for first 4 Sectors of Data Bank" hexmask.long.byte 0x0 0.--7. 1. "DATA,00: Both RW allowed 01: Read Only 10: No Read No Write 11: No Read No Write - Not Used" line.long 0x4 "SYSCTL_FRXPROTMAINSTART,Flash RX Protection Start Address" hexmask.long.word 0x4 6.--21. 1. "ADDR,Flash RX Protection Start Address 64B granularity" line.long 0x8 "SYSCTL_FRXPROTMAINEND,Flash RX Protection End Address" hexmask.long.word 0x8 6.--21. 1. "ADDR,Flash RX Protection End Address 64B granularity" line.long 0xC "SYSCTL_FIPPROTMAINSTART,Flash IP Protection Start Address" hexmask.long.word 0xC 6.--21. 1. "ADDR,Flash IP Protection Start Address 64B granularity" line.long 0x10 "SYSCTL_FIPPROTMAINEND,Flash IP Protection End Address" hexmask.long.word 0x10 6.--21. 1. "ADDR,Flash IP Protection End Address 64B granularity" wgroup.long 0x3038++0x7 line.long 0x0 "SYSCTL_FLBANKSWPPOLICY,Flash Bank Swap Policy" bitfld.long 0x0 0. "DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping" line.long 0x4 "SYSCTL_FLBANKSWP,Flash MAIN bank address swap" bitfld.long 0x4 0. "USEUPPER,1: Use Upper Bank as Logical 0" "0: Normal (default) memory map addressing scheme,1: Use Upper Bank as Logical 0" wgroup.long 0x3044++0x3 line.long 0x0 "SYSCTL_FWENABLE,Security Firewall Enable Register" bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR" bitfld.long 0x0 6. "FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" rgroup.long 0x3048++0x3 line.long 0x0 "SYSCTL_SECSTATUS,Security Configuration status" bitfld.long 0x0 12. "FLBANKSWP,1: Upper and Lower Banks have been swapped" "?,1: Upper and Lower Banks have been swapped" newline bitfld.long 0x0 10. "FLBANKSWPPOLICY,1: Upper and Lower Banks allowed to be swapped" "?,1: Upper and Lower Banks allowed to be swapped" newline bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: SRAM Boundary MMR Locked" "?,1: SRAM Boundary MMR Locked" bitfld.long 0x0 6. "FLIPPROT,1: Flash IP Protection Active" "?,1: Flash IP Protection Active" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" bitfld.long 0x0 2. "CSCEXISTS,1: CSC Exists in the system" "0: System does not have a CSC,1: CSC Exists in the system" newline bitfld.long 0x0 0. "INITDONE,1: CSC has been completed" "0: INIT is not yet done,1: CSC has been completed" wgroup.long 0x3060++0x3 line.long 0x0 "SYSCTL_INITDONE,INITCODE PASS" bitfld.long 0x0 0. "PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: INITCODE PASS" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xA808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xA814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xC800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xC804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xC808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xC814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x18800++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x18804++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x18814++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x82800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x82804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x82814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x92800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x92804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x92814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" group.long 0x96800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP4_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x96804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP4_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x96814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP4_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA4800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA4804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA4814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF4800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF4804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF4808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF4814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x10A800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x10A804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x10A808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x10A814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x410800++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x410804++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x410814++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46C800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46C804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46C808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46C814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x500800++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x500804++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x500808++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x500814++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x502800++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x502804++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x502808++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x502814++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x504800++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x504804++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x504808++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x504814++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x506800++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x506804++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x506808++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x506814++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x50E800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x50E804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x50E814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x516800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x516804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x516814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x862800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x862804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x862814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x868800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x868804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x868814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86A800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86A804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86A814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0G310*")) group.long 0x800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x1380++0x3 line.long 0x0 "SYSCTL_PMUOPAMP,GPAMP control" bitfld.long 0x0 10.--11. "CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: Chopping disabled,1: Normal chopping,2: ADC Assisted chopping,?" bitfld.long 0x0 8.--9. "CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: 16kHz,1: 8kHz,2: 4kHz,3: 2kHz" newline bitfld.long 0x0 6. "OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: GPAMP_OUT signal is not connected to the..,1: GPAMP_OUT signal is connected to the GPAMP_OUT pin" bitfld.long 0x0 4.--5. "RRI,RRI selects the rail-to-rail input mode." "0: PMOS input pairs,1: NMOS input pairs,2: Rail-to-rail mode,3: Rail-to-rail mode" newline bitfld.long 0x0 2.--3. "NSEL,NSEL selects the GPAMP negative channel input." "0: GPAMP_OUT pin connected to negative channel,1: GPAMP_IN- pin connected to negative channel,2: GPAMP_OUT signal connected to negative channel,3: No channel selected" bitfld.long 0x0 1. "PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: Positive channel disabled,1: GPAMP_IN+ connected to positive channel" newline bitfld.long 0x0 0. "ENABLE,Set ENABLE to turn on the GPAMP." "0: GPAMP is disabled,1: GPAMP is enabled" group.long 0x2800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x2804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x2808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x2814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xA808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xA814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xC800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xC804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xC808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xC814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x18800++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x18804++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x18814++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x82800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x82804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x82814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94800++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x94804++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x94814++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x102800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x102804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x102808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x102814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x410800++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x410804++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x410814++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x500800++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x500804++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x500808++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x500814++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x50E800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x50E804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x50E814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x862800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x862804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x862814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x868800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x868804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x868814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86A800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86A804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86A814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x900800++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x900804++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" endif sif (cpuis("MSPM0G350*")) group.long 0x800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x1380++0x3 line.long 0x0 "SYSCTL_PMUOPAMP,GPAMP control" bitfld.long 0x0 10.--11. "CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: Chopping disabled,1: Normal chopping,2: ADC Assisted chopping,?" bitfld.long 0x0 8.--9. "CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: 16kHz,1: 8kHz,2: 4kHz,3: 2kHz" newline bitfld.long 0x0 6. "OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: GPAMP_OUT signal is not connected to the..,1: GPAMP_OUT signal is connected to the GPAMP_OUT pin" bitfld.long 0x0 4.--5. "RRI,RRI selects the rail-to-rail input mode." "0: PMOS input pairs,1: NMOS input pairs,2: Rail-to-rail mode,3: Rail-to-rail mode" newline bitfld.long 0x0 2.--3. "NSEL,NSEL selects the GPAMP negative channel input." "0: GPAMP_OUT pin connected to negative channel,1: GPAMP_IN- pin connected to negative channel,2: GPAMP_OUT signal connected to negative channel,3: No channel selected" bitfld.long 0x0 1. "PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: Positive channel disabled,1: GPAMP_IN+ connected to positive channel" newline bitfld.long 0x0 0. "ENABLE,Set ENABLE to turn on the GPAMP." "0: GPAMP is disabled,1: GPAMP is enabled" group.long 0x2800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x2804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x2808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x2814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xA808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xA814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xC800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xC804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xC808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xC814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x18800++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x18804++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x18814++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x82800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x82804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x82814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94800++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x94804++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x94814++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x102800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x102804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x102808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x102814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x410800++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x410804++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x410814++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x500800++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x500804++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x500808++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x500814++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x50E800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x50E804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x50E814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x862800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x862804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x862814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x868800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x868804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x868814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86A800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86A804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86A814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x900800++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x900804++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" endif sif (cpuis("MSPM0G351*")) group.long 0x800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" hexmask.long.byte 0x0 0.--3. 1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 5. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 4. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 3. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 2. "WWDT1,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x7 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." line.long 0x4 "SYSCTL_SRAMBOUNDARYHIGH,SRAM Write Boundary High" hexmask.long.word 0x4 5.--19. 1. "ADDR,SRAM boundary high configuration. The value configured into this acts such that: SRAM accesses to greater than value will be RW only. SRAM accesses to addresses less than or equal to value will be RX until meeting SRAMBOUNDARY MMR Value. Value of 0.." group.long 0x1184++0x3 line.long 0x0 "SYSCTL_SRAMCFG,System SRAM configuration" bitfld.long 0x0 9. "BANKSTOP1,SRAM BANK1 power level for STOP mode" "0: SRAM BANK1 power OFF for STOP mode,1: SRAM BANK1 power RETAIN for STOP mode" bitfld.long 0x0 1. "BANKOFF1,SRAM BANK1 power level for RUN mode" "0: SRAM BANK1 power ON for RUN mode,1: SRAM BANK1 power OFF for RUN mode" rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x2800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x2804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x2808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x2814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x3000++0x3 line.long 0x0 "SYSCTL_FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash" group.long 0x3014++0x13 line.long 0x0 "SYSCTL_FWPROTMAINDATA,Read-Write Protection for first 4 Sectors of Data Bank" hexmask.long.byte 0x0 0.--7. 1. "DATA,00: Both RW allowed 01: Read Only 10: No Read No Write 11: No Read No Write - Not Used" line.long 0x4 "SYSCTL_FRXPROTMAINSTART,Flash RX Protection Start Address" hexmask.long.word 0x4 6.--21. 1. "ADDR,Flash RX Protection Start Address 64B granularity" line.long 0x8 "SYSCTL_FRXPROTMAINEND,Flash RX Protection End Address" hexmask.long.word 0x8 6.--21. 1. "ADDR,Flash RX Protection End Address 64B granularity" line.long 0xC "SYSCTL_FIPPROTMAINSTART,Flash IP Protection Start Address" hexmask.long.word 0xC 6.--21. 1. "ADDR,Flash IP Protection Start Address 64B granularity" line.long 0x10 "SYSCTL_FIPPROTMAINEND,Flash IP Protection End Address" hexmask.long.word 0x10 6.--21. 1. "ADDR,Flash IP Protection End Address 64B granularity" wgroup.long 0x3038++0x7 line.long 0x0 "SYSCTL_FLBANKSWPPOLICY,Flash Bank Swap Policy" bitfld.long 0x0 0. "DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping" line.long 0x4 "SYSCTL_FLBANKSWP,Flash MAIN bank address swap" bitfld.long 0x4 0. "USEUPPER,1: Use Upper Bank as Logical 0" "0: Normal (default) memory map addressing scheme,1: Use Upper Bank as Logical 0" wgroup.long 0x3044++0x3 line.long 0x0 "SYSCTL_FWENABLE,Security Firewall Enable Register" bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR" bitfld.long 0x0 6. "FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" rgroup.long 0x3048++0x3 line.long 0x0 "SYSCTL_SECSTATUS,Security Configuration status" bitfld.long 0x0 12. "FLBANKSWP,1: Upper and Lower Banks have been swapped" "?,1: Upper and Lower Banks have been swapped" newline bitfld.long 0x0 10. "FLBANKSWPPOLICY,1: Upper and Lower Banks allowed to be swapped" "?,1: Upper and Lower Banks allowed to be swapped" newline bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: SRAM Boundary MMR Locked" "?,1: SRAM Boundary MMR Locked" bitfld.long 0x0 6. "FLIPPROT,1: Flash IP Protection Active" "?,1: Flash IP Protection Active" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" bitfld.long 0x0 2. "CSCEXISTS,1: CSC Exists in the system" "0: System does not have a CSC,1: CSC Exists in the system" newline bitfld.long 0x0 0. "INITDONE,1: CSC has been completed" "0: INIT is not yet done,1: CSC has been completed" wgroup.long 0x3060++0x3 line.long 0x0 "SYSCTL_INITDONE,INITCODE PASS" bitfld.long 0x0 0. "PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: INITCODE PASS" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xA808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xA814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xC800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xC804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xC808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xC814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x18800++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x18804++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x18814++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x82800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x82804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x82814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x92800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x92804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x92814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" group.long 0x96800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP4_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x96804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP4_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x96814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP4_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA4800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA4804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA4814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF4800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF4804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF4808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF4814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x10A800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x10A804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x10A808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x10A814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x410800++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x410804++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x410814++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46C800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46C804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46C808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46C814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x500800++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x500804++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x500808++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x500814++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x502800++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x502804++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x502808++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x502814++0x3 line.long 0x0 "SYSCTL_MGMT_UART1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x504800++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x504804++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x504808++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x504814++0x3 line.long 0x0 "SYSCTL_MGMT_UART2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x506800++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x506804++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x506808++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x506814++0x3 line.long 0x0 "SYSCTL_MGMT_UART3_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x50E800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x50E804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x50E814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x516800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x516804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x516814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x862800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x862804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x862814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x868800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x868804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x868814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86A800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86A804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86A814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif rgroup.long 0x1020++0x3 line.long 0x0 "SYSCTL_IIDX,Event IIDX" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,Interrupt Index Register -- Read Only" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 0.--3. 1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." "0: No interrupt pending,1: LFOSCGOOD interrupt pending,?,?" endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 0.--2. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." "0: No interrupt pending,1: LFOSCGOOD interrupt pending,?,?,?,?,?,?" endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 0.--2. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." "0: No interrupt pending,1: LFOSCGOOD interrupt pending,?,?,?,?,?,?" endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." "0: No interrupt pending,1: LFOSCGOOD interrupt pending,?,?" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--1. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." "0: No interrupt pending,1: LFOSCGOOD interrupt pending,?,?" endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 0.--2. "STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read of.." "0: No interrupt pending,1: LFOSCGOOD interrupt pending,?,?,?,?,?,?" endif group.long 0x1028++0x3 line.long 0x0 "SYSCTL_IMASK,Event IMASK" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 8. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 7. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 6. "HFCLKGOOD,HFCLK GOOD" "0,1" newline bitfld.long 0x0 5. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline bitfld.long 0x0 3. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 2. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 1. "BORLVL,BOR Level Indicator" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 3. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif bitfld.long 0x0 0. "LFOSCGOOD,LFOSC GOOD" "0,1" rgroup.long 0x1030++0x3 line.long 0x0 "SYSCTL_RIS,Event RIS" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) rbitfld.long 0x0 8. "HSCLKGOOD,HSCLK GOOD" "0,1" newline rbitfld.long 0x0 7. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 6. "HFCLKGOOD,HFCLK GOOD" "0,1" newline rbitfld.long 0x0 5. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline rbitfld.long 0x0 3. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 2. "FLASHDED,Flash Double Error Detect" "0,1" newline rbitfld.long 0x0 1. "BORLVL,BOR Level Indicator" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) rbitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 3. "LFXTGOOD,LFXT GOOD" "0,1" newline rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif rbitfld.long 0x0 0. "LFOSCGOOD,LFOSC GOOD" "0,1" rgroup.long 0x1038++0x3 line.long 0x0 "SYSCTL_MIS,Event MIS" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) rbitfld.long 0x0 8. "HSCLKGOOD,HSCLK GOOD" "0,1" newline rbitfld.long 0x0 7. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 6. "HFCLKGOOD,HFCLK GOOD" "0,1" newline rbitfld.long 0x0 5. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline rbitfld.long 0x0 3. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 2. "FLASHDED,Flash Double Error Detect" "0,1" newline rbitfld.long 0x0 1. "BORLVL,BOR Level Indicator" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline rbitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) rbitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 3. "LFXTGOOD,LFXT GOOD" "0,1" newline rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif rbitfld.long 0x0 0. "LFOSCGOOD,LFOSC GOOD" "0,1" wgroup.long 0x1040++0x3 line.long 0x0 "SYSCTL_ISET,Event ISET" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 8. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 7. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 6. "HFCLKGOOD,HFCLK GOOD" "0,1" newline bitfld.long 0x0 5. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline bitfld.long 0x0 3. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 2. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 1. "BORLVL,BOR Level Indicator" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 3. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif bitfld.long 0x0 0. "LFOSCGOOD,LFOSC GOOD" "0,1" wgroup.long 0x1048++0x3 line.long 0x0 "SYSCTL_ICLR,Event ICLR" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 8. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 7. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 6. "HFCLKGOOD,HFCLK GOOD" "0,1" newline bitfld.long 0x0 5. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline bitfld.long 0x0 3. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 2. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 1. "BORLVL,BOR Level Indicator" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 7. "HSCLKGOOD,HSCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 6. "SYSPLLGOOD,SYSPLL GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 6. "HSCLKGOOD,HSCLK GOOD" "0,1" newline bitfld.long 0x0 5. "HFCLKGOOD,HFCLK GOOD" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) bitfld.long 0x0 4. "LFXTGOOD,LFXT GOOD" "0,1" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 3. "LFXTGOOD,LFXT GOOD" "0,1" newline bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 3. "SRAMSEC,SRAM Single Error Correct" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 2. "FLASHSEC,Flash Single Error Correct" "0,1" newline bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 1. "ANACLKERR,Analog Clocking Consistency Error" "0,1" newline endif bitfld.long 0x0 0. "LFOSCGOOD,LFOSC GOOD" "0,1" sif (cpuis("MSPM0L110*")) rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" bitfld.long 0x0 0.--1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." "0: No NMI pending,1: BOR Threshold NMI pending,?,?" rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x1380++0x3 line.long 0x0 "SYSCTL_PMUOPAMP,GPAMP control" bitfld.long 0x0 10.--11. "CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: Chopping disabled,1: Normal chopping,2: ADC Assisted chopping,?" bitfld.long 0x0 8.--9. "CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: 16kHz,1: 8kHz,2: 4kHz,3: 2kHz" newline bitfld.long 0x0 6. "OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: GPAMP_OUT signal is not connected to the..,1: GPAMP_OUT signal is connected to the GPAMP_OUT pin" bitfld.long 0x0 4.--5. "RRI,RRI selects the rail-to-rail input mode." "0: PMOS input pairs,1: NMOS input pairs,2: Rail-to-rail mode,3: Sample channel 0" newline bitfld.long 0x0 2.--3. "NSEL,NSEL selects the GPAMP negative channel input." "0: GPAMP_OUT pin connected to negative channel,1: GPAMP_IN- pin connected to negative channel,2: GPAMP_OUT signal connected to negative channel,3: No channel selected" bitfld.long 0x0 1. "PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: Positive channel disabled,1: GPAMP_IN+ connected to positive channel" newline bitfld.long 0x0 0. "ENABLE,Set ENABLE to turn on the GPAMP." "0: GPAMP is disabled,1: GPAMP is enabled" group.long 0x4800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x4804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x4808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x4814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x88800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x88804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x88814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8C800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8C804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8C814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0L111*")) rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" bitfld.long 0x0 0.--2. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." "0: No NMI pending,1: BOR Threshold NMI pending,?,?,?,?,?,?" rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" newline bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" group.long 0x1108++0x3 line.long 0x0 "SYSCTL_HSCLKEN,High-speed clock (HSCLK) source enable/disable" bitfld.long 0x0 16. "USEEXTHFCLK,USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously." "0: Use HFXT as the HFCLK source,1: Use the HFCLK_IN digital clock input as the.." group.long 0x1114++0x3 line.long 0x0 "SYSCTL_LFCLKCFG,Low frequency crystal oscillator (LFXT) configuration" bitfld.long 0x0 8. "LOWCAP,LOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf LOWCAP may be set for reduced power consumption." "0: LFXT low capacitance mode is disabled,1: LFXT low capacitance mode is enabled" bitfld.long 0x0 4. "MONITOR,MONITOR enables or disables the LFCLK monitor which continuously checks LFXT or LFCLK_IN for a clock stuck fault." "0: Clock monitor is disabled,1: Clock monitor is enabled" newline bitfld.long 0x0 0.--1. "XT1DRIVE,XT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength." "0: Lowest drive and current,1: Lower drive and current,2: Higher drive and current,3: Highest drive and current" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x1314++0x7 line.long 0x0 "SYSCTL_LFXTCTL,LFXT and LFCLK control" bitfld.long 0x0 1. "SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "?,1: Use LFXT as the LFCLK source" bitfld.long 0x0 0. "STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: LFXT not started,1: Start LFXT" line.long 0x4 "SYSCTL_EXLFCTL,LFCLK_IN and LFCLK control" bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x3000++0x3 line.long 0x0 "SYSCTL_FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash" group.long 0x3018++0xF line.long 0x0 "SYSCTL_FRXPROTMAINSTART,Flash RX Protection Start Address" hexmask.long.word 0x0 6.--21. 1. "ADDR,Flash RX Protection Start Address 64B granularity" line.long 0x4 "SYSCTL_FRXPROTMAINEND,Flash RX Protection End Address" hexmask.long.word 0x4 6.--21. 1. "ADDR,Flash RX Protection End Address 64B granularity" line.long 0x8 "SYSCTL_FIPPROTMAINSTART,Flash IP Protection Start Address" hexmask.long.word 0x8 6.--21. 1. "ADDR,Flash IP Protection Start Address 64B granularity" line.long 0xC "SYSCTL_FIPPROTMAINEND,Flash IP Protection End Address" hexmask.long.word 0xC 6.--21. 1. "ADDR,Flash IP Protection End Address 64B granularity" wgroup.long 0x3038++0x7 line.long 0x0 "SYSCTL_FLBANKSWPPOLICY,Flash Bank Swap Policy" bitfld.long 0x0 0. "DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping" line.long 0x4 "SYSCTL_FLBANKSWP,Flash MAIN bank address swap" bitfld.long 0x4 0. "USEUPPER,1: Use Upper Bank as Logical 0" "0: Normal (default) memory map addressing scheme,1: Use Upper Bank as Logical 0" wgroup.long 0x3044++0x3 line.long 0x0 "SYSCTL_FWENABLE,Security Firewall Enable Register" bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR" bitfld.long 0x0 6. "FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" rgroup.long 0x3048++0x3 line.long 0x0 "SYSCTL_SECSTATUS,Security Configuration status" bitfld.long 0x0 12. "FLBANKSWP,1: Upper and Lower Banks have been swapped" "?,1: Upper and Lower Banks have been swapped" newline bitfld.long 0x0 10. "FLBANKSWPPOLICY,1: Upper and Lower Banks allowed to be swapped" "?,1: Upper and Lower Banks allowed to be swapped" newline bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: SRAM Boundary MMR Locked" "?,1: SRAM Boundary MMR Locked" bitfld.long 0x0 6. "FLIPPROT,1: Flash IP Protection Active" "?,1: Flash IP Protection Active" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" bitfld.long 0x0 2. "CSCEXISTS,1: CSC Exists in the system" "0: System does not have a CSC,1: CSC Exists in the system" newline bitfld.long 0x0 0. "INITDONE,1: CSC has been completed" "0: INIT is not yet done,1: CSC has been completed" wgroup.long 0x3060++0x3 line.long 0x0 "SYSCTL_INITDONE,INITCODE PASS" bitfld.long 0x0 0. "PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: INITCODE PASS" group.long 0x4800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x4804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x4808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x4814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0L122*")) rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" bitfld.long 0x0 0.--2. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." "0: No NMI pending,1: BOR Threshold NMI pending,?,?,?,?,?,?" rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 6. "VBATUP,VBAT Power On" "0,1" bitfld.long 0x0 5. "VBATDN,VBAT Power Off" "0,1" newline bitfld.long 0x0 4. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 6. "VBATUP,VBAT Power On" "0,1" bitfld.long 0x0 5. "VBATDN,VBAT Power Off" "0,1" newline bitfld.long 0x0 4. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 6. "VBATUP,VBAT Power On" "0,1" bitfld.long 0x0 5. "VBATDN,VBAT Power Off" "0,1" newline bitfld.long 0x0 4. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" group.long 0x1108++0xF line.long 0x0 "SYSCTL_HSCLKEN,High-speed clock (HSCLK) source enable/disable" bitfld.long 0x0 16. "USEEXTHFCLK,USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously." "0: Use HFXT as the HFCLK source,1: Use the HFCLK_IN digital clock input as the.." bitfld.long 0x0 0. "HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: Disable the HFXT,1: Enable the HFXT" line.long 0x4 "SYSCTL_HSCLKCFG,High-speed clock (HSCLK) source selection" bitfld.long 0x4 0. "HSCLKSEL,HSCLKSEL selects the HSCLK source (SYSPLL or HFCLK)." "?,1: HSCLK is sourced from the HFCLK" line.long 0x8 "SYSCTL_HFCLKCLKCFG,High-frequency clock (HFCLK) configuration" bitfld.long 0x8 28. "HFCLKFLTCHK,HFCLKFLTCHK enables or disables the HFCLK startup monitor." "0: HFCLK startup is not checked,1: HFCLK startup is checked" bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." line.long 0xC "SYSCTL_LFCLKCFG,Low frequency crystal oscillator (LFXT) configuration" bitfld.long 0xC 8. "LOWCAP,LOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf LOWCAP may be set for reduced power consumption." "0: LFXT low capacitance mode is disabled,1: LFXT low capacitance mode is enabled" bitfld.long 0xC 4. "MONITOR,MONITOR enables or disables the LFCLK monitor which continuously checks LFXT or LFCLK_IN for a clock stuck fault." "0: Clock monitor is disabled,1: Clock monitor is enabled" newline bitfld.long 0xC 0.--1. "XT1DRIVE,XT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength." "0: Lowest drive and current,1: Lower drive and current,2: Higher drive and current,3: Highest drive and current" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x1314++0x7 line.long 0x0 "SYSCTL_LFXTCTL,LFXT and LFCLK control" bitfld.long 0x0 1. "SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "?,1: Use LFXT as the LFCLK source" bitfld.long 0x0 0. "STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: LFXT not started,1: Start LFXT" line.long 0x4 "SYSCTL_EXLFCTL,LFCLK_IN and LFCLK control" bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x3000++0x3 line.long 0x0 "SYSCTL_FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash" group.long 0x3018++0xF line.long 0x0 "SYSCTL_FRXPROTMAINSTART,Flash RX Protection Start Address" hexmask.long.word 0x0 6.--21. 1. "ADDR,Flash RX Protection Start Address 64B granularity" line.long 0x4 "SYSCTL_FRXPROTMAINEND,Flash RX Protection End Address" hexmask.long.word 0x4 6.--21. 1. "ADDR,Flash RX Protection End Address 64B granularity" line.long 0x8 "SYSCTL_FIPPROTMAINSTART,Flash IP Protection Start Address" hexmask.long.word 0x8 6.--21. 1. "ADDR,Flash IP Protection Start Address 64B granularity" line.long 0xC "SYSCTL_FIPPROTMAINEND,Flash IP Protection End Address" hexmask.long.word 0xC 6.--21. 1. "ADDR,Flash IP Protection End Address 64B granularity" wgroup.long 0x3038++0x7 line.long 0x0 "SYSCTL_FLBANKSWPPOLICY,Flash Bank Swap Policy" bitfld.long 0x0 0. "DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping" line.long 0x4 "SYSCTL_FLBANKSWP,Flash MAIN bank address swap" bitfld.long 0x4 0. "USEUPPER,1: Use Upper Bank as Logical 0" "0: Normal (default) memory map addressing scheme,1: Use Upper Bank as Logical 0" wgroup.long 0x3044++0x3 line.long 0x0 "SYSCTL_FWENABLE,Security Firewall Enable Register" bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR" bitfld.long 0x0 6. "FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" rgroup.long 0x3048++0x3 line.long 0x0 "SYSCTL_SECSTATUS,Security Configuration status" bitfld.long 0x0 12. "FLBANKSWP,1: Upper and Lower Banks have been swapped" "?,1: Upper and Lower Banks have been swapped" newline bitfld.long 0x0 10. "FLBANKSWPPOLICY,1: Upper and Lower Banks allowed to be swapped" "?,1: Upper and Lower Banks allowed to be swapped" newline bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: SRAM Boundary MMR Locked" "?,1: SRAM Boundary MMR Locked" bitfld.long 0x0 6. "FLIPPROT,1: Flash IP Protection Active" "?,1: Flash IP Protection Active" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" bitfld.long 0x0 2. "CSCEXISTS,1: CSC Exists in the system" "0: System does not have a CSC,1: CSC Exists in the system" newline bitfld.long 0x0 0. "INITDONE,1: CSC has been completed" "0: INIT is not yet done,1: CSC has been completed" wgroup.long 0x3060++0x3 line.long 0x0 "SYSCTL_INITDONE,INITCODE PASS" bitfld.long 0x0 0. "PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: INITCODE PASS" group.long 0x4800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x4804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x4808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x4814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x70800++0x3 line.long 0x0 "SYSCTL_MGMT_LCD_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x70804++0x3 line.long 0x0 "SYSCTL_MGMT_LCD_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x70814++0x3 line.long 0x0 "SYSCTL_MGMT_LCD_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8C800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8C804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8C814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8E800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8E804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8E814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA4800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA4804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA4814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF4800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF4804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF4808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF4814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x102800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x102804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x102808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x102814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x104800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x104804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x104808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x104814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x10A800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x10A804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x10A808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x10A814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0L130*")) rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" bitfld.long 0x0 0.--1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." "0: No NMI pending,1: BOR Threshold NMI pending,?,?" rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x1380++0x3 line.long 0x0 "SYSCTL_PMUOPAMP,GPAMP control" bitfld.long 0x0 10.--11. "CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: Chopping disabled,1: Normal chopping,2: ADC Assisted chopping,?" bitfld.long 0x0 8.--9. "CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: 16kHz,1: 8kHz,2: 4kHz,3: 2kHz" newline bitfld.long 0x0 6. "OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: GPAMP_OUT signal is not connected to the..,1: GPAMP_OUT signal is connected to the GPAMP_OUT pin" bitfld.long 0x0 4.--5. "RRI,RRI selects the rail-to-rail input mode." "0: PMOS input pairs,1: NMOS input pairs,2: Rail-to-rail mode,3: Sample channel 0" newline bitfld.long 0x0 2.--3. "NSEL,NSEL selects the GPAMP negative channel input." "0: GPAMP_OUT pin connected to negative channel,1: GPAMP_IN- pin connected to negative channel,2: GPAMP_OUT signal connected to negative channel,3: No channel selected" bitfld.long 0x0 1. "PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: Positive channel disabled,1: GPAMP_IN+ connected to positive channel" newline bitfld.long 0x0 0. "ENABLE,Set ENABLE to turn on the GPAMP." "0: GPAMP is disabled,1: GPAMP is enabled" group.long 0x4800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x4804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x4808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x4814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x88800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x88804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x88814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8C800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8C804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8C814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0L134*")) rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" bitfld.long 0x0 0.--1. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." "0: No NMI pending,1: BOR Threshold NMI pending,?,?" rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x1380++0x3 line.long 0x0 "SYSCTL_PMUOPAMP,GPAMP control" bitfld.long 0x0 10.--11. "CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: Chopping disabled,1: Normal chopping,2: ADC Assisted chopping,?" bitfld.long 0x0 8.--9. "CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: 16kHz,1: 8kHz,2: 4kHz,3: 2kHz" newline bitfld.long 0x0 6. "OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: GPAMP_OUT signal is not connected to the..,1: GPAMP_OUT signal is connected to the GPAMP_OUT pin" bitfld.long 0x0 4.--5. "RRI,RRI selects the rail-to-rail input mode." "0: PMOS input pairs,1: NMOS input pairs,2: Rail-to-rail mode,3: Sample channel 0" newline bitfld.long 0x0 2.--3. "NSEL,NSEL selects the GPAMP negative channel input." "0: GPAMP_OUT pin connected to negative channel,1: GPAMP_IN- pin connected to negative channel,2: GPAMP_OUT signal connected to negative channel,3: No channel selected" bitfld.long 0x0 1. "PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: Positive channel disabled,1: GPAMP_IN+ connected to positive channel" newline bitfld.long 0x0 0. "ENABLE,Set ENABLE to turn on the GPAMP." "0: GPAMP is disabled,1: GPAMP is enabled" group.long 0x4800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x4804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x4808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x4814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x88800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x88804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x88814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8C800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8C804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8C814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0L222*")) rgroup.long 0x1050++0x3 line.long 0x0 "SYSCTL_NMIIIDX,NMI interrupt index" bitfld.long 0x0 0.--2. "STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the NMIIIDX.." "0: No NMI pending,1: BOR Threshold NMI pending,?,?,?,?,?,?" rgroup.long 0x1060++0x3 line.long 0x0 "SYSCTL_NMIRIS,NMI raw interrupt status" bitfld.long 0x0 6. "VBATUP,VBAT Power On" "0,1" bitfld.long 0x0 5. "VBATDN,VBAT Power Off" "0,1" newline bitfld.long 0x0 4. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 0. "BORLVL,Raw status of the BORLVL NMI" "0: No interrupt pending,1: Interrupt pending" wgroup.long 0x1070++0x3 line.long 0x0 "SYSCTL_NMIISET,NMI interrupt set" bitfld.long 0x0 6. "VBATUP,VBAT Power On" "0,1" bitfld.long 0x0 5. "VBATDN,VBAT Power Off" "0,1" newline bitfld.long 0x0 4. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 0. "BORLVL,Set the BORLVL NMI" "0: Writing 0h hs no effect,1: Set interrupt" wgroup.long 0x1078++0x3 line.long 0x0 "SYSCTL_NMIICLR,NMI interrupt clear" bitfld.long 0x0 6. "VBATUP,VBAT Power On" "0,1" bitfld.long 0x0 5. "VBATDN,VBAT Power Off" "0,1" newline bitfld.long 0x0 4. "SRAMDED,SRAM Double Error Detect" "0,1" bitfld.long 0x0 3. "FLASHDED,Flash Double Error Detect" "0,1" newline bitfld.long 0x0 2. "LFCLKFAIL,LFXT-EXLF Monitor Fail" "0,1" bitfld.long 0x0 1. "WWDT0,Watch Dog 0 Fault" "0,1" newline bitfld.long 0x0 0. "BORLVL,Clr the BORLVL NMI" "0: Writing 0h hs no effect,1: Clear interrupt" group.long 0x1108++0xF line.long 0x0 "SYSCTL_HSCLKEN,High-speed clock (HSCLK) source enable/disable" bitfld.long 0x0 16. "USEEXTHFCLK,USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously." "0: Use HFXT as the HFCLK source,1: Use the HFCLK_IN digital clock input as the.." bitfld.long 0x0 0. "HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: Disable the HFXT,1: Enable the HFXT" line.long 0x4 "SYSCTL_HSCLKCFG,High-speed clock (HSCLK) source selection" bitfld.long 0x4 0. "HSCLKSEL,HSCLKSEL selects the HSCLK source (SYSPLL or HFCLK)." "?,1: HSCLK is sourced from the HFCLK" line.long 0x8 "SYSCTL_HFCLKCLKCFG,High-frequency clock (HFCLK) configuration" bitfld.long 0x8 28. "HFCLKFLTCHK,HFCLKFLTCHK enables or disables the HFCLK startup monitor." "0: HFCLK startup is not checked,1: HFCLK startup is checked" bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." line.long 0xC "SYSCTL_LFCLKCFG,Low frequency crystal oscillator (LFXT) configuration" bitfld.long 0xC 8. "LOWCAP,LOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf LOWCAP may be set for reduced power consumption." "0: LFXT low capacitance mode is disabled,1: LFXT low capacitance mode is enabled" bitfld.long 0xC 4. "MONITOR,MONITOR enables or disables the LFCLK monitor which continuously checks LFXT or LFCLK_IN for a clock stuck fault." "0: Clock monitor is disabled,1: Clock monitor is enabled" newline bitfld.long 0xC 0.--1. "XT1DRIVE,XT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength." "0: Lowest drive and current,1: Lower drive and current,2: Higher drive and current,3: Highest drive and current" rgroup.long 0x1150++0x3 line.long 0x0 "SYSCTL_FCC,Frequency clock counter (FCC) count" hexmask.long.tbyte 0x0 0.--21. 1. "DATA,Frequency clock counter (FCC) count value." group.long 0x1178++0x3 line.long 0x0 "SYSCTL_SRAMBOUNDARY,SRAM Write Boundary" hexmask.long.word 0x0 5.--19. 1. "ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have.." rgroup.long 0x120C++0x3 line.long 0x0 "SYSCTL_DEDERRADDR,Memory DED Address" rgroup.long 0x1220++0x3 line.long 0x0 "SYSCTL_RSTCAUSE,Reset cause" hexmask.long.byte 0x0 0.--4. 1. "ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read." wgroup.long 0x130C++0x3 line.long 0x0 "SYSCTL_BORCLRCMD,Set the BOR threshold" bitfld.long 0x0 0. "GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: Issue clear" wgroup.long 0x1314++0x7 line.long 0x0 "SYSCTL_LFXTCTL,LFXT and LFCLK control" bitfld.long 0x0 1. "SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "?,1: Use LFXT as the LFCLK source" bitfld.long 0x0 0. "STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: LFXT not started,1: Start LFXT" line.long 0x4 "SYSCTL_EXLFCTL,LFCLK_IN and LFCLK control" bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" wgroup.long 0x132C++0x3 line.long 0x0 "SYSCTL_FCCCMD,Frequency clock counter start capture" bitfld.long 0x0 0. "GO,Set GO to start a capture with the frequency clock counter (FCC)." "0,1" group.long 0x3000++0x3 line.long 0x0 "SYSCTL_FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash" group.long 0x3018++0xF line.long 0x0 "SYSCTL_FRXPROTMAINSTART,Flash RX Protection Start Address" hexmask.long.word 0x0 6.--21. 1. "ADDR,Flash RX Protection Start Address 64B granularity" line.long 0x4 "SYSCTL_FRXPROTMAINEND,Flash RX Protection End Address" hexmask.long.word 0x4 6.--21. 1. "ADDR,Flash RX Protection End Address 64B granularity" line.long 0x8 "SYSCTL_FIPPROTMAINSTART,Flash IP Protection Start Address" hexmask.long.word 0x8 6.--21. 1. "ADDR,Flash IP Protection Start Address 64B granularity" line.long 0xC "SYSCTL_FIPPROTMAINEND,Flash IP Protection End Address" hexmask.long.word 0xC 6.--21. 1. "ADDR,Flash IP Protection End Address 64B granularity" wgroup.long 0x3038++0x7 line.long 0x0 "SYSCTL_FLBANKSWPPOLICY,Flash Bank Swap Policy" bitfld.long 0x0 0. "DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping" line.long 0x4 "SYSCTL_FLBANKSWP,Flash MAIN bank address swap" bitfld.long 0x4 0. "USEUPPER,1: Use Upper Bank as Logical 0" "0: Normal (default) memory map addressing scheme,1: Use Upper Bank as Logical 0" wgroup.long 0x3044++0x3 line.long 0x0 "SYSCTL_FWENABLE,Security Firewall Enable Register" bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR" bitfld.long 0x0 6. "FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" rgroup.long 0x3048++0x3 line.long 0x0 "SYSCTL_SECSTATUS,Security Configuration status" bitfld.long 0x0 12. "FLBANKSWP,1: Upper and Lower Banks have been swapped" "?,1: Upper and Lower Banks have been swapped" newline bitfld.long 0x0 10. "FLBANKSWPPOLICY,1: Upper and Lower Banks allowed to be swapped" "?,1: Upper and Lower Banks allowed to be swapped" newline bitfld.long 0x0 8. "SRAMBOUNDARYLOCK,1: SRAM Boundary MMR Locked" "?,1: SRAM Boundary MMR Locked" bitfld.long 0x0 6. "FLIPPROT,1: Flash IP Protection Active" "?,1: Flash IP Protection Active" newline bitfld.long 0x0 4. "FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active" bitfld.long 0x0 2. "CSCEXISTS,1: CSC Exists in the system" "0: System does not have a CSC,1: CSC Exists in the system" newline bitfld.long 0x0 0. "INITDONE,1: CSC has been completed" "0: INIT is not yet done,1: CSC has been completed" wgroup.long 0x3060++0x3 line.long 0x0 "SYSCTL_INITDONE,INITCODE PASS" bitfld.long 0x0 0. "PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: INITCODE PASS" group.long 0x4800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x4804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x4808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x4814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B1MSPS0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x70800++0x3 line.long 0x0 "SYSCTL_MGMT_LCD_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x70804++0x3 line.long 0x0 "SYSCTL_MGMT_LCD_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x70814++0x3 line.long 0x0 "SYSCTL_MGMT_LCD_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8C800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8C804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8C814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8E800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8E804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x8E814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSPLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA4800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA4804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA4814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF4800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF4804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF4808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF4814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x102800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x102804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x102808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x102814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x104800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x104804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x104808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x104814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x10A800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x10A804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x10A808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x10A814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif group.long 0x1100++0x7 line.long 0x0 "SYSCTL_SYSOSCCFG,SYSOSC Configuration" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 18. "BLOCKASYNCACOMP,Block all ACOMP async requests from enabling SYSOSC via hardware ie keep running from LFCLK if UART is requester" "0,1" newline bitfld.long 0x0 17. "BLOCKASYNCUART,Block all UART async requests from enabling SYSOSC via hardware ie keep running from LFCLK if UART is requester" "0,1" newline bitfld.long 0x0 11. "FASTCLKONAREQ,Force BASE (or higher) Freqency when there is async sysosc request 0: Leave as current frequency 1: Force BASE or current that is higher" "0: Leave as current frequency,1: Force BASE or current that is higher" newline bitfld.long 0x0 0.--1. "FREQ,Freq Target: 0: BASE 1: 4M 2: USER 3: Reserved for Turbo 48MHz" "0: BASE,1: 4M,2: USER,3: Reserved for Turbo 48MHz" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 17. "FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: An interrupt to the CPU will not assert a fast..,1: An interrupt to the CPU will assert a fast clock.." newline endif bitfld.long 0x0 16. "BLOCKASYNCALL,Block all async requests from enabling SYSOSC via hardware ie keep running from LFCLK" "0,1" newline bitfld.long 0x0 10. "DISABLE,Disable SYSOSC to run all power modes with LFCLK" "0,1" newline bitfld.long 0x0 9. "DISABLESTOP,Disable SYSOSC when in STOP mode to allow STOP with LFCLK" "0,1" newline bitfld.long 0x0 8. "USE4MHZSTOP,SYOSC Frequency during stop 0: 32M 1: 4M" "0: 32M,1: 4M" newline sif (cpuis("MSPM0G110*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),3: Turbo frequency (48MHz)" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),3: Turbo frequency (48MHz)" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),3: Turbo frequency (48MHz)" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 0.--1. "FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: Base frequency (32MHz),1: Low frequency (4MHz),2: User-trimmed frequency (16 or 24 MHz),?" endif line.long 0x4 "SYSCTL_MCLKCFG,Configuration related to MCLK" sif (cpuis("MSPM0G110*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x4 22. "MCLKDEADCHK,MCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled." "0: The MCLK dead check monitor is disabled,1: The MCLK dead check monitor is enabled" newline endif bitfld.long 0x4 21. "STOPCLKSTBY,STOP ULPCLK Root during STANDBY Only wake on ASYNC IO Events" "0,1" newline bitfld.long 0x4 20. "USELFCLK,Low Frequency Clock Selected for MCLK" "0,1" newline sif (cpuis("MSPM0L111*")) bitfld.long 0x4 16. "USEHSCLK,USEHSCLK together with USELFCLK sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes." "0: MCLK will not use the high speed clock (HSCLK),1: MCLK will use the high speed clock (HSCLK) in.." newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x4 16. "USEHSCLK,USEHSCLK together with USELFCLK sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes." "0: MCLK will not use the high speed clock (HSCLK),1: MCLK will use the high speed clock (HSCLK) in.." newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x4 16. "USEHSCLK,USEHSCLK together with USELFCLK sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes." "0: MCLK will not use the high speed clock (HSCLK),1: MCLK will use the high speed clock (HSCLK) in.." newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) bitfld.long 0x4 16. "USEHSCLK,High Speed Clock Selected for MCLK (HFCLK PLL ...)" "0,1" newline endif bitfld.long 0x4 12. "USEMFTICK,USE the MFTICK feature (this will limit MDIV options)" "0,1" newline sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0L110*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0L111*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0L130*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0L134*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK. FLASHWAIT has no effect when MCLK is sourced from SYSOSC or LFCLK." newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x4 8.--11. 1. "FLASHWAIT,Flash wait states when using a high speed clock source - HFCLK or PLL" newline bitfld.long 0x4 4.--5. "UDIV,UDIV Divider 0: MCLK 1: MCLK div 22: MCLK div 3 when USEHSCLK is TRUE" "0: MCLK,1: MCLK div,?,?" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x4 4.--5. "UDIV,UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK." "0: ULPCLK is not divided and is equal to MCLK,1: ULPCLK is MCLK/2 (divided-by-2),2: ULPCLK is MCLK/3 (divided-by-3),?" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x4 4.--5. "UDIV,UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK." "0: ULPCLK is not divided and is equal to MCLK,1: ULPCLK is MCLK/2 (divided-by-2),2: ULPCLK is MCLK/3 (divided-by-3),?" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x4 4.--5. "UDIV,UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK." "0: ULPCLK is not divided and is equal to MCLK,1: ULPCLK is MCLK/2 (divided-by-2),?,?" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x4 4.--5. "UDIV,UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK." "0: ULPCLK is not divided and is equal to MCLK,1: ULPCLK is MCLK/2 (divided-by-2),2: ULPCLK is MCLK/3 (divided-by-3),?" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x4 4.--5. "UDIV,UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK." "0: ULPCLK is not divided and is equal to MCLK,1: ULPCLK is MCLK/2 (divided-by-2),2: ULPCLK is MCLK/3 (divided-by-3),?" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x4 4.--5. "UDIV,UDIV specifies the ULPCLK divider when MCLK is sourced from HSCLK. UDIV has no effect when MCLK is sourced from SYSOSC or LFCLK." "0: ULPCLK is not divided and is equal to MCLK,1: ULPCLK is MCLK/2 (divided-by-2),?,?" newline endif hexmask.long.byte 0x4 0.--3. 1. "MDIV,MDIV Divider 1..16 when RUN-SLEEP" sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) group.long 0x1108++0xF line.long 0x0 "SYSCTL_HSCLKEN,High Speed Clock Configuration" bitfld.long 0x0 16. "USEEXTHFCLK,Use External Pin as High Frequency Oscillator Source(HFCLK)" "0,1" bitfld.long 0x0 8. "SYSPLLEN,Enable the SYSTEM PLL" "0,1" newline bitfld.long 0x0 0. "HFXTEN,Enable the HFXT Crystal" "0,1" line.long 0x4 "SYSCTL_HSCLKCFG,High Speed Clock Configuration" bitfld.long 0x4 0. "HSCLKSEL,High Speed Clock Source 0: SYSPLL 1:HFCLKCLK" "0: SYSPLL,1: HFCLKCLK" line.long 0x8 "SYSCTL_HFCLKCLKCFG,High Frequency OSC Clock Configuration" bitfld.long 0x8 28. "HFCLKFLTCHK,Check for stuck fault on HFCLK related pins" "0,1" newline sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXT startup time in 64 usec resolution" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x8 12.--13. "HFXTRSEL,HFXT Range Select" "0: 4MHz <= HFXT frequency <= 8MHz,1: 8MHz < HFXT frequency <= 16MHz,2: 16MHz < HFXT frequency <= 32MHz,3: 32MHz < HFXT frequency <= 48MHz" newline endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." newline endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x8 0.--7. 1. "HFXTTIME,HFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK) HFXT will be checked after this time expires." endif line.long 0xC "SYSCTL_LFCLKCFG,Low Frequency External Clock Configuration" bitfld.long 0xC 8. "LOWCAP,Can be enabled if CAP is less than 3pf for reduced power" "0,1" bitfld.long 0xC 4. "MONITOR,Use Monitor for LFXT EXLF failure" "0,1" newline bitfld.long 0xC 0.--1. "XT1DRIVE,Drive strength and power consumption option" "0: Lowest Drive and Current,1: Lower Drive and Current,2: Higher Drive and Current,3: Highest Drive and Current" group.long 0x1120++0xF line.long 0x0 "SYSCTL_SYSPLLCFG0,System PLL Configuration 0 MMR" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,Final Divider for CLK2X Output 1-16" hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,Final Divider for CLK1 Output 1-16" newline hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,Final Divider for CLK0 Output 1-16" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output." newline hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output." newline hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output." newline hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output." newline hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output." newline hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 16.--19. 1. "RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output." newline hexmask.long.byte 0x0 12.--15. 1. "RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output." endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 8.--11. 1. "RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output." endif newline bitfld.long 0x0 6. "ENABLECLK2X,PLL CLK2X Output enabled" "0,1" newline bitfld.long 0x0 5. "ENABLECLK1,PLL CLK1 Output enabled" "0,1" bitfld.long 0x0 4. "ENABLECLK0,PLL CLK0 Output enabled" "0,1" newline bitfld.long 0x0 1. "MCLK2XVCO,Use PLL CLK2X PATH as source for MCLK" "0,1" bitfld.long 0x0 0. "SYSPLLREF,System PLL Reference Clock Source 0: SYSOSC 1:HFCLK" "0: SYSOSC,1: HFCLK" line.long 0x4 "SYSCTL_SYSPLLCFG1,System PLL Configuration 1 MMR" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,PLL Feedback Clock Divider 1-127 by 1" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,QDIV selects the SYSPLL feedback path divider." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,QDIV selects the SYSPLL feedback path divider." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,QDIV selects the SYSPLL feedback path divider." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,QDIV selects the SYSPLL feedback path divider." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,QDIV selects the SYSPLL feedback path divider." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x4 8.--14. 1. "QDIV,QDIV selects the SYSPLL feedback path divider." endif newline bitfld.long 0x4 0.--1. "PDIV,PLL Reference Clock Divider 1 2 4 8" "0,1,2,3" line.long 0x8 "SYSCTL_SYSPLLPARAM0,System PLL Paramater 0 MMR --- Data from Flash Table Lookup" bitfld.long 0x8 31. "CAPBOVERRIDE,Override Enable For Cap B" "0,1" hexmask.long.byte 0x8 24.--28. 1. "CAPBVAL,Override Value for Cap B" newline hexmask.long.byte 0x8 16.--21. 1. "CPCURRENT,Charge Pump Current" hexmask.long.byte 0x8 8.--13. 1. "STARTTIMELP,Startup time from Low Power Exit to Locked Clock in resolution of 1usec" newline hexmask.long.byte 0x8 0.--5. 1. "STARTTIME,Startup time from Enable to Locked Clock in resolution of 1usec" line.long 0xC "SYSCTL_SYSPLLPARAM1,System PLL Paramater 1 MMR --- Data from Flash Table Lookup" hexmask.long.byte 0xC 24.--31. 1. "LPFRESC,Loop Filter Res C" hexmask.long.word 0xC 8.--17. 1. "LPFRESA,Loop Filter Res A" newline hexmask.long.byte 0xC 0.--4. 1. "LPFCAPA,Loop Filter Cap A" wgroup.long 0x1314++0x7 line.long 0x0 "SYSCTL_LFXTCTL,LFXT Control -- Only BOR Level Reset will clear" bitfld.long 0x0 1. "SETUSELFXT,Use LFXT" "?,1: Use LFXT as 32KHz source" bitfld.long 0x0 0. "STARTLFXT,Start LFXT" "?,1: Start LFXT" line.long 0x4 "SYSCTL_EXLFCTL,EX LF Control -- Only BOR Level Reset will clear" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 2. "SETUSEEXLF,Use external LF CLK IN" "?,1: Use External LF source" endif sif (cpuis("MSPM0G150*")) bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" endif sif (cpuis("MSPM0G310*")) bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" endif sif (cpuis("MSPM0G351*")) bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x4 0. "SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: Use LFCLK_IN as the LFCLK source" endif endif group.long 0x1138++0xB line.long 0x0 "SYSCTL_GENCLKCFG,General Clock Configuration" sif (cpuis("MSPM0L111*")) bitfld.long 0x0 29. "FCCLFCLKSRC,FCCLFCLKSRC selects between SYSTEM LFCLK and EXTERNAL SOURCED LFCLK." "0,1" newline endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0L110*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0L111*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0L130*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0L134*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x0 24.--28. 1. "FCCTRIGCNT,FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified." newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 22.--23. "ANACPUMPCFG,ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method." "0: VBOOST is enabled on request from a COMP GPAMP..,1: VBOOST is enabled when the device is in RUN or..,2: VBOOST is always enabled,?" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK4MFPCLKDIV selects the divider applied to HFCLK when HFCLK is used as the MFPCLK source. Integer dividers from /1 to /16 may be selected." newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 21. "FCCLVLTRIG,FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode." "0: Rising edge to rising edge triggered,1: Level triggered" newline bitfld.long 0x0 20. "FCCTRIGSRC,FCCTRIGSRC selects the frequency clock counter (FCC) trigger source." "0: FCC trigger is the external pin,1: FCC trigger is the LFCLK" newline hexmask.long.byte 0x0 16.--19. 1. "FCCSELCLK,FCCSELCLK selectes the frequency clock counter (FCC) clock source." newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) hexmask.long.byte 0x0 12.--15. 1. "HFCLK4MFPCLKDIV,HFCLK Divider 1..16" newline bitfld.long 0x0 0.--2. "EXCLKSRC,External Clock Source Select" "?,1: NOTE: This must be divided in post divider,?,3: NOTE: This must be divided in post divider,?,5: NOTE: Must be 48MHz or below,?,?" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 9. "MFPCLKSRC,MFPCLKSRC selects the MFPCLK (middle frequency precision clock) source." "0: MFPCLK is sourced from SYSOSC,1: MFPCLK is sourced from HFCLK" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 9. "MFPCLKSRC,MFPCLKSRC selects the MFPCLK (middle frequency precision clock) source." "0: MFPCLK is sourced from SYSOSC,1: MFPCLK is sourced from HFCLK" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 9. "MFPCLKSRC,MFPCLKSRC selects the MFPCLK (middle frequency precision clock) source." "0: MFPCLK is sourced from SYSOSC,1: MFPCLK is sourced from HFCLK" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) bitfld.long 0x0 9. "MFPCLKSRC,Source for MFPCLK Clock" "0,1" newline bitfld.long 0x0 8. "CANCLKSRC,Source for CAN Clock" "0,1" newline endif bitfld.long 0x0 7. "EXCLKDIVEN,1: Enable divide 0: Pass Src Clock Through" "0: Pass Src Clock Through,1: Enable divide" newline bitfld.long 0x0 4.--6. "EXCLKDIVVAL" "0,1,2,3,4,5,6,7" newline sif (cpuis("MSPM0G110*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,5: CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be..,?,?" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,5: CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be..,?,?" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,5: CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be <=48MHz),?,?" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,5: CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be..,?,?" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,5: CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be..,?,?" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,5: CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be <=48MHz),?,?" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),?,?,?,?" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,?,?,?" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,?,?,?" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),?,?,?,?" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),?,?,?,?" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 0.--2. "EXCLKSRC,EXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK and MFPCLK require the CLK_OUT divider (EXCLKDIVEN) to be enabled" "0: CLK_OUT is SYSOSC,1: CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled),2: CLK_OUT is LFCLK,3: CLK_OUT is MFPCLK (EXCLKDIVEN must be enabled),4: CLK_OUT is HFCLK,?,?,?" endif line.long 0x4 "SYSCTL_GENCLKEN,General Clock Enables" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 4. "MFCLKEN,Enable the MFCLK" "0,1" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x4 4. "MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: MFPCLK is disabled,1: MFPCLK is enabled" newline endif bitfld.long 0x4 0. "EXCLKEN,Enable the External Clock Output" "0,1" line.long 0x8 "SYSCTL_PMODECFG,Power Mode Configurations" sif (cpuis("MSPM0L110*")) bitfld.long 0x8 5. "SYSSRAMONSTOP,SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode." "0: SRAM controller is disabled in STOP mode (lower..,1: SRAM controller is left enabled in STOP mode.." newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x8 5. "SYSSRAMONSTOP,SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode." "0: SRAM controller is disabled in STOP mode (lower..,1: SRAM controller is left enabled in STOP mode.." newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x8 5. "SYSSRAMONSTOP,SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode." "0: SRAM controller is disabled in STOP mode (lower..,1: SRAM controller is left enabled in STOP mode.." newline endif bitfld.long 0x8 0.--1. "DSLEEP,Action to be taken on DEEPSLEEP 0: STOP 1:STANDBY 2: SHUTDOWN 3: Reserved" "0: STOP,1: STANDBY,2: SHUTDOWN,3: Reserved" group.long 0x1170++0x3 line.long 0x0 "SYSCTL_SYSOSCTRIMUSER,SYSOSC Trim Values specified by user" hexmask.long.word 0x0 20.--28. 1. "RDIV,FCL RDIV TRIM - Changes per frequency target" newline hexmask.long.byte 0x0 16.--19. 1. "RESFINE,Resister Coarse TRIM - Changes per frequency target" newline hexmask.long.byte 0x0 8.--13. 1. "RESCOARSE,Resister Coarse TRIM - Changes per frequency target" newline bitfld.long 0x0 4.--6. "CAP,CAP TRIM - Changes per frequency target" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "FREQ,Freq Target: 0: NOT VALID TRIM 1: 16M 2: 24M 3: Reserved" "0: NOT VALID TRIM,1: 16M,2: 24M,3: Reserved" group.long 0x1180++0x3 line.long 0x0 "SYSCTL_SYSTEMCFG,SRAM Write Protect" sif (cpuis("MSPM0L122*")) bitfld.long 0x0 8. "SUPERCAPEN,SUPERCAP specifies whether the battery backup system can be powered by a SUPERCAP" "0: SUPERCAP Function is not enabled,1: SUPERCAP Function is not enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 8. "SUPERCAPEN,SUPERCAP specifies whether the battery backup system can be powered by a SUPERCAP" "0: SUPERCAP Function is not enabled,1: SUPERCAP Function is not enabled" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 2. "FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: Flash ECC DED will trigger a SYSRST,1: Flash ECC DED will trigger a NMI" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 1. "WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: WWDTLP1 Error Event will trigger a SYSRST,1: WWDTLP1 Error Event will trigger an NMI" newline bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 1. "WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: WWDTLP1 Error Event will trigger a SYSRST,1: WWDTLP1 Error Event will trigger an NMI" newline bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 1. "WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: WWDTLP1 Error Event will trigger a SYSRST,1: WWDTLP1 Error Event will trigger an NMI" newline bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 1. "WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: WWDTLP1 Error Event will trigger a SYSRST,1: WWDTLP1 Error Event will trigger an NMI" newline bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 1. "WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: WWDTLP1 Error Event will trigger a SYSRST,1: WWDTLP1 Error Event will trigger an NMI" newline bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 1. "WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: WWDTLP1 Error Event will trigger a SYSRST,1: WWDTLP1 Error Event will trigger an NMI" newline bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0. "FLASHECCRSTDIS,0: Flash ECC Double Error will issue System Reset (default) 1: Reset is disable but sysstatus will be provided" "0: Flash ECC Double Error will issue System Reset,1: Reset is disable but sysstatus will be provided" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 0. "WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: WWDTLP0 Error Event will trigger a BOOTRST,1: WWDTLP0 Error Event will trigger an NMI" endif group.long 0x1200++0x3 line.long 0x0 "SYSCTL_WRITELOCK,SYSOSC Trim Values specified by user" bitfld.long 0x0 0. "ACTIVE,LOCK configuration MMRs from write" "0: Disallow Writes to Lockable MMRs,1: Allow Writes to Lockable MMRs" rgroup.long 0x1204++0x7 line.long 0x0 "SYSCTL_CLKSTATUS,Useful debug status of clock selections" sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline rbitfld.long 0x0 30. "OPAMPCLKERR,OPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected." "0: No OPA clock generation errors detected,1: OPA clock generation error detected" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline rbitfld.long 0x0 30. "OPAMPCLKERR,OPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected." "0: No OPA clock generation errors detected,1: OPA clock generation error detected" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline rbitfld.long 0x0 30. "OPAMPCLKERR,OPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected." "0: No OPA clock generation errors detected,1: OPA clock generation error detected" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline rbitfld.long 0x0 30. "OPAMPCLKERR,OPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected." "0: No OPA clock generation errors detected,1: OPA clock generation error detected" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline rbitfld.long 0x0 30. "OPAMPCLKERR,OPAMPCLKERR is set when the device clock configuration does not support an enabled OPA mode and the OPA may not be functioning as expected." "0: No OPA clock generation errors detected,1: OPA clock generation error detected" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) rbitfld.long 0x0 31. "ACOMPHSCLKERR,Error with Anacomp High Speed CP Clock Generation - SYSOSC must not run at 4MHz" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 31. "ANACLKERR,ANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected." "0: No analog clock errors detected,1: Analog clock error detected" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPS003.*")) rbitfld.long 0x0 30. "OPAMPCLKERR,Error with OPAMP Clock Generation" "0,1" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) rbitfld.long 0x0 29. "SYSPLLBLKUPD,Writes to SYSPLLCFG0-1 SYSPLLPARAM0-1 are blocked" "0,1" newline rbitfld.long 0x0 28. "HFCLKBLKUPD,Writes to HFCLKCLKCFG are blocked" "0,1" newline rbitfld.long 0x0 23. "LFCLKFAIL,Clock Fail for LFXT or EXLF clock source" "0,1" newline rbitfld.long 0x0 21. "HSCLKGOOD,High Speed Clock Good" "0,1" newline rbitfld.long 0x0 20. "HSCLKDEAD,High Speed Clock Stuck Fault" "0,1" newline rbitfld.long 0x0 16. "CURHSCLKSEL,High Speed Clock Source 0: SYSPLL 1:HFCLK" "0: SYSPLL,1: HFCLK" newline rbitfld.long 0x0 14. "SYSPLLOFF,SYSPLL is OFF or DEAD" "0,1" newline rbitfld.long 0x0 13. "HFCLKOFF,HFCLKs is OFF or DEAD" "0,1" newline rbitfld.long 0x0 12. "HSCLKSOFF,All PLLs HFCLKs are OFF or DEAD" "0,1" newline rbitfld.long 0x0 10. "LFXTGOOD,LFXT is Valid" "0,1" newline rbitfld.long 0x0 9. "SYSPLLGOOD,SYSTEM PLL ON" "0,1" newline rbitfld.long 0x0 8. "HFCLKGOOD,High Frequency Clock ON" "0,1" newline rbitfld.long 0x0 4. "HSCLKMUX,High Speed Clock Selected for MCLK (HFCLK PLL ...)" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 28. "HFCLKBLKUPD,HFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked." "0: Writes to HFCLKCLKCFG are allowed,1: Writes to HFCLKCLKCFG are blocked" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 28. "HFCLKBLKUPD,HFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked." "0: Writes to HFCLKCLKCFG are allowed,1: Writes to HFCLKCLKCFG are blocked" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 25. "FCCDONE,FCCDONE indicates when a frequency clock counter capture is complete." "0: FCC capture is not done,1: FCC capture is done" newline endif rbitfld.long 0x0 24. "FCLMODE,SYSOSC FCL MODE ON" "0,1" newline sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 23. "LFCLKFAIL,LFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure." "0: No LFCLK fault detected,1: LFCLK stuck fault detected" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 23. "LFCLKFAIL,LFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure." "0: No LFCLK fault detected,1: LFCLK stuck fault detected" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 23. "LFCLKFAIL,LFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure." "0: No LFCLK fault detected,1: LFCLK stuck fault detected" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 21. "HSCLKGOOD,HSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully." "0: The HSCLK source did not start correctly,1: The HSCLK source started correctly" newline rbitfld.long 0x0 20. "HSCLKDEAD,HSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully." "0: The HSCLK source was not started or started..,1: The HSCLK source did not start correctly" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 21. "HSCLKGOOD,HSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully." "0: The HSCLK source did not start correctly,1: The HSCLK source started correctly" newline rbitfld.long 0x0 20. "HSCLKDEAD,HSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully." "0: The HSCLK source was not started or started..,1: The HSCLK source did not start correctly" newline endif rbitfld.long 0x0 17. "CURMCLKSEL,MCLK Clock Source 0: NOT LFCLK 1:LFCLK" "0: NOT LFCLK,1: LFCLK" newline sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 16. "CURHSCLKSEL,CURHSCLKSEL indicates the current clock source for HSCLK." "0: HSCLK is currently sourced from the SYSPLL,1: HSCLK is currently sourced from the HFCLK" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 16. "CURHSCLKSEL,CURHSCLKSEL indicates the current clock source for HSCLK." "0: HSCLK is currently sourced from the SYSPLL,1: HSCLK is currently sourced from the HFCLK" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 13. "HFCLKOFF,HFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started HFCLKOFF is cleared by hardware. Following startup of the HFCLK if the HFCLK startup monitor determines that the HFCLK was not started correctly .." "0: HFCLK started correctly and is enabled,1: HFCLK is disabled or was dead at startup" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 13. "HFCLKOFF,HFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started HFCLKOFF is cleared by hardware. Following startup of the HFCLK if the HFCLK startup monitor determines that the HFCLK was not started correctly .." "0: HFCLK started correctly and is enabled,1: HFCLK is disabled or was dead at startup" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 12. "HSCLKSOFF,HSCLKSOFF is set when the high speed clock sources (SYSPLL HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF." "0: SYSPLL HFCLK or both were started correctly and..,1: SYSPLL and HFCLK are both either off or dead" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 12. "HSCLKSOFF,HSCLKSOFF is set when the high speed clock sources (SYSPLL HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF." "0: SYSPLL HFCLK or both were started correctly and..,1: SYSPLL and HFCLK are both either off or dead" newline endif rbitfld.long 0x0 11. "LFOSCGOOD,LFOSC is Valid" "0,1" newline sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 10. "LFXTGOOD,LFXTGOOD indicates if the LFXT started correctly. When the LFXT is started LFXTGOOD is cleared by hardware. After the startup settling time has expired the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set .." "0: LFXT did not start correctly,1: LFXT started correctly" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 10. "LFXTGOOD,LFXTGOOD indicates if the LFXT started correctly. When the LFXT is started LFXTGOOD is cleared by hardware. After the startup settling time has expired the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set .." "0: LFXT did not start correctly,1: LFXT started correctly" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 10. "LFXTGOOD,LFXTGOOD indicates if the LFXT started correctly. When the LFXT is started LFXTGOOD is cleared by hardware. After the startup settling time has expired the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set .." "0: LFXT did not start correctly,1: LFXT started correctly" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 8. "HFCLKGOOD,HFCLKGOOD indicates that the HFCLK started correctly. When the HFXT is started or HFCLK_IN is selected as the HFCLK source this bit will be set by hardware if a valid HFCLK is detected and cleared if HFCLK is not operating within the.." "0: HFCLK did not start correctly,1: HFCLK started correctly" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 8. "HFCLKGOOD,HFCLKGOOD indicates that the HFCLK started correctly. When the HFXT is started or HFCLK_IN is selected as the HFCLK source this bit will be set by hardware if a valid HFCLK is detected and cleared if HFCLK is not operating within the.." "0: HFCLK did not start correctly,1: HFCLK started correctly" newline endif rbitfld.long 0x0 6.--7. "LFCLKMUX,Low Frequency Clock Selected" "0: Internal LFOSC,1: LF Crystal,2: External LFCLK IN,?" newline sif (cpuis("MSPM0L111*")) rbitfld.long 0x0 4. "HSCLKMUX,HSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK)." "0: MCLK is not sourced from HSCLK,1: MCLK is sourced from HSCLK" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x0 4. "HSCLKMUX,HSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK)." "0: MCLK is not sourced from HSCLK,1: MCLK is sourced from HSCLK" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x0 4. "HSCLKMUX,HSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK)." "0: MCLK is not sourced from HSCLK,1: MCLK is sourced from HSCLK" newline endif rbitfld.long 0x0 0.--1. "SYSOSCFREQ,Current SYSOSC frequency setting" "0,1,2,3" line.long 0x4 "SYSCTL_SYSSTATUS,Useful System Status Data" sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 30.--31. "REBOOTATTEMPTS,REBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts." "0,1,2,3" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 17. "SRAMBANK1READY,SRAM BANK1 READY STATE" "0: SRAM BANK1 is NOT READY for access,1: SRAM BANK1 is READY for access" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 17. "SRAMBANK1READY,SRAM BANK1 READY STATE" "0: SRAM BANK1 is NOT READY for access,1: SRAM BANK1 is READY for access" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 14. "SHDNIOLOCK,SHDNIOLOCK indicates when IO is locked due to SHUTDOWN" "0: IO IS NOT Locked due to SHUTDOWN,1: IO IS Locked due to SHUTDOWN" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 13. "SWDCFGDIS,SWDCFGDIS indicates when user has disabled the use of SWD Port" "0: SWD Port Enabled,1: SWD Port Disabled" newline rbitfld.long 0x4 12. "EXTRSTPINDIS,EXTRSTPINDIS indicates when user has disabled the use of external reset pin" "0: External Reset Pin Enabled,1: External Reset Pin Disabled" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 9. "MCAN1READY,MCAN1READY indicates when the MCAN1 peripheral is ready." "0: MCAN1 is not ready,1: MCAN1 is ready" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 9. "MCAN1READY,MCAN1READY indicates when the MCAN1 peripheral is ready." "0: MCAN1 is not ready,1: MCAN1 is ready" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPS003.*")) rbitfld.long 0x4 8. "MCAN0READY,MCAN0 Ready" "0,1" newline rbitfld.long 0x4 1. "FLASHSEC,Single Error Correction on Flash" "0,1" newline rbitfld.long 0x4 0. "FLASHDED,Double Error Detect on Flash" "0,1" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 7. "VBATGOOD,VBATGOOD is set by hardware when the VBAT Power Domain is valid." "0: VBAT Power Domain is not valid,1: VBAT Power Domain is valid" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 7. "VBATGOOD,VBATGOOD is set by hardware when the VBAT Power Domain is valid." "0: VBAT Power Domain is not valid,1: VBAT Power Domain is valid" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 6. "PMUIREFGOOD,PMUIREFGOOD is set by hardware when the PMU current reference is ready." "0: IREF is not ready,1: IREF is ready" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 5. "ANACPUMPGOOD,ANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready." "0: VBOOST is not ready,1: VBOOST is ready" newline endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) rbitfld.long 0x4 4. "PMUIREFGOOD,PMU IFREF GOOD" "0,1" newline rbitfld.long 0x4 2. "BORLVL,BOR LEVEL STATUS Indicator" "0,1" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 4. "BORLVL,BORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware." "0: No BOR violation occured,1: A BOR violation occured and the BOR threshold.." newline endif sif (cpuis("MSPM0L111*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline rbitfld.long 0x4 1. "FLASHSEC,FLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC)." "0: No flash ECC single bit error detected,1: Flash ECC single bit error was detected and.." newline rbitfld.long 0x4 0. "FLASHDED,FLASHDED indicates if a flash ECC double bit error was detected (DED)." "0: No flash ECC double bit error detected,1: Flash ECC double bit error detected" newline endif sif (cpuis("MSPM0L122*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline rbitfld.long 0x4 1. "FLASHSEC,FLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC)." "0: No flash ECC single bit error detected,1: Flash ECC single bit error was detected and.." newline rbitfld.long 0x4 0. "FLASHDED,FLASHDED indicates if a flash ECC double bit error was detected (DED)." "0: No flash ECC double bit error detected,1: Flash ECC double bit error detected" newline endif sif (cpuis("MSPM0L222*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline rbitfld.long 0x4 1. "FLASHSEC,FLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC)." "0: No flash ECC single bit error detected,1: Flash ECC single bit error was detected and.." newline rbitfld.long 0x4 0. "FLASHDED,FLASHDED indicates if a flash ECC double bit error was detected (DED)." "0: No flash ECC double bit error detected,1: Flash ECC double bit error detected" newline endif sif (cpuis("MSPM0G110*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0G150*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0G151*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0G310*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0G350*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0G351*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0L110*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0L130*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" newline endif sif (cpuis("MSPM0L134*")) rbitfld.long 0x4 2.--3. "BORCURTHRESHOLD,BORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration." "0: Default minimum threshold; a BOR0- violation..,1: A BOR1- violation generates a BORLVL interrupt,2: A BOR2- violation generates a BORLVL interrupt,3: A BOR3- violation generates a BORLVL interrupt" endif group.long 0x1300++0x3 line.long 0x0 "SYSCTL_RESETLEVEL,Reset Level for Application Reset Command" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "LEVEL,Reset Level 0: CPU plus peripherals 1: BOR level reset to BOOTCODE 2: Do CPU plus Peripheral reset then BOOTLOADER 3: Full Power On Reset -- vcore disabled" "0: CPU plus peripherals,1: BOR level reset to BOOTCODE,2: Do CPU plus Peripheral reset then BOOTLOADER,3: Full Power On Reset -- vcore disabled" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 0.--2. "LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: Issue a SYSRST (CPU plus peripherals only),1: Issue a BOOTRST (CPU peripherals and boot..,2: Issue a SYSRST and enter the boot strap loader..,3: Issue a power-on reset (POR),4: Issue a SYSRST and exit the boot strap loader..,?,?,?" endif wgroup.long 0x1304++0x3 line.long 0x0 "SYSCTL_RESETCMD,Execute Reset Command" bitfld.long 0x0 0. "GO,Execute Reset defined in RESETLEVEL" "?,1: Issue Reset" group.long 0x1308++0x3 line.long 0x0 "SYSCTL_BORTHRESHOLD,BOR Threshold Level" bitfld.long 0x0 0.--1. "LEVEL,BOR Threshold Level 0: Full Re-boot This level is always enforced regardless of MMR seting 1-3: Generates interrupt" "0: Full Re-boot This level is always enforced..,1: BOR Level 1 -- Generates an Interupt,2: BOR Level 2 -- Generates an Interupt,3: BOR Level 3 -- Generates an Interupt" wgroup.long 0x1310++0x3 line.long 0x0 "SYSCTL_SYSOSCFCLCTL,SYSOSC Frequency Control Loop with External Resistor" sif (cpuis("MSPM0G110*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 1. "SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: Enable the SYSOSC external Resistor" newline endif bitfld.long 0x0 0. "SETUSEFCL,Use Freq Control Loop" "?,1: Set FCL Control" wgroup.long 0x131C++0xF line.long 0x0 "SYSCTL_SHDNIOREL,Shutdown IO Release Command" bitfld.long 0x0 0. "RELEASE,Release IO after Shutdown" "?,1: Release IO after SHUTDOWN Exit" line.long 0x4 "SYSCTL_EXRSTPIN,Disable use of external Reset Pin" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 2. "DISABLE,Disable External Reset" "?,1: Disable External Reset" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x4 0. "DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: Reset function of NRST pin is enabled,1: Reset function of NRST pin is disabled" endif line.long 0x8 "SYSCTL_SYSSTATUSCLR,Clear sticky bits of SYSSTATUS" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x8 2. "ALLECC,Clear ALL ECC related SYSSTATUS indicators" "?,1: Clear ECC state" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0x8 0. "ALLECC,Set ALLECC to clear all ECC related SYSSTATUS indicators." "?,1: Clear ECC error state" endif line.long 0xC "SYSCTL_SWDCFG,Disable SWD" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0xC 2. "DISABLE,Disable SWD" "?,1: Disable SWD" newline endif sif (cpuis("MSPM0G150*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0G151*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0G310*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0G350*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0G351*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0L111*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0L122*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0L130*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" newline endif sif (cpuis("MSPM0G110*")) bitfld.long 0xC 0. "DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: Disable SWD function on SWD pins" endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPS003.*")) group.long 0x1380++0x3 line.long 0x0 "SYSCTL_PMUOPAMP,PMU OPAMP Control" bitfld.long 0x0 10.--11. "CHOPCLKMODE,CHOP Clock Mode" "0: Chop Disabled,1: Regular Chop,2: ADC Assisted Chop,?" bitfld.long 0x0 8.--9. "CHOPCLKFREQ,CHOP Clock frequency select" "0,1,2,3" newline bitfld.long 0x0 6. "OUTENABLE,Output To Pad Enable" "0,1" bitfld.long 0x0 4.--5. "RRI,Rail to Rail Input Mode Select" "0: select PMOS input pairs mode,1: select NMOS input pairs mode,2: select rail to rail mode,3: select sample channel 0" newline bitfld.long 0x0 2.--3. "NSEL,Negative Channel Input Select" "0: Select buf output pad as input,1: select unbuf output pad as input,2: select internal buffer output as input,3: no channel selected" bitfld.long 0x0 1. "PCHENABLE,Positive Channel Input Enable" "0,1" newline bitfld.long 0x0 0. "ENABLE,Enable PMU OPAMP" "0,1" endif group.long 0x1400++0xF line.long 0x0 "SYSCTL_SHUTDNSTORE0,Shutdown Storage Byte 0" hexmask.long.byte 0x0 0.--7. 1. "DATA,Shutdown Storage Byte 0" line.long 0x4 "SYSCTL_SHUTDNSTORE1,Shutdown Storage Byte 1" hexmask.long.byte 0x4 0.--7. 1. "DATA,Shutdown Storage Byte 1" line.long 0x8 "SYSCTL_SHUTDNSTORE2,Shutdown Storage Byte 2" hexmask.long.byte 0x8 0.--7. 1. "DATA,Shutdown Storage Byte 2" line.long 0xC "SYSCTL_SHUTDNSTORE3,Shutdown Storage Byte 3" hexmask.long.byte 0xC 0.--7. 1. "DATA,Shutdown Storage Byte 3" sif (cpuis("MSPM0G110*")) group.long 0x2800++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x2804++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x2808++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 5. "CCONSTOP,Conversion Clock is ON during STOP Mode" "0,1" bitfld.long 0x0 4. "CCONRUN,Conversion Clock is ON during RUN Mode" "0,1" newline bitfld.long 0x0 0.--1. "SAMPCLK,Sample Window Clock" "0,1,2,3" rgroup.long 0x2814++0x3 line.long 0x0 "SYSCTL_MGMT_ADC12B4MSPS1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x8800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x8804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x8808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x8814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xA808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xA814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xC800++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xC804++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xC808++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xC814++0x3 line.long 0x0 "SYSCTL_MGMT_ANACOMP2_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x18800++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x18804++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x18814++0x3 line.long 0x0 "SYSCTL_MGMT_DAC12B0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x20800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x20804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x20814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x22800++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x22804++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x22814++0x3 line.long 0x0 "SYSCTL_MGMT_OPAMP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x30800++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x30804++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x30814++0x3 line.long 0x0 "SYSCTL_MGMT_VREF_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x80800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x80804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x80814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x82800++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x82804++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x82814++0x3 line.long 0x0 "SYSCTL_MGMT_WWDTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x84800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x84804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x84814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x90800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x90804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x90814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCQEILP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x94800++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x94804++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x94808++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x94814++0x3 line.long 0x0 "SYSCTL_MGMT_RTC_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA0800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA0804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA0814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xA2800++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xA2804++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0xA2814++0x3 line.long 0x0 "SYSCTL_MGMT_GPIO1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF0800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF0804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF0808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF0814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0xF2800++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0xF2804++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0xF2808++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0xF2814++0x3 line.long 0x0 "SYSCTL_MGMT_I2C1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x100800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x100804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x100808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x100814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x102800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x102804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x102808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x102814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTLP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x108800++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x108804++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x108808++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x108814++0x3 line.long 0x0 "SYSCTL_MGMT_UARTADVLP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x410800++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x410804++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x410814++0x3 line.long 0x0 "SYSCTL_MGMT_MATHACL_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x440800++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x440804++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x440814++0x3 line.long 0x0 "SYSCTL_MGMT_CRC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x442800++0x3 line.long 0x0 "SYSCTL_MGMT_AES_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x442804++0x3 line.long 0x0 "SYSCTL_MGMT_AES_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x442814++0x3 line.long 0x0 "SYSCTL_MGMT_AES_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x444800++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x444804++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x444814++0x3 line.long 0x0 "SYSCTL_MGMT_TRNG_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x468800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x468804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x468808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x468814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x46A800++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x46A804++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x46A808++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x46A814++0x3 line.long 0x0 "SYSCTL_MGMT_SPI1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x500800++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x500804++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" group.long 0x500808++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_CLKCFG,IP Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x500814++0x3 line.long 0x0 "SYSCTL_MGMT_UART0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x50E800++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x50E804++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x50E814++0x3 line.long 0x0 "SYSCTL_MGMT_MCAN0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x860800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x860804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x860814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV4CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x862800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x862804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x862814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16BADV2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x868800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x868804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x868814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x86A800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x86A804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x86A814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER16B2CCSP1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x870800++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x870804++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x870814++0x3 line.long 0x0 "SYSCTL_MGMT_GPTIMER32B2CC0_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" group.long 0x900800++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_PWREN,IP Enable Register" bitfld.long 0x0 0. "ENABLE,IP Enable" "0,1" wgroup.long 0x900804++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_RSTCTL,Power Control Register - Write Only Register. Always Read as 0" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESET STICKY Bit" "0,1" bitfld.long 0x0 0. "RESETASSERT,Assert Reset to IP Domain." "0,1" rgroup.long 0x900814++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0G150*")) rgroup.long 0x900814++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0G310*")) rgroup.long 0x900814++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif sif (cpuis("MSPM0G350*")) rgroup.long 0x900814++0x3 line.long 0x0 "SYSCTL_MGMT_TMALITE1_STAT,IP State Register - Read Only" bitfld.long 0x0 16. "RESETSTKY,IP has been Reset" "0,1" endif tree.end sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")||cpuis("MSPS003.*")) tree "TIMA (Advanced Timer)" base ad:0x0 sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0L111*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "TIMA0_CPU_INT[%s]" base ad:0x40861020 rgroup.long 0x0++0x3 line.long 0x0 "TIMA0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMA0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMA0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMA0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMA0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMA0_GEN_EVENT0[%s]" base ad:0x40861050 rgroup.long 0x0++0x3 line.long 0x0 "TIMA0_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMA0_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMA0_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMA0_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMA0_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMA0_GEN_EVENT1[%s]" base ad:0x40861080 rgroup.long 0x0++0x3 line.long 0x0 "TIMA0_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMA0_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMA0_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMA0_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMA0_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to GEN_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,CCP3 direction" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,CCP2 direction" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,CCP1 direction" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,CCP0 direction" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger." bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault is caused by external fault pin 2." "0: Disable,1: Enable" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault is caused by external fault pin 1." "0: Disable,1: Enable" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault is caused by external fault pin 0." "0: Disable,1: Enable" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault is caused by COMP2 output." "0: Disable,1: Enable" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault is caused by COMP1 output." "0: Disable,1: Enable" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal is caused by COMP0 output." "0: Disable,1: Enable" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault is caused by the system clock fault." "0: Disable,1: Enable" line.long 0x4 "TIMA0_GCTL,Global control register" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0/1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 2/3" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],The CC_45 register are a registers which can be used as compare to the current CTR to create an events CC4U. CC4D. CC5U and CC5D." hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers 0/1" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero event (CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: On a TRIG pulse the value stored in CCACT_xy..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero event(CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse." "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse." "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers 2/3" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=cc_xy) Writes to the..,4: Following a zero event (CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event (CTR=0) with repeat count..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers 4/5" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero event (CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers 0/1" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers 2/3" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers 0/1" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP Complimentary output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP Complimentary output value is set high,2: CCP Complimentary output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers 2/3" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP Complimentary Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP Complimentary output value is set high,2: CCP Complimentary output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register 0/1" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register 2/3" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Phase Load Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select Register" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter Register" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter load Register" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin2 high/low is treated as fault condition." "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 high/low is treated as fault condition." "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 high/low is treated as fault condition." "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the COMP2 output high/low is treated as fault condition." "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the COMP1 output high/low is treated as fault condition." "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the COMP0 output high/low is treated as fault condition." "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0L122*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0L222*")) tree "TIMA0" base ad:0x40860000 group.long 0x400++0x7 line.long 0x0 "TIMA0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA0_GPRCM[%s]" base ad:0x40860800 group.long 0x0++0x3 line.long 0x0 "TIMA0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40860000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40861020 ad:0x4086104C ad:0x40861078) tree "TIMA0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA0_IMASK,Interrupt mask" bitfld.long 0x0 26. "REPC,Repeat Counter Zero Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_RIS,Raw interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_MIS,Masked interrupt status" bitfld.long 0x0 26. "REPC,Repeat Counter Zero" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_ISET,Interrupt set" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA0_ICLR,Interrupt clear" bitfld.long 0x0 26. "REPC,Repeat Counter Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40860000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA0_COMMONREGS[%s]" base ad:0x40861100 group.long 0x0++0xF line.long 0x0 "TIMA0_CCPD,CCP Direction" bitfld.long 0x0 3. "C0CCP3,Counter CCP3" "0: Input,1: Output" bitfld.long 0x0 2. "C0CCP2,Counter CCP2" "0: input,1: Output" newline bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA0_ODIS,Output Disable" bitfld.long 0x4 3. "C0CCP3,Counter CCP3 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[3] is forced low." bitfld.long 0x4 2. "C0CCP2,Counter CCP2 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[2] is forced low." newline bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA0_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA0_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA0_COUNTERREGS[%s]" base ad:0x40861800 group.long 0x0++0xB line.long 0x0 "TIMA0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 23. "SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: Disabled. Z and L events are always generated..,1: Enabled. Z and L events are generated from the.." newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMA0_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA0_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMA0_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA0_CCCTL_45[$1],Capture or Compare Control Registers" bitfld.long 0x0 25. "SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: CCD CCU and RC events are always generated from..,1: CCD CCU and RC events are generated from the.." newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMA0_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMA0_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMA0_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA0_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA0_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xB4++0x3 line.long 0x0 "TIMA0_RC,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RC,Repeat Counter Value" group.long 0xB8++0x3 line.long 0x0 "TIMA0_RCLD,Repeat counter" hexmask.long.byte 0x0 0.--7. 1. "RCLD,Repeat Counter Load Value" group.long 0xD0++0x7 line.long 0x0 "TIMA0_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA0_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G110*")) tree "TIMA1" base ad:0x40862000 group.long 0x400++0x7 line.long 0x0 "TIMA1_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA1_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA1_GPRCM[%s]" base ad:0x40862800 group.long 0x0++0x3 line.long 0x0 "TIMA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40862000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40863020 ad:0x4086304C ad:0x40863078) tree "TIMA1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40862000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA1_COMMONREGS[%s]" base ad:0x40863100 group.long 0x0++0xF line.long 0x0 "TIMA1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA1_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA1_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA1_COUNTERREGS[%s]" base ad:0x40863800 group.long 0x0++0xB line.long 0x0 "TIMA1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA1_CCCTL_45[$1],Capture or Compare Control Registers" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA1_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA1_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." group.long 0xD0++0x7 line.long 0x0 "TIMA1_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA1_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMA1" base ad:0x40862000 group.long 0x400++0x7 line.long 0x0 "TIMA1_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA1_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA1_GPRCM[%s]" base ad:0x40862800 group.long 0x0++0x3 line.long 0x0 "TIMA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40862000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40863020 ad:0x4086304C ad:0x40863078) tree "TIMA1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40862000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA1_COMMONREGS[%s]" base ad:0x40863100 group.long 0x0++0xF line.long 0x0 "TIMA1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA1_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA1_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA1_COUNTERREGS[%s]" base ad:0x40863800 group.long 0x0++0xB line.long 0x0 "TIMA1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA1_CCCTL_45[$1],Capture or Compare Control Registers" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA1_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA1_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." group.long 0xD0++0x7 line.long 0x0 "TIMA1_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA1_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMA1" base ad:0x40862000 group.long 0x400++0x7 line.long 0x0 "TIMA1_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA1_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA1_GPRCM[%s]" base ad:0x40862800 group.long 0x0++0x3 line.long 0x0 "TIMA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40862000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40863020 ad:0x4086304C ad:0x40863078) tree "TIMA1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40862000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA1_COMMONREGS[%s]" base ad:0x40863100 group.long 0x0++0xF line.long 0x0 "TIMA1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA1_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA1_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA1_COUNTERREGS[%s]" base ad:0x40863800 group.long 0x0++0xB line.long 0x0 "TIMA1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA1_CCCTL_45[$1],Capture or Compare Control Registers" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA1_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA1_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." group.long 0xD0++0x7 line.long 0x0 "TIMA1_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA1_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMA1" base ad:0x40862000 group.long 0x400++0x7 line.long 0x0 "TIMA1_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA1_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA1_GPRCM[%s]" base ad:0x40862800 group.long 0x0++0x3 line.long 0x0 "TIMA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40862000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40863020 ad:0x4086304C ad:0x40863078) tree "TIMA1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40862000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA1_COMMONREGS[%s]" base ad:0x40863100 group.long 0x0++0xF line.long 0x0 "TIMA1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA1_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA1_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA1_COUNTERREGS[%s]" base ad:0x40863800 group.long 0x0++0xB line.long 0x0 "TIMA1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA1_CCCTL_45[$1],Capture or Compare Control Registers" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA1_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA1_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." group.long 0xD0++0x7 line.long 0x0 "TIMA1_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA1_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMA1" base ad:0x40862000 group.long 0x400++0x7 line.long 0x0 "TIMA1_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA1_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA1_GPRCM[%s]" base ad:0x40862800 group.long 0x0++0x3 line.long 0x0 "TIMA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40862000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40863020 ad:0x4086304C ad:0x40863078) tree "TIMA1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40862000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA1_COMMONREGS[%s]" base ad:0x40863100 group.long 0x0++0xF line.long 0x0 "TIMA1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA1_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA1_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA1_COUNTERREGS[%s]" base ad:0x40863800 group.long 0x0++0xB line.long 0x0 "TIMA1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA1_CCCTL_45[$1],Capture or Compare Control Registers" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA1_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA1_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." group.long 0xD0++0x7 line.long 0x0 "TIMA1_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA1_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMA1" base ad:0x40862000 group.long 0x400++0x7 line.long 0x0 "TIMA1_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMA1_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMA1_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMA1_GPRCM[%s]" base ad:0x40862800 group.long 0x0++0x3 line.long 0x0 "TIMA1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMA1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMA1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40862000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMA1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMA1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMA1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40863020 ad:0x4086304C ad:0x40863078) tree "TIMA1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMA1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMA1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 24. "F,Fault Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 15. "CCU5,Compare UP event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 14. "CCU4,Compare UP event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "CCD5,Compare DN event mask CCP5" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "CCD4,Compare DN event mask CCP4" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCU4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCD5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCD4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMA1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 24. "F,Fault" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 24. "F,Fault event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event 4 SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 12. "CCD4,Compare down event 4 SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMA1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 24. "F,Fault event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 15. "CCU5,Compare up event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 14. "CCU4,Compare up event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 13. "CCD5,Compare down event 5 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 12. "CCD4,Compare down event 4 CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40862000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMA1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMA1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMA1_COMMONREGS[%s]" base ad:0x40863100 group.long 0x0++0xF line.long 0x0 "TIMA1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMA1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMA1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMA1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMA1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMA1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMA1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x20++0x7 line.long 0x0 "TIMA1_FSCTL,Fault Source Control" bitfld.long 0x0 6. "FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 5. "FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 4. "FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE" bitfld.long 0x0 3. "FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 2. "FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE" bitfld.long 0x0 1. "FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x0 0. "FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE" line.long 0x4 "TIMA1_GCTL,Shadow to active load mask" bitfld.long 0x4 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMA1_COUNTERREGS[%s]" base ad:0x40863800 group.long 0x0++0xB line.long 0x0 "TIMA1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMA1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" newline bitfld.long 0x4 24. "PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: Disabled,1: Enabled" newline bitfld.long 0x4 19. "FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 18. "FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: Continues counting,1: Suspends counting" newline bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" newline bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" newline bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMA1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMA1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "TIMA1_CC_45[$1],Compare Register 4 to Compare Register 5" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMA1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" newline bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" newline bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "TIMA1_CCCTL_45[$1],Capture or Compare Control Registers" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMA1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" newline bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMA1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 30.--31. "SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP_CMPL output value is set high,2: CCP_CMPL output value is set low,?" newline bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" newline bitfld.long 0x0 25.--27. "FEXACT,CCP Output Action on Fault Exit" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 22.--24. "FENACT,CCP Output Action on Fault Entry" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled,4: CCP output value is tristated,?,?,?" newline bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMA1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." newline bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" newline bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xA0++0x7 line.long 0x0 "TIMA1_PL,Counter Register" hexmask.long.word 0x0 0.--15. 1. "PHASE,Phase Load value" line.long 0x4 "TIMA1_DBCTL,Dead Band insertion control register" hexmask.long.word 0x4 16.--27. 1. "FALLDELAY,Fall Delay" newline bitfld.long 0x4 12. "M1_ENABLE,Dead Band Mode 1 Enable." "0: Disabled,1: Enabled" newline hexmask.long.word 0x4 0.--11. 1. "RISEDELAY,Rise Delay" group.long 0xB0++0x3 line.long 0x0 "TIMA1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" newline hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." group.long 0xD0++0x7 line.long 0x0 "TIMA1_FCTL,Fault Control Register" bitfld.long 0x0 13. "FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 12. "FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 11. "FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 10. "FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 9. "FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 8. "FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: Fault Input is active low.,1: Fault Input is active high." newline bitfld.long 0x0 7. "TFIM,Trigger Fault Input Mask" "0: Selected trigger does not participate in fault..,1: Selected trigger participates in fault condition.." newline bitfld.long 0x0 3.--4. "FL,Fault Latch mode" "0: Overall fault condition is not dependent on the..,1: Overall fault condition is dependent on the F..,2: Fault condition is latched. Fault condition is..,3: Fault condition is latched. Fault condition is.." newline bitfld.long 0x0 2. "FI,Fault Input" "0: Overall Fault condition is not dependent on..,1: Overall Fault condition is dependent on sensed.." newline bitfld.long 0x0 0. "FIEN,Fault Input Enable" "0: Fault Input Disabled,1: Fault Input Enabled" line.long 0x4 "TIMA1_FIFCTL,Fault input Filter control register" bitfld.long 0x4 4. "FILTEN,Filter Enable" "0: Bypass,1: Filtered." newline bitfld.long 0x4 3. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods. The input must be at a..,1: Voting. The filter ignores one clock of opposite.." newline bitfld.long 0x4 0.--1. "FP,Filter Period" "0: Filter Period 3,1: Filter Period 5,2: Filter Period 8,?" tree.end tree.end endif tree.end endif tree "TIMG (General Purpose Timer)" base ad:0x0 sif (cpuis("MSPM0G110*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L110*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L111*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "TIMG0_CPU_INT[%s]" base ad:0x40085020 rgroup.long 0x0++0x3 line.long 0x0 "TIMG0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMG0_GEN_EVENT0[%s]" base ad:0x40085050 rgroup.long 0x0++0x3 line.long 0x0 "TIMG0_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG0_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG0_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG0_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG0_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMG0_GEN_EVENT1[%s]" base ad:0x40085080 rgroup.long 0x0++0x3 line.long 0x0 "TIMG0_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG0_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG0_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG0_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG0_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to GEN_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,CCP1 direction" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,CCP0 direction" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger." bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0/1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers 0/1" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero event (CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: On a TRIG pulse the value stored in CCACT_xy..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse." "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse." "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers 0/1" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers 0/1" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register 0/1" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select Register" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L122*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L130*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L134*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L222*")) tree "TIMG0" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG0_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG0_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG0_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG0_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG0_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG0_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG0_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG0_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG0_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG0_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG0_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG0_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG0_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG0_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG0_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG0_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG0_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG0_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG0_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG0_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG0_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG0_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG0_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L110*")) tree "TIMG1" base ad:0x40086000 group.long 0x400++0x7 line.long 0x0 "TIMG1_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG1_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG1_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG1_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG1_GPRCM[%s]" base ad:0x40086800 group.long 0x0++0x3 line.long 0x0 "TIMG1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40086000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40087020 ad:0x4008704C ad:0x40087078) tree "TIMG1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40086000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG1_COMMONREGS[%s]" base ad:0x40087100 group.long 0x0++0xF line.long 0x0 "TIMG1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG1_COUNTERREGS[%s]" base ad:0x40087800 group.long 0x0++0xB line.long 0x0 "TIMG1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L111*")) tree "TIMG1" base ad:0x40086000 group.long 0x400++0x7 line.long 0x0 "TIMG1_FSUB_0,Subsciber Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG1_FSUB_1,Subscriber Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG1_FPUB_0,Publisher Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG1_FPUB_1,Publisher Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." tree "TIMG1_GPRCM[%s]" base ad:0x40086800 group.long 0x0++0x3 line.long 0x0 "TIMG1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40086000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "TIMG1_CPU_INT[%s]" base ad:0x40087020 rgroup.long 0x0++0x3 line.long 0x0 "TIMG1_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMG1_GEN_EVENT0[%s]" base ad:0x40087050 rgroup.long 0x0++0x3 line.long 0x0 "TIMG1_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG1_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG1_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG1_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG1_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMG1_GEN_EVENT1[%s]" base ad:0x40087080 rgroup.long 0x0++0x3 line.long 0x0 "TIMG1_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG1_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG1_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG1_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG1_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end base ad:0x40086000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "TIMG1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to GEN_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG1_COMMONREGS[%s]" base ad:0x40087100 group.long 0x0++0xF line.long 0x0 "TIMG1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,CCP1 direction" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,CCP0 direction" "0: Input,1: Output" line.long 0x4 "TIMG1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger." bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG1_COUNTERREGS[%s]" base ad:0x40087800 group.long 0x0++0xB line.long 0x0 "TIMG1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_CC_01[$1],Capture or Compare Register 0/1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG1_CCCTL_01[$1],Capture or Compare Control Registers 0/1" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero event (CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: On a TRIG pulse the value stored in CCACT_xy..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse." "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse." "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG1_OCTL_01[$1],CCP Output Control Registers 0/1" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG1_CCACT_01[$1],Capture or Compare Action Registers 0/1" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG1_IFCTL_01[$1],Input Filter Control Register 0/1" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG1_TSEL,Trigger Select Register" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L130*")) tree "TIMG1" base ad:0x40086000 group.long 0x400++0x7 line.long 0x0 "TIMG1_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG1_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG1_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG1_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG1_GPRCM[%s]" base ad:0x40086800 group.long 0x0++0x3 line.long 0x0 "TIMG1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40086000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40087020 ad:0x4008704C ad:0x40087078) tree "TIMG1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40086000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG1_COMMONREGS[%s]" base ad:0x40087100 group.long 0x0++0xF line.long 0x0 "TIMG1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG1_COUNTERREGS[%s]" base ad:0x40087800 group.long 0x0++0xB line.long 0x0 "TIMG1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L134*")) tree "TIMG1" base ad:0x40086000 group.long 0x400++0x7 line.long 0x0 "TIMG1_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG1_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG1_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG1_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG1_GPRCM[%s]" base ad:0x40086800 group.long 0x0++0x3 line.long 0x0 "TIMG1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40086000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40087020 ad:0x4008704C ad:0x40087078) tree "TIMG1_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG1_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG1_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG1_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG1_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40086000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG1_COMMONREGS[%s]" base ad:0x40087100 group.long 0x0++0xF line.long 0x0 "TIMG1_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG1_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG1_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG1_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG1_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG1_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG1_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG1_COUNTERREGS[%s]" base ad:0x40087800 group.long 0x0++0xB line.long 0x0 "TIMG1_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG1_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG1_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG1_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG1_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG1_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG1_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG1_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG1_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L110*")) tree "TIMG2" base ad:0x40088000 group.long 0x400++0x7 line.long 0x0 "TIMG2_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG2_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG2_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG2_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG2_GPRCM[%s]" base ad:0x40088800 group.long 0x0++0x3 line.long 0x0 "TIMG2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG2_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40088000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40089020 ad:0x4008904C ad:0x40089078) tree "TIMG2_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG2_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG2_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG2_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG2_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG2_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40088000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG2_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG2_COMMONREGS[%s]" base ad:0x40089100 group.long 0x0++0xF line.long 0x0 "TIMG2_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG2_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG2_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG2_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG2_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG2_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG2_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG2_COUNTERREGS[%s]" base ad:0x40089800 group.long 0x0++0xB line.long 0x0 "TIMG2_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG2_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG2_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG2_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG2_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG2_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG2_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG2_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG2_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L130*")) tree "TIMG2" base ad:0x40088000 group.long 0x400++0x7 line.long 0x0 "TIMG2_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG2_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG2_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG2_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG2_GPRCM[%s]" base ad:0x40088800 group.long 0x0++0x3 line.long 0x0 "TIMG2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG2_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40088000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40089020 ad:0x4008904C ad:0x40089078) tree "TIMG2_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG2_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG2_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG2_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG2_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG2_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40088000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG2_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG2_COMMONREGS[%s]" base ad:0x40089100 group.long 0x0++0xF line.long 0x0 "TIMG2_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG2_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG2_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG2_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG2_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG2_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG2_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG2_COUNTERREGS[%s]" base ad:0x40089800 group.long 0x0++0xB line.long 0x0 "TIMG2_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG2_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG2_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG2_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG2_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG2_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG2_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG2_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG2_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L134*")) tree "TIMG2" base ad:0x40088000 group.long 0x400++0x7 line.long 0x0 "TIMG2_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG2_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG2_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG2_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG2_GPRCM[%s]" base ad:0x40088800 group.long 0x0++0x3 line.long 0x0 "TIMG2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG2_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40088000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40089020 ad:0x4008904C ad:0x40089078) tree "TIMG2_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG2_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG2_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG2_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG2_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG2_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40088000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG2_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG2_COMMONREGS[%s]" base ad:0x40089100 group.long 0x0++0xF line.long 0x0 "TIMG2_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG2_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG2_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG2_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG2_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG2_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG2_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG2_COUNTERREGS[%s]" base ad:0x40089800 group.long 0x0++0xB line.long 0x0 "TIMG2_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG2_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG2_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG2_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG2_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG2_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG2_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG2_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG2_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L110*")) tree "TIMG4" base ad:0x4008C000 group.long 0x400++0x7 line.long 0x0 "TIMG4_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG4_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG4_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG4_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG4_GPRCM[%s]" base ad:0x4008C800 group.long 0x0++0x3 line.long 0x0 "TIMG4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG4_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008C000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008D020 ad:0x4008D04C ad:0x4008D078) tree "TIMG4_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG4_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG4_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG4_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG4_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG4_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008C000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG4_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG4_COMMONREGS[%s]" base ad:0x4008D100 group.long 0x0++0xF line.long 0x0 "TIMG4_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG4_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG4_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG4_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG4_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG4_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG4_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG4_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG4_COUNTERREGS[%s]" base ad:0x4008D800 group.long 0x0++0xB line.long 0x0 "TIMG4_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG4_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG4_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG4_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG4_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG4_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG4_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG4_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L122*")) tree "TIMG4" base ad:0x4008C000 group.long 0x400++0x7 line.long 0x0 "TIMG4_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG4_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG4_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG4_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG4_GPRCM[%s]" base ad:0x4008C800 group.long 0x0++0x3 line.long 0x0 "TIMG4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG4_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008C000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008D020 ad:0x4008D04C ad:0x4008D078) tree "TIMG4_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG4_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG4_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG4_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG4_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG4_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008C000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG4_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG4_COMMONREGS[%s]" base ad:0x4008D100 group.long 0x0++0xF line.long 0x0 "TIMG4_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG4_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG4_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG4_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG4_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG4_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG4_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG4_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG4_COUNTERREGS[%s]" base ad:0x4008D800 group.long 0x0++0xB line.long 0x0 "TIMG4_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG4_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG4_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG4_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG4_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG4_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG4_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG4_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L130*")) tree "TIMG4" base ad:0x4008C000 group.long 0x400++0x7 line.long 0x0 "TIMG4_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG4_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG4_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG4_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG4_GPRCM[%s]" base ad:0x4008C800 group.long 0x0++0x3 line.long 0x0 "TIMG4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG4_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008C000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008D020 ad:0x4008D04C ad:0x4008D078) tree "TIMG4_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG4_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG4_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG4_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG4_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG4_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008C000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG4_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG4_COMMONREGS[%s]" base ad:0x4008D100 group.long 0x0++0xF line.long 0x0 "TIMG4_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG4_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG4_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG4_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG4_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG4_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG4_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG4_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG4_COUNTERREGS[%s]" base ad:0x4008D800 group.long 0x0++0xB line.long 0x0 "TIMG4_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG4_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG4_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG4_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG4_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG4_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG4_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG4_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L134*")) tree "TIMG4" base ad:0x4008C000 group.long 0x400++0x7 line.long 0x0 "TIMG4_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG4_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG4_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG4_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG4_GPRCM[%s]" base ad:0x4008C800 group.long 0x0++0x3 line.long 0x0 "TIMG4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG4_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008C000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008D020 ad:0x4008D04C ad:0x4008D078) tree "TIMG4_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG4_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG4_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG4_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG4_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG4_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008C000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG4_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG4_COMMONREGS[%s]" base ad:0x4008D100 group.long 0x0++0xF line.long 0x0 "TIMG4_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG4_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG4_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG4_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG4_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG4_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG4_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG4_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG4_COUNTERREGS[%s]" base ad:0x4008D800 group.long 0x0++0xB line.long 0x0 "TIMG4_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG4_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG4_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG4_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG4_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG4_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG4_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG4_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L222*")) tree "TIMG4" base ad:0x4008C000 group.long 0x400++0x7 line.long 0x0 "TIMG4_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG4_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG4_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG4_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG4_GPRCM[%s]" base ad:0x4008C800 group.long 0x0++0x3 line.long 0x0 "TIMG4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG4_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008C000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008D020 ad:0x4008D04C ad:0x4008D078) tree "TIMG4_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG4_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG4_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG4_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG4_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG4_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008C000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG4_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG4_COMMONREGS[%s]" base ad:0x4008D100 group.long 0x0++0xF line.long 0x0 "TIMG4_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG4_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG4_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG4_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG4_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG4_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG4_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG4_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG4_COUNTERREGS[%s]" base ad:0x4008D800 group.long 0x0++0xB line.long 0x0 "TIMG4_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG4_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG4_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG4_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG4_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG4_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG4_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG4_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG4_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L122*")) tree "TIMG5" base ad:0x4008E000 group.long 0x400++0x7 line.long 0x0 "TIMG5_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG5_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG5_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG5_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG5_GPRCM[%s]" base ad:0x4008E800 group.long 0x0++0x3 line.long 0x0 "TIMG5_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG5_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG5_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008E000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG5_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG5_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG5_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008F020 ad:0x4008F04C ad:0x4008F078) tree "TIMG5_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG5_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG5_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG5_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG5_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG5_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG5_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008E000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG5_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG5_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG5_COMMONREGS[%s]" base ad:0x4008F100 group.long 0x0++0xF line.long 0x0 "TIMG5_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG5_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG5_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG5_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG5_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG5_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG5_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG5_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG5_COUNTERREGS[%s]" base ad:0x4008F800 group.long 0x0++0xB line.long 0x0 "TIMG5_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG5_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG5_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG5_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG5_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG5_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG5_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG5_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG5_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L222*")) tree "TIMG5" base ad:0x4008E000 group.long 0x400++0x7 line.long 0x0 "TIMG5_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG5_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG5_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG5_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG5_GPRCM[%s]" base ad:0x4008E800 group.long 0x0++0x3 line.long 0x0 "TIMG5_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG5_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG5_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4008E000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG5_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG5_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG5_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4008F020 ad:0x4008F04C ad:0x4008F078) tree "TIMG5_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG5_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG5_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG5_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG5_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG5_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG5_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4008E000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG5_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG5_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG5_COMMONREGS[%s]" base ad:0x4008F100 group.long 0x0++0xF line.long 0x0 "TIMG5_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG5_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG5_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG5_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG5_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG5_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG5_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG5_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG5_COUNTERREGS[%s]" base ad:0x4008F800 group.long 0x0++0xB line.long 0x0 "TIMG5_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG5_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG5_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG5_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG5_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG5_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG5_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG5_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG5_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end endif sif (cpuis("MSPM0G110*")) repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end endif tree.end tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) tree "TIMG14" base ad:0x40084000 group.long 0x400++0x7 line.long 0x0 "TIMG14_FSUB_0,Subsciber Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG14_FSUB_1,Subscriber Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" group.long 0x444++0x7 line.long 0x0 "TIMG14_FPUB_0,Publisher Port 0" bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" line.long 0x4 "TIMG14_FPUB_1,Publisher Port 1" bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" tree "TIMG14_GPRCM[%s]" base ad:0x40084800 group.long 0x0++0x3 line.long 0x0 "TIMG14_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG14_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG14_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40084000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG14_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG14_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG14_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40085020 ad:0x4008504C ad:0x40085078) tree "TIMG14_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG14_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG14_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG14_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG14_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG14_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG14_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40084000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG14_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG14_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG14_COMMONREGS[%s]" base ad:0x40085100 group.long 0x0++0xF line.long 0x0 "TIMG14_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG14_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG14_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG14_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG14_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG14_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG14_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG14_COUNTERREGS[%s]" base ad:0x40085800 group.long 0x0++0xB line.long 0x0 "TIMG14_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG14_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG14_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG14_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMG14_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG14_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMG14_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG14_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMG14_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG14_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMG14_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG14_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMG14_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG14_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0L111*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "TIMG8_CPU_INT[%s]" base ad:0x40091020 rgroup.long 0x0++0x3 line.long 0x0 "TIMG8_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG8_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG8_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG8_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG8_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMG8_GEN_EVENT0[%s]" base ad:0x40091050 rgroup.long 0x0++0x3 line.long 0x0 "TIMG8_GEN_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG8_GEN_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_GEN_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG8_GEN_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG8_GEN_EVENT0_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG8_GEN_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end tree "TIMG8_GEN_EVENT1[%s]" base ad:0x40091080 rgroup.long 0x0++0x3 line.long 0x0 "TIMG8_GEN_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x8++0x3 line.long 0x0 "TIMG8_GEN_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_GEN_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long 0x18++0x3 line.long 0x0 "TIMG8_GEN_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long 0x20++0x3 line.long 0x0 "TIMG8_GEN_EVENT1_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long 0x28++0x3 line.long 0x0 "TIMG8_GEN_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to GEN_EVENT1" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT0" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,CCP1 direction" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,CCP0 direction" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger." bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0/1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers 0/1" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event (CTR=0) Writes to the..,2: Following a CCD event (CTR=CC_xy) Writes to the..,3: Following a CCU event (CTR=CC_xy) Writes to the..,4: Following a zero event (CTR=0) or load event..,5: Following a zero event (CTR=0) with repeat count..,6: On a TRIG pulse the value stored in CCACT_xy..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse." "0: CCP edges have no effect,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse." "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse." "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers 0/1" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers 0/1" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register 0/1" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select Register" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,QEI Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0L122*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0L222*")) tree "TIMG8" base ad:0x40090000 group.long 0x400++0x7 line.long 0x0 "TIMG8_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG8_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG8_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG8_GPRCM[%s]" base ad:0x40090800 group.long 0x0++0x3 line.long 0x0 "TIMG8_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG8_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG8_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40090000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG8_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG8_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG8_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40091020 ad:0x4009104C ad:0x40091078) tree "TIMG8_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG8_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG8_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG8_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG8_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG8_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40090000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG8_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG8_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG8_COMMONREGS[%s]" base ad:0x40091100 group.long 0x0++0xF line.long 0x0 "TIMG8_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG8_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG8_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG8_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG8_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG8_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG8_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG8_COUNTERREGS[%s]" base ad:0x40091800 group.long 0x0++0xB line.long 0x0 "TIMG8_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG8_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG8_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG8_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG8_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG8_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG8_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG8_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG8_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG8_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG9" base ad:0x40092000 group.long 0x400++0x7 line.long 0x0 "TIMG9_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG9_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG9_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG9_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG9_GPRCM[%s]" base ad:0x40092800 group.long 0x0++0x3 line.long 0x0 "TIMG9_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG9_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG9_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40092000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG9_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG9_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG9_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40093020 ad:0x4009304C ad:0x40093078) tree "TIMG9_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG9_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG9_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG9_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG9_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG9_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG9_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40092000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG9_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG9_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG9_COMMONREGS[%s]" base ad:0x40093100 group.long 0x0++0xF line.long 0x0 "TIMG9_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG9_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG9_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG9_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG9_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG9_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG9_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG9_COUNTERREGS[%s]" base ad:0x40093800 group.long 0x0++0xB line.long 0x0 "TIMG9_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG9_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG9_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG9_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG9_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG9_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG9_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG9_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG9_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG9_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG9" base ad:0x40092000 group.long 0x400++0x7 line.long 0x0 "TIMG9_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG9_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG9_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG9_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG9_GPRCM[%s]" base ad:0x40092800 group.long 0x0++0x3 line.long 0x0 "TIMG9_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG9_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG9_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40092000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG9_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG9_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG9_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40093020 ad:0x4009304C ad:0x40093078) tree "TIMG9_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG9_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG9_IMASK,Interrupt mask" bitfld.long 0x0 28. "QEIERR,QEIERR Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 27. "DC,Direction Change Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" newline bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG9_RIS,Raw interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG9_MIS,Masked interrupt status" bitfld.long 0x0 28. "QEIERR,QEIERR" "0: Event Cleared,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change" "0: Event Cleared,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG9_ISET,Interrupt set" bitfld.long 0x0 28. "QEIERR,QEIERR event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 27. "DC,Direction Change event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG9_ICLR,Interrupt clear" bitfld.long 0x0 28. "QEIERR,QEIERR event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 27. "DC,Direction Change event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40092000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG9_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG9_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG9_COMMONREGS[%s]" base ad:0x40093100 group.long 0x0++0xF line.long 0x0 "TIMG9_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG9_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG9_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG9_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG9_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG9_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG9_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG9_COUNTERREGS[%s]" base ad:0x40093800 group.long 0x0++0xB line.long 0x0 "TIMG9_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG9_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG9_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG9_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG9_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG9_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG9_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG9_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG9_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." rgroup.long 0xBC++0x3 line.long 0x0 "TIMG9_QDIR,Count Direction Register" bitfld.long 0x0 0. "DIR,Direction of count" "0: Down (Phase B leads Phase A),1: Up (Phase A leads Phase B)" tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG14" base ad:0x40096000 group.long 0x400++0x7 line.long 0x0 "TIMG14_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG14_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG14_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG14_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG14_GPRCM[%s]" base ad:0x40096800 group.long 0x0++0x3 line.long 0x0 "TIMG14_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG14_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG14_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40096000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG14_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG14_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG14_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097020 ad:0x4009704C ad:0x40097078) tree "TIMG14_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG14_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG14_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG14_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG14_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG14_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG14_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40096000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG14_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG14_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG14_COMMONREGS[%s]" base ad:0x40097100 group.long 0x0++0xF line.long 0x0 "TIMG14_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG14_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG14_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG14_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG14_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG14_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG14_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG14_COUNTERREGS[%s]" base ad:0x40097800 group.long 0x0++0xB line.long 0x0 "TIMG14_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG14_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG14_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG14_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMG14_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG14_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMG14_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG14_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMG14_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG14_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMG14_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG14_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMG14_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG14_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG14" base ad:0x40096000 group.long 0x400++0x7 line.long 0x0 "TIMG14_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG14_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG14_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG14_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG14_GPRCM[%s]" base ad:0x40096800 group.long 0x0++0x3 line.long 0x0 "TIMG14_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG14_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG14_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40096000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG14_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG14_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG14_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40097020 ad:0x4009704C ad:0x40097078) tree "TIMG14_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG14_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG14_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 11. "CCU3,Capture or Compare UP event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "CCU2,Capture or Compare UP event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "CCD3,Capture or Compare DN event mask CCP3" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "CCD2,Capture or Compare DN event mask CCP2" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG14_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG14_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event generated an interrupt CCP3" "0: Event Cleared,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event generated an interrupt CCP2" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG14_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 11. "CCU3,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 10. "CCU2,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 7. "CCD3,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 6. "CCD2,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG14_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 11. "CCU3,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 10. "CCU2,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 7. "CCD3,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 6. "CCD2,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40096000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG14_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG14_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG14_COMMONREGS[%s]" base ad:0x40097100 group.long 0x0++0xF line.long 0x0 "TIMG14_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG14_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG14_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG14_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG14_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG14_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG14_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG14_COUNTERREGS[%s]" base ad:0x40097800 group.long 0x0++0xB line.long 0x0 "TIMG14_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG14_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG14_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG14_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x18)++0x3 line.long 0x0 "TIMG14_CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG14_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x38)++0x3 line.long 0x0 "TIMG14_CCCTL_23[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACTx_y register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" newline bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG14_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x58)++0x3 line.long 0x0 "TIMG14_OCTL_23[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG14_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x78)++0x3 line.long 0x0 "TIMG14_CCACT_23[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG14_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "TIMG14_IFCTL_23[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG14_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G110*")) tree "TIMG6" base ad:0x40868000 group.long 0x400++0x7 line.long 0x0 "TIMG6_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG6_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG6_GPRCM[%s]" base ad:0x40868800 group.long 0x0++0x3 line.long 0x0 "TIMG6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG6_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40868000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40869020 ad:0x4086904C ad:0x40869078) tree "TIMG6_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG6_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG6_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG6_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG6_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG6_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40868000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG6_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG6_COMMONREGS[%s]" base ad:0x40869100 group.long 0x0++0xF line.long 0x0 "TIMG6_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG6_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG6_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG6_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG6_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG6_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG6_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG6_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG6_COUNTERREGS[%s]" base ad:0x40869800 group.long 0x0++0xB line.long 0x0 "TIMG6_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG6_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG6_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG6_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG6_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG6_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG6_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG6_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMG6" base ad:0x40868000 group.long 0x400++0x7 line.long 0x0 "TIMG6_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG6_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG6_GPRCM[%s]" base ad:0x40868800 group.long 0x0++0x3 line.long 0x0 "TIMG6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG6_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40868000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40869020 ad:0x4086904C ad:0x40869078) tree "TIMG6_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG6_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG6_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG6_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG6_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG6_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40868000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG6_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG6_COMMONREGS[%s]" base ad:0x40869100 group.long 0x0++0xF line.long 0x0 "TIMG6_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG6_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG6_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG6_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG6_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG6_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG6_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG6_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG6_COUNTERREGS[%s]" base ad:0x40869800 group.long 0x0++0xB line.long 0x0 "TIMG6_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG6_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG6_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG6_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG6_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG6_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG6_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG6_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG6" base ad:0x40868000 group.long 0x400++0x7 line.long 0x0 "TIMG6_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG6_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG6_GPRCM[%s]" base ad:0x40868800 group.long 0x0++0x3 line.long 0x0 "TIMG6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG6_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40868000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40869020 ad:0x4086904C ad:0x40869078) tree "TIMG6_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG6_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG6_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG6_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG6_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG6_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40868000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG6_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG6_COMMONREGS[%s]" base ad:0x40869100 group.long 0x0++0xF line.long 0x0 "TIMG6_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG6_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG6_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG6_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG6_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG6_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG6_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG6_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG6_COUNTERREGS[%s]" base ad:0x40869800 group.long 0x0++0xB line.long 0x0 "TIMG6_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG6_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG6_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG6_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG6_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG6_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG6_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG6_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMG6" base ad:0x40868000 group.long 0x400++0x7 line.long 0x0 "TIMG6_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG6_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG6_GPRCM[%s]" base ad:0x40868800 group.long 0x0++0x3 line.long 0x0 "TIMG6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG6_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40868000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40869020 ad:0x4086904C ad:0x40869078) tree "TIMG6_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG6_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG6_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG6_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG6_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG6_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40868000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG6_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG6_COMMONREGS[%s]" base ad:0x40869100 group.long 0x0++0xF line.long 0x0 "TIMG6_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG6_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG6_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG6_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG6_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG6_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG6_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG6_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG6_COUNTERREGS[%s]" base ad:0x40869800 group.long 0x0++0xB line.long 0x0 "TIMG6_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG6_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG6_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG6_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG6_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG6_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG6_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG6_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMG6" base ad:0x40868000 group.long 0x400++0x7 line.long 0x0 "TIMG6_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG6_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG6_GPRCM[%s]" base ad:0x40868800 group.long 0x0++0x3 line.long 0x0 "TIMG6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG6_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40868000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40869020 ad:0x4086904C ad:0x40869078) tree "TIMG6_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG6_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG6_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG6_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG6_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG6_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40868000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG6_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG6_COMMONREGS[%s]" base ad:0x40869100 group.long 0x0++0xF line.long 0x0 "TIMG6_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG6_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG6_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG6_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG6_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG6_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG6_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG6_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG6_COUNTERREGS[%s]" base ad:0x40869800 group.long 0x0++0xB line.long 0x0 "TIMG6_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG6_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG6_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG6_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG6_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG6_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG6_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG6_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG6" base ad:0x40868000 group.long 0x400++0x7 line.long 0x0 "TIMG6_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG6_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG6_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG6_GPRCM[%s]" base ad:0x40868800 group.long 0x0++0x3 line.long 0x0 "TIMG6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG6_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40868000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40869020 ad:0x4086904C ad:0x40869078) tree "TIMG6_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG6_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG6_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG6_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG6_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG6_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40868000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG6_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG6_COMMONREGS[%s]" base ad:0x40869100 group.long 0x0++0xF line.long 0x0 "TIMG6_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG6_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG6_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG6_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG6_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG6_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG6_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG6_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG6_COUNTERREGS[%s]" base ad:0x40869800 group.long 0x0++0xB line.long 0x0 "TIMG6_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG6_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG6_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG6_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG6_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG6_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG6_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG6_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG6_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G110*")) tree "TIMG7" base ad:0x4086A000 group.long 0x400++0x7 line.long 0x0 "TIMG7_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG7_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG7_GPRCM[%s]" base ad:0x4086A800 group.long 0x0++0x3 line.long 0x0 "TIMG7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG7_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4086A000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4086B020 ad:0x4086B04C ad:0x4086B078) tree "TIMG7_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG7_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG7_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG7_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG7_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG7_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4086A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG7_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG7_COMMONREGS[%s]" base ad:0x4086B100 group.long 0x0++0xF line.long 0x0 "TIMG7_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG7_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG7_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG7_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG7_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG7_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG7_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG7_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG7_COUNTERREGS[%s]" base ad:0x4086B800 group.long 0x0++0xB line.long 0x0 "TIMG7_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG7_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG7_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG7_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG7_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG7_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG7_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG7_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMG7" base ad:0x4086A000 group.long 0x400++0x7 line.long 0x0 "TIMG7_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG7_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG7_GPRCM[%s]" base ad:0x4086A800 group.long 0x0++0x3 line.long 0x0 "TIMG7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG7_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4086A000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4086B020 ad:0x4086B04C ad:0x4086B078) tree "TIMG7_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG7_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG7_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG7_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG7_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG7_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4086A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG7_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG7_COMMONREGS[%s]" base ad:0x4086B100 group.long 0x0++0xF line.long 0x0 "TIMG7_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG7_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG7_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG7_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG7_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG7_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG7_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG7_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG7_COUNTERREGS[%s]" base ad:0x4086B800 group.long 0x0++0xB line.long 0x0 "TIMG7_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG7_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG7_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG7_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG7_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG7_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG7_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG7_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG7" base ad:0x4086A000 group.long 0x400++0x7 line.long 0x0 "TIMG7_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG7_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG7_GPRCM[%s]" base ad:0x4086A800 group.long 0x0++0x3 line.long 0x0 "TIMG7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG7_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4086A000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4086B020 ad:0x4086B04C ad:0x4086B078) tree "TIMG7_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG7_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG7_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG7_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG7_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG7_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4086A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG7_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG7_COMMONREGS[%s]" base ad:0x4086B100 group.long 0x0++0xF line.long 0x0 "TIMG7_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG7_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG7_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG7_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG7_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG7_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG7_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG7_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG7_COUNTERREGS[%s]" base ad:0x4086B800 group.long 0x0++0xB line.long 0x0 "TIMG7_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG7_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG7_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG7_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG7_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG7_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG7_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG7_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMG7" base ad:0x4086A000 group.long 0x400++0x7 line.long 0x0 "TIMG7_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG7_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG7_GPRCM[%s]" base ad:0x4086A800 group.long 0x0++0x3 line.long 0x0 "TIMG7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG7_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4086A000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4086B020 ad:0x4086B04C ad:0x4086B078) tree "TIMG7_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG7_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG7_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG7_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG7_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG7_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4086A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG7_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG7_COMMONREGS[%s]" base ad:0x4086B100 group.long 0x0++0xF line.long 0x0 "TIMG7_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG7_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG7_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG7_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG7_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG7_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG7_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG7_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG7_COUNTERREGS[%s]" base ad:0x4086B800 group.long 0x0++0xB line.long 0x0 "TIMG7_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG7_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG7_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG7_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG7_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG7_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG7_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG7_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMG7" base ad:0x4086A000 group.long 0x400++0x7 line.long 0x0 "TIMG7_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG7_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG7_GPRCM[%s]" base ad:0x4086A800 group.long 0x0++0x3 line.long 0x0 "TIMG7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG7_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4086A000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4086B020 ad:0x4086B04C ad:0x4086B078) tree "TIMG7_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG7_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG7_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG7_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG7_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG7_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4086A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG7_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG7_COMMONREGS[%s]" base ad:0x4086B100 group.long 0x0++0xF line.long 0x0 "TIMG7_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG7_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG7_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG7_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG7_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG7_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG7_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG7_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG7_COUNTERREGS[%s]" base ad:0x4086B800 group.long 0x0++0xB line.long 0x0 "TIMG7_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG7_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG7_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG7_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG7_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG7_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG7_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG7_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG7" base ad:0x4086A000 group.long 0x400++0x7 line.long 0x0 "TIMG7_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG7_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG7_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG7_GPRCM[%s]" base ad:0x4086A800 group.long 0x0++0x3 line.long 0x0 "TIMG7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG7_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4086A000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x4086B020 ad:0x4086B04C ad:0x4086B078) tree "TIMG7_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG7_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG7_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG7_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG7_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG7_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x4086A000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG7_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG7_COMMONREGS[%s]" base ad:0x4086B100 group.long 0x0++0xF line.long 0x0 "TIMG7_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG7_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG7_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" line.long 0xC "TIMG7_CPS,Clock Prescale Register" hexmask.long.byte 0xC 0.--7. 1. "PCNT,Pre-Scale Count" rgroup.long 0x10++0x3 line.long 0x0 "TIMG7_CPSV,Clock prescale count status register" hexmask.long.byte 0x0 0.--7. 1. "CPSVAL,Current Prescale Count Value" group.long 0x14++0x3 line.long 0x0 "TIMG7_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG7_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" group.long 0x24++0x3 line.long 0x0 "TIMG7_GCTL,Shadow to active load mask" bitfld.long 0x0 0. "SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: Disable,1: Enable" tree.end tree "TIMG7_COUNTERREGS[%s]" base ad:0x4086B800 group.long 0x0++0xB line.long 0x0 "TIMG7_CTR,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG7_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG7_LOAD,Load Register" hexmask.long.word 0x8 0.--15. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG7_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long.word 0x0 0.--15. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG7_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG7_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG7_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG7_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG7_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G110*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G150*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G151*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G310*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G350*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Froce Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0G351*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L122*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif sif (cpuis("MSPM0L222*")) tree "TIMG12" base ad:0x40870000 group.long 0x400++0x7 line.long 0x0 "TIMG12_FSUB_0,Subsciber Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FSUB_1,Subscriber Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." group.long 0x444++0x7 line.long 0x0 "TIMG12_FPUB_0,Publisher Port 0" hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." line.long 0x4 "TIMG12_FPUB_1,Publisher Port 1" hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." tree "TIMG12_GPRCM[%s]" base ad:0x40870800 group.long 0x0++0x3 line.long 0x0 "TIMG12_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TIMG12_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TIMG12_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40870000 newline group.long 0x1000++0x3 newline line.long 0x0 "TIMG12_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "TIMG12_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "TIMG12_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40871020 ad:0x4087104C ad:0x40871078) tree "TIMG12_INT_EVENT[$1]" base $2 rgroup.long ($2)++0x3 line.long 0x0 "TIMG12_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long ($2+0x8)++0x3 line.long 0x0 "TIMG12_IMASK,Interrupt mask" bitfld.long 0x0 25. "TOV,Trigger Overflow Event mask" "0: Disable Event,1: Enable Event" bitfld.long 0x0 9. "CCU1,Capture or Compare UP event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "CCU0,Capture or Compare UP event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 5. "CCD1,Capture or Compare DN event mask CCP1" "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 4. "CCD0,Capture or Compare DN event mask CCP0" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "L,Load Event mask" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "Z,Zero Event mask" "0: Disable Event,1: Enable Event" rgroup.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_RIS,Raw interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" rgroup.long ($2+0x18)++0x3 line.long 0x0 "TIMG12_MIS,Masked interrupt status" bitfld.long 0x0 25. "TOV,Trigger overflow" "0: Event Cleared,1: Event Set" bitfld.long 0x0 15. "CCU5,Compare up event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" bitfld.long 0x0 14. "CCU4,Compare up event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 13. "CCD5,Compare down event generated an interrupt CCP5" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 12. "CCD4,Compare down event generated an interrupt CCP4" "0: Event Cleared,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event generated an interrupt CCP1" "0: Event Cleared,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event generated an interrupt CCP0" "0: Event Cleared,1: Event Set" bitfld.long 0x0 1. "L,Load event generated an interrupt." "0: Event Cleared,1: Event Set" bitfld.long 0x0 0. "Z,Zero event generated an interrupt." "0: Event Cleared,1: Event Set" wgroup.long ($2+0x20)++0x3 line.long 0x0 "TIMG12_ISET,Interrupt set" bitfld.long 0x0 25. "TOV,Trigger Overflow event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 9. "CCU1,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 8. "CCU0,Capture or compare up event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 5. "CCD1,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 1. "L,Load event SET" "0: Writing 0 has no effect.,1: Event Set" bitfld.long 0x0 0. "Z,Zero event SET" "0: Writing 0 has no effect.,1: Event Set" wgroup.long ($2+0x28)++0x3 line.long 0x0 "TIMG12_ICLR,Interrupt clear" bitfld.long 0x0 25. "TOV,Trigger Overflow event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 9. "CCU1,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 8. "CCU0,Capture or compare up event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 5. "CCD1,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" newline bitfld.long 0x0 4. "CCD0,Capture or compare down event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 1. "L,Load event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" bitfld.long 0x0 0. "Z,Zero event CLEAR" "0: Writing 0 has no effect.,1: Event Clear" tree.end repeat.end base ad:0x40870000 newline rgroup.long 0x10E0++0x3 line.long 0x0 "TIMG12_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "TIMG12_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" tree "TIMG12_COMMONREGS[%s]" base ad:0x40871100 group.long 0x0++0xB line.long 0x0 "TIMG12_CCPD,CCP Direction" bitfld.long 0x0 1. "C0CCP1,Counter CCP1" "0: Input,1: Output" bitfld.long 0x0 0. "C0CCP0,Counter CCP0" "0: Input,1: Output" line.long 0x4 "TIMG12_ODIS,Output Disable" bitfld.long 0x4 1. "C0CCP1,Counter CCP1 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[1] is forced low." bitfld.long 0x4 0. "C0CCP0,Counter CCP0 Disable Mask" "0: Output function as selected by the OCTL register..,1: CCP output occpout[0] is forced low." line.long 0x8 "TIMG12_CCLKCTL,Counter Clock Control Register" bitfld.long 0x8 0. "CLKEN,Clock Enable" "0: Clock is disabled.,1: Clock is enabled" group.long 0x14++0x3 line.long 0x0 "TIMG12_CTTRIGCTL,Timer Cross Trigger Control Register" hexmask.long.byte 0x0 16.--19. 1. "EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path" bitfld.long 0x0 1. "EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" newline bitfld.long 0x0 0. "CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: Cross trigger generation disabled.,1: Cross trigger generation enabled" wgroup.long 0x1C++0x3 line.long 0x0 "TIMG12_CTTRIG,Timer Cross Trigger Register" bitfld.long 0x0 0. "TRIG,Generate Cross Trigger" "0: Cross trigger generation disabled,1: Generate Cross trigger pulse" tree.end tree "TIMG12_COUNTERREGS[%s]" base ad:0x40871800 group.long 0x0++0xB line.long 0x0 "TIMG12_CTR,Counter Register" hexmask.long 0x0 0.--31. 1. "CCTR,Current Counter value" line.long 0x4 "TIMG12_CTRCTL,Counter Control Register" bitfld.long 0x4 28.--29. "CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: The counter is set to the LOAD register value,1: The counter value is unchanged from its current..,2: The counter is set to zero,?" bitfld.long 0x4 17. "DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: Resume counting,1: Perform the action as specified by the CVAE field." newline bitfld.long 0x4 13.--15. "CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL_0 ZCOND,1: CCCTL_1 ZCOND,2: CCCTL_2 ZCOND This value exists when there are 4..,3: CCCTL_3 ZCOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" bitfld.long 0x4 10.--12. "CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL_0 ACOND,1: CCCTL_1 ACOND,2: CCCTL_2 ACOND This value exists when there are 4..,3: CCCTL_3 ACOND This value exists when there are 4..,4: Controlled by 2-input QEI mode This value exists..,5: Controlled by 3-input QEI mode This value exists..,?,?" newline bitfld.long 0x4 7.--9. "CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL_0 LCOND,1: CCCTL_1 LCOND,2: CCCTL_2 LCOND This value exists when there are 4..,3: CCCTL_3 LCOND This value exists when there are 4..,4: Controlled by 2 input QEI mode. This value..,5: Controlled by 3 input QEI mode. This value..,?,?" bitfld.long 0x4 4.--5. "CM,Count Mode" "0: Down,1: Up/Down,2: Counter counts up.,?" newline bitfld.long 0x4 1.--3. "REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: Does not automatically advance following a zero..,1: Continues to advance following a zero event.,2: Reserved,3: Continues to advance following a zero event if..,4: Reserved,?,?,?" bitfld.long 0x4 0. "EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set per the.." "0: Disabled,1: Enabled" line.long 0x8 "TIMG12_LOAD,Load Register" hexmask.long 0x8 0.--31. 1. "LD,Load Value" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "TIMG12_CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1" hexmask.long 0x0 0.--31. 1. "CCVAL,Capture or compare value" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "TIMG12_CCCTL_01[$1],Capture or Compare Control Registers" bitfld.long 0x0 29.--31. "CC2SELD,Selects the source second CCD event." "0: Selects CCD from CC0.,1: Selects CCD from CC1.,2: Selects CCD from CC2.,3: Selects CCD from CC3.,4: Selects CCD from CC4.,5: Selects CCD from CC5.,?,?" bitfld.long 0x0 26.--28. "CCACTUPD,CCACT shadow register Update Method" "0: Value written to the CCACT register has..,1: Following a zero event Writes to the CCACTx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: On a TRIG pulse the value stored in CCACTx_y..,?" newline bitfld.long 0x0 22.--24. "CC2SELU,Selects the source second CCU event." "0: Selects CCU from CC0.,1: Selects CCU from CC1.,2: Selects CCU from CC2.,3: Selects CCU from CC3.,4: Selects CCU from CC4.,5: Selects CCU from CC5.,?,?" bitfld.long 0x0 18.--20. "CCUPD,Capture and Compare Update Method" "0: Writes to the CCx_y register is written to the..,1: Following a zero event Writes to the CCx_y..,2: Following a compare (down) event Writes to the..,3: Following a compare (up) event Writes to the..,4: Following a zero or load event Writes to the..,5: Following a zero event with repeat count also..,6: Following a TRIG pulse. Writes to the CCx_y..,?" newline bitfld.long 0x0 17. "COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: Compare,1: Capture" bitfld.long 0x0 12.--14. "ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" newline bitfld.long 0x0 8.--10. "LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" bitfld.long 0x0 4.--6. "ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: Each TIMCLK,1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,5: CCP High or Trigger assertion (level),?,?" newline bitfld.long 0x0 0.--2. "CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: None (never captures),1: Rising edge of CCP or trigger assertion edge,2: Falling edge of CCP or trigger de-assertion edge,3: Either edge of CCP or trigger change..,?,?,?,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "TIMG12_OCTL_01[$1],CCP Output Control Registers" bitfld.long 0x0 5. "CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: Low,1: High" bitfld.long 0x0 4. "CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: No inversion,1: Invert" newline hexmask.long.byte 0x0 0.--3. 1. "CCPO,CCP Output Source" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x70)++0x3 line.long 0x0 "TIMG12_CCACT_01[$1],Capture or Compare Action Registers" bitfld.long 0x0 28.--29. "SWFRCACT,CCP Output Action on Software Force Output" "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,?" bitfld.long 0x0 15.--16. "CC2UACT,CCP Output Action on CC2U event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 12.--13. "CC2DACT,CCP Output Action on CC2D event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 9.--10. "CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 6.--7. "CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" bitfld.long 0x0 3.--4. "LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" newline bitfld.long 0x0 0.--1. "ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: This event is disabled and a lower priority..,1: CCP output value is set high,2: CCP output value is set low,3: CCP output value is toggled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "TIMG12_IFCTL_01[$1],Input Filter Control Register" bitfld.long 0x0 12. "FE,Filter Enable" "0: Bypass.,1: Filtered." bitfld.long 0x0 11. "CPV,Consecutive Period/Voting Select" "0: Consecutive Periods The input must be at a..,1: Voting The filter ignores one clock of opposite.." newline bitfld.long 0x0 8.--9. "FP,Filter Period. This field specifies the sample period for the" "0: The division factor is 3,1: The division factor is 5,2: The division factor is 8,?" bitfld.long 0x0 7. "INV,Input Inversion This bit controls whether the selected input is inverted." "0: Noninverted,1: Inverted" newline hexmask.long.byte 0x0 0.--3. 1. "ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved" repeat.end group.long 0xB0++0x3 line.long 0x0 "TIMG12_TSEL,Trigger Select" bitfld.long 0x0 9. "TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field" hexmask.long.byte 0x0 0.--4. 1. "ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger." tree.end tree.end endif tree.end sif (cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")||cpuis("MSPM0L111*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*")) tree "TRNG (True Random Number Generator)" base ad:0x40444000 tree "TRNG_GPRCM[%s]" base ad:0x40444800 group.long 0x0++0x3 line.long 0x0 "TRNG_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "TRNG_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "TRNG_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40444000 newline rgroup.long 0x1020++0x3 newline line.long 0x0 "TRNG_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,Interrupt index status" group.long 0x1028++0x3 line.long 0x0 "TRNG_IMASK,Interrupt mask" bitfld.long 0x0 3. "IRQ_CAPTURED_RDY,Mask for IRQ_CAPTURED_RDY. Indicates to the CPU that the Captured Word is ready to be read." "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 2. "IRQ_CMD_DONE,Mask for IRQ_CMD_DONE. Indicates that a command has finished" "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 1. "IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." newline bitfld.long 0x0 0. "IRQ_HEALTH_FAIL,Mask for IRQ_HEALTH_FAIL. Indicates that a health test has failed." "0: Interrupt is masked out,1: Interrupt will request an interrupt service.." rgroup.long 0x1030++0x3 line.long 0x0 "TRNG_RIS,Raw interrupt status" bitfld.long 0x0 3. "IRQ_CAPTURED_RDY,Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt." "0: IRQ_CAPTURED_READY did not occur,1: IRQ_CAPTURED_READY occurred" newline bitfld.long 0x0 2. "IRQ_CMD_DONE,Raw interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed." "0: IRQ_CMD_DONE did not occur,1: IRQ_CMD_DONE occurred" newline bitfld.long 0x0 1. "IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: IRQ_CMD_FAIL did not occur,1: IRQ_CMD_FAIL occurred" newline bitfld.long 0x0 0. "IRQ_HEALTH_FAIL,Indicates to the CPU that any of the health tests have failed. Reading the IIDX will clear this interrupt." "0: IRQ_CAPTURED_READY did not occur,1: IRQ_CAPTURED_READY occurred" rgroup.long 0x1038++0x3 line.long 0x0 "TRNG_MIS,Masked interrupt status" bitfld.long 0x0 3. "IRQ_CAPTURED_RDY,Masked interrupt result for CAPTURED_READY. Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt." "0: IRQ_CAPTURED_READY did not request an interrupt..,1: IRQ_CAPTURED_READY requests an interrupt service.." newline bitfld.long 0x0 2. "IRQ_CMD_DONE,Masked interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed." "0: IRQ_CAPTURED_READY did not request an interrupt..,1: IRQ_CMD_DONE requests an interrupt service routine" newline bitfld.long 0x0 1. "IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: IRQ_CMD_FAIL did not request an interrupt..,1: IRQ_CMD_FAIL requests an interrupt service routine" newline bitfld.long 0x0 0. "IRQ_HEALTH_FAIL,Masked interrupt result for HEALTH_FAIL. Indicates to the CPU that any of the health tests have failed for the latest 1024-bit window." "0: IRQ_CAPTURED_READY did not request an interrupt..,1: IRQ_CAPTURED_READY requests an interrupt service.." wgroup.long 0x1040++0x3 line.long 0x0 "TRNG_ISET,Interrupt set" bitfld.long 0x0 3. "IRQ_CAPTURED_RDY,Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: Writing a 0 has no effect,1: RIS bit corresponding to CAPTURED_READY is set" newline bitfld.long 0x0 2. "IRQ_CMD_DONE,Write to turn on CMD_DONE IRQ. Indicates that the last issued TRNG command has finished." "0: Writing a 0 has no effect.,1: RIS bit corresponding to CMD_DONE is set" newline bitfld.long 0x0 1. "IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: Writing a 0 has no effect.,1: RIS bit corresponding to CMD_FAIL is set" newline bitfld.long 0x0 0. "IRQ_HEALTH_FAIL,Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: Writing a 0 has no effect,1: RIS bit corresponding to HEALTH_FAIL is set" wgroup.long 0x1048++0x3 line.long 0x0 "TRNG_ICLR,Interrupt clear" bitfld.long 0x0 3. "IRQ_CAPTURED_RDY,Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: Writing a 0 has no effect,1: RIS bit corresponding to CAPTURED_READY is cleared" newline bitfld.long 0x0 2. "IRQ_CMD_DONE,Write to turn off CMD_DONE IRQ. Indicates that the last issued TRNG command has finished." "0: Writing a 0 has no effect.,1: RIS bit corresponding to CMD_DONE is cleared" newline bitfld.long 0x0 1. "IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: Writing a 0 has no effect.,1: RIS bit corresponding to CMD_FAIL is cleared" newline bitfld.long 0x0 0. "IRQ_HEALTH_FAIL,Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: Writing a 0 has no effect,1: RIS bit corresponding to CAPTURED_READY is cleared" rgroup.long 0x10FC++0x3 line.long 0x0 "TRNG_DESC,Module descriptions" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module Identifier - An internal TI page has been created to request unique module IDs" newline hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x3 line.long 0x0 "TRNG_CTL,Controls the command and decimation rate" bitfld.long 0x0 19.--20. "PWRUP_PSTART_CFG,Configure pusle startup sequence length" "0: Disabled,1: rise at 10us,2: rise at 10us,3: rise at 10us" newline bitfld.long 0x0 17.--18. "PWRUP_PCHRG_CFG,Configure PCHARGE sequence length" "0: Disabled,1: 20 us PCHARGE,2: 30 us PCHARGE,3: 40 us PCHARGE" newline bitfld.long 0x0 16. "PWRUP_CLKDIV,When '1' the powerup sequence will take twice as long (i.e. clock frequency halved)" "0,1" newline bitfld.long 0x0 8.--10. "DECIM_RATE,Set decimation rate. Decimate by n" "0: Decimation by 1,1: Decimation by 2,?,?,?,?,?,7: Decimation by 8" newline bitfld.long 0x0 0.--1. "CMD,Sets the TRNG mode through a command. The mode will not be updated until the previous command is done as indicated by IRQ_CMD_DONE." "0: Turns the power off of the analog source and..,1: Initiates the powerup test sequence for the..,2: Initiates the powerup test sequence for the..,3: Normal operating mode for TRNG. All components.." rgroup.long 0x1104++0xB line.long 0x0 "TRNG_STAT,Status register that informs health test results and last issued command" hexmask.long.byte 0x0 16.--19. 1. "FSM_STATE,Current state of the front end FSM (behind a clock domain crossing)." newline rbitfld.long 0x0 8.--9. "ISSUED_CMD,Indicates the last accepted command that is issued to the TRNG interface." "0,1,2,3" newline rbitfld.long 0x0 1. "REP_FAIL,Indicates that the repetition counter test caused the most recent failure. Thus the health count numbers are most likely not for a complete 1024-bit window." "0,1" newline bitfld.long 0x0 0. "ADAP_FAIL,Indicates that the Adaptive Proportion Test (1 2 3 or 4-bit counters) failed by having too many or too few counted samples in the last 1024 bit window." "0,1" line.long 0x4 "TRNG_DATA_CAPTURE,Captured word buffer of RNG data" line.long 0x8 "TRNG_TEST_RESULTS,Test results from TEST_ANA and TEST_DIG" bitfld.long 0x8 8. "ANA_TEST,Runs through 4096 samples from an enabled entropy source and verifies that none of the health tests failed indicating sufficient entropy was produced by the analog components" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DIG_TEST,Bit 0 indicates if the first decimation rate test and health test(verifies conditioning decimation and captured buffer) fails and Bit 1 indicates if the second decimation test and health test fails" group.long 0x1110++0x3 line.long 0x0 "TRNG_CLKDIVIDE,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,?,3: Divide clock source by 4,?,5: Divide clock source by 6,?,7: Divide clock source by 8" tree.end endif tree "UART (Universal Asynchronouns Receiver Transmitter)" base ad:0x0 sif (cpuis("MSPM0G110*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G150*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G151*")) tree "UART1" base ad:0x40100000 tree "UART1_DMA_TRIG_RX[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_DMA_TRIG_TX[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_CPU_INT[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G310*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G350*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G351*")) tree "UART1" base ad:0x40100000 tree "UART1_DMA_TRIG_RX[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_DMA_TRIG_TX[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_CPU_INT[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L110*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "UART1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: UARTxTXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTXD path is fed through the UARTxRXD.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh." tree.end endif sif (cpuis("MSPM0L111*")) tree "UART1" base ad:0x40100000 tree "UART1_DMA_TRIG_RX[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_DMA_TRIG_TX[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_CPU_INT[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L122*")) tree "UART2" base ad:0x40100000 tree "UART2_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART2_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART2_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART2_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART2_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART2_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART2_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART2_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART2_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART2_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART2_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART2_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART2_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L130*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "UART1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: UARTxTXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTXD path is fed through the UARTxRXD.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh." tree.end endif sif (cpuis("MSPM0L134*")) tree "UART1" base ad:0x40100000 tree "UART1_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "UART1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: UARTxTXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTXD path is fed through the UARTxRXD.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh." tree.end endif sif (cpuis("MSPM0L222*")) tree "UART2" base ad:0x40100000 tree "UART2_GPRCM[%s]" base ad:0x40100800 group.long 0x0++0x3 line.long 0x0 "UART2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40100000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART2_INT_EVENT0[%s]" base ad:0x40101020 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT1[%s]" base ad:0x40101050 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT2[%s]" base ad:0x40101080 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40100000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART2_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART2_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART2_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART2_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART2_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART2_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART2_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART2_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART2_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART2_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART2_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G110*")) tree "UART2" base ad:0x40102000 tree "UART2_GPRCM[%s]" base ad:0x40102800 group.long 0x0++0x3 line.long 0x0 "UART2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40102000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART2_INT_EVENT0[%s]" base ad:0x40103020 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT1[%s]" base ad:0x40103050 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT2[%s]" base ad:0x40103080 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40102000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART2_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART2_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART2_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART2_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART2_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART2_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART2_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART2_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART2_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART2_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART2_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G150*")) tree "UART2" base ad:0x40102000 tree "UART2_GPRCM[%s]" base ad:0x40102800 group.long 0x0++0x3 line.long 0x0 "UART2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40102000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART2_INT_EVENT0[%s]" base ad:0x40103020 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT1[%s]" base ad:0x40103050 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT2[%s]" base ad:0x40103080 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40102000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART2_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART2_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART2_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART2_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART2_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART2_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART2_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART2_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART2_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART2_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART2_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G310*")) tree "UART2" base ad:0x40102000 tree "UART2_GPRCM[%s]" base ad:0x40102800 group.long 0x0++0x3 line.long 0x0 "UART2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40102000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART2_INT_EVENT0[%s]" base ad:0x40103020 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT1[%s]" base ad:0x40103050 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT2[%s]" base ad:0x40103080 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40102000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART2_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART2_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART2_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART2_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART2_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART2_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART2_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART2_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART2_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART2_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART2_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G350*")) tree "UART2" base ad:0x40102000 tree "UART2_GPRCM[%s]" base ad:0x40102800 group.long 0x0++0x3 line.long 0x0 "UART2_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART2_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART2_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40102000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART2_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART2_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART2_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART2_INT_EVENT0[%s]" base ad:0x40103020 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT1[%s]" base ad:0x40103050 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART2_INT_EVENT2[%s]" base ad:0x40103080 rgroup.long 0x0++0x3 line.long 0x0 "UART2_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART2_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART2_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART2_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART2_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART2_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40102000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART2_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART2_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART2_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART2_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART2_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART2_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART2_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART2_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART2_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART2_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART2_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART2_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART2_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L122*")) tree "UART3" base ad:0x40102000 tree "UART3_GPRCM[%s]" base ad:0x40102800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40102000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_INT_EVENT0[%s]" base ad:0x40103020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT1[%s]" base ad:0x40103050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT2[%s]" base ad:0x40103080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40102000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L222*")) tree "UART3" base ad:0x40102000 tree "UART3_GPRCM[%s]" base ad:0x40102800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40102000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_INT_EVENT0[%s]" base ad:0x40103020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT1[%s]" base ad:0x40103050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT2[%s]" base ad:0x40103080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40102000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L122*")) tree "UART4" base ad:0x40104000 tree "UART4_GPRCM[%s]" base ad:0x40104800 group.long 0x0++0x3 line.long 0x0 "UART4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART4_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART4_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40104000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART4_INT_EVENT0[%s]" base ad:0x40105020 rgroup.long 0x0++0x3 line.long 0x0 "UART4_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_INT_EVENT1[%s]" base ad:0x40105050 rgroup.long 0x0++0x3 line.long 0x0 "UART4_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_INT_EVENT2[%s]" base ad:0x40105080 rgroup.long 0x0++0x3 line.long 0x0 "UART4_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40104000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART4_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART4_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART4_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART4_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART4_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART4_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART4_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART4_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART4_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART4_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART4_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART4_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0L222*")) tree "UART4" base ad:0x40104000 tree "UART4_GPRCM[%s]" base ad:0x40104800 group.long 0x0++0x3 line.long 0x0 "UART4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART4_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART4_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40104000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART4_INT_EVENT0[%s]" base ad:0x40105020 rgroup.long 0x0++0x3 line.long 0x0 "UART4_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_INT_EVENT1[%s]" base ad:0x40105050 rgroup.long 0x0++0x3 line.long 0x0 "UART4_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_INT_EVENT2[%s]" base ad:0x40105080 rgroup.long 0x0++0x3 line.long 0x0 "UART4_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40104000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART4_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART4_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART4_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART4_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART4_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART4_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART4_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART4_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" group.long 0x1120++0x3 line.long 0x0 "UART4_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART4_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART4_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART4_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0C110*")||cpuis("MSPM0G110*")||cpuis("MSPS003.*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) rgroup.long 0x0++0x3 line.long 0x0 "UART0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" endif sif (cpuis("MSPM0G110*")) rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" endif tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." endif sif (cpuis("MSPM0G110*")) bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" endif line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" sif (cpuis("MSPM0G110*")) tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end endif tree.end endif sif (cpuis("MSPM0G150*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G151*")) tree "UART0" base ad:0x40108000 tree "UART0_DMA_TRIG_TX[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_CPU_INT[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_DMA_TRIG_RX[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G310*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G350*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G351*")) tree "UART0" base ad:0x40108000 tree "UART0_DMA_TRIG_TX[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_CPU_INT[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_DMA_TRIG_RX[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L110*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "UART0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: UARTxTXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTXD path is fed through the UARTxRXD.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the module clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt." line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture." line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L111*")) tree "UART0" base ad:0x40108000 tree "UART0_DMA_TRIG_TX[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_CPU_INT[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_DMA_TRIG_RX[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L122*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L130*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "UART0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: UARTxTXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTXD path is fed through the UARTxRXD.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the module clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt." line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture." line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L134*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "UART0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: UARTxTXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTXD path is fed through the UARTxRXD.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the module clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt." line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture." line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L222*")) tree "UART0" base ad:0x40108000 tree "UART0_GPRCM[%s]" base ad:0x40108800 group.long 0x0++0x3 line.long 0x0 "UART0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART0_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40108000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART0_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART0_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART0_INT_EVENT0[%s]" base ad:0x40109020 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT1[%s]" base ad:0x40109050 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART0_INT_EVENT2[%s]" base ad:0x40109080 rgroup.long 0x0++0x3 line.long 0x0 "UART0_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART0_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART0_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART0_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART0_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART0_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40108000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART0_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART0_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART0_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART0_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART0_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART0_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART0_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART0_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART0_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART0_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART0_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART0_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART0_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART0_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART0_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART0_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART0_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART0_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART0_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G151*")) tree "UART7" base ad:0x4010A000 tree "UART7_DMA_TRIG_TX[%s]" base ad:0x4010B080 rgroup.long 0x0++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART7_GPRCM[%s]" base ad:0x4010A800 group.long 0x0++0x3 line.long 0x0 "UART7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART7_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART7_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4010A000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART7_CPU_INT[%s]" base ad:0x4010B020 rgroup.long 0x0++0x3 line.long 0x0 "UART7_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART7_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART7_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART7_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART7_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART7_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART7_DMA_TRIG_RX[%s]" base ad:0x4010B050 rgroup.long 0x0++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x4010A000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART7_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART7_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART7_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART7_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART7_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART7_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART7_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART7_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART7_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART7_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART7_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART7_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART7_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART7_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART7_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART7_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART7_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART7_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G351*")) tree "UART7" base ad:0x4010A000 tree "UART7_DMA_TRIG_TX[%s]" base ad:0x4010B080 rgroup.long 0x0++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART7_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART7_GPRCM[%s]" base ad:0x4010A800 group.long 0x0++0x3 line.long 0x0 "UART7_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART7_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART7_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART7_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4010A000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART7_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART7_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART7_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART7_CPU_INT[%s]" base ad:0x4010B020 rgroup.long 0x0++0x3 line.long 0x0 "UART7_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART7_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART7_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART7_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART7_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART7_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART7_DMA_TRIG_RX[%s]" base ad:0x4010B050 rgroup.long 0x0++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART7_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x4010A000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART7_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART7_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART7_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART7_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART7_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART7_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART7_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART7_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART7_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART7_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART7_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART7_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART7_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART7_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART7_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART7_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART7_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART7_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART7_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L122*")) tree "UART1" base ad:0x4010A000 tree "UART1_GPRCM[%s]" base ad:0x4010A800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4010A000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x4010B020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x4010B050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x4010B080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x4010A000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART1_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART1_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART1_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART1_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART1_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART1_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0L222*")) tree "UART1" base ad:0x4010A000 tree "UART1_GPRCM[%s]" base ad:0x4010A800 group.long 0x0++0x3 line.long 0x0 "UART1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART1_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x4010A000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART1_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART1_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART1_INT_EVENT0[%s]" base ad:0x4010B020 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 9. "LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 8. "LINC1,Enable LIN Capture 1 Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 7. "LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 9. "LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 8. "LINC1,Masked LIN Capture 1 Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 7. "LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 9. "LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 8. "LINC1,Set LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 7. "LINC0,Set LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 9. "LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 8. "LINC1,Clear LIN Capture 1 Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 7. "LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT1[%s]" base ad:0x4010B050 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART1_INT_EVENT2[%s]" base ad:0x4010B080 rgroup.long 0x0++0x3 line.long 0x0 "UART1_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART1_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART1_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART1_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART1_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART1_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x4010A000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART1_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART1_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART1_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 7. "MENC,Manchester Encode enable" "0: Disable Manchester Encoding,1: Enable Manchester Encoding" bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" newline bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." newline bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." newline bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART1_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART1_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART1_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART1_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART1_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART1_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." newline bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disable,1: Analog Glitch Filter enable" hexmask.long.byte 0xC 0.--5. 1. "DGFSEL,Glitch Suppression Pulse Width" group.long 0x1120++0x3 line.long 0x0 "UART1_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART1_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1130++0x13 line.long 0x0 "UART1_LINCNT,UART LIN Mode Counter Register" hexmask.long.word 0x0 0.--15. 1. "LINCNT,16 bit up counter clocked by the functional clock of the UART." line.long 0x4 "UART1_LINCTL,UART LIN Mode Control Register" bitfld.long 0x4 6. "LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: Counter compare match mode disabled (capture..,1: Counter compare match enabled (capture mode.." bitfld.long 0x4 5. "LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: Capture counter on positive UARTxRXD edge disabled,1: Capture counter on positive UARTxRXD edge enabled" newline bitfld.long 0x4 4. "LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: Capture counter on negative UARTxRXD edge disabled,1: Capture counter on negative UARTxRXD edge enabled" bitfld.long 0x4 2. "CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: Count while low Signal on UARTxRXD disabled,1: Count while low Signal on UARTxRXD enabled" newline bitfld.long 0x4 1. "ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: Zero on negative edge disabled,1: Zero on negative edge enabled" bitfld.long 0x4 0. "CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: Counter disabled,1: Counter enabled" line.long 0x8 "UART1_LINC0,UART LIN Mode Capture 0 Register" hexmask.long.word 0x8 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0xC "UART1_LINC1,UART LIN Mode Capture 1 Register" hexmask.long.word 0xC 0.--15. 1. "DATA,16 Bit Capture / Compare Register" line.long 0x10 "UART1_IRCTL,eUSCI_Ax IrDA Control Word Register" bitfld.long 0x10 9. "IRRXPL,IrDA receive input UCAxRXD polarity" "0: IrDA transceiver delivers a high pulse when a..,1: IrDA transceiver delivers a low pulse when a.." hexmask.long.byte 0x10 2.--7. 1. "IRTXPL,Transmit pulse length." newline bitfld.long 0x10 1. "IRTXCLK,IrDA transmit pulse clock select" "0: IrDA encode data is based on the functional clock.,1: IrDA encode data is based on the Baud Rate.." bitfld.long 0x10 0. "IREN,IrDA encoder/decoder enable" "0: IrDA encoder/decoder disabled,1: IrDA encoder/decoder enabled" group.long 0x1148++0x7 line.long 0x0 "UART1_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART1_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." group.long 0x1160++0x3 line.long 0x0 "UART1_CLKDIV2,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" tree.end endif sif (cpuis("MSPM0G110*")) tree "UART3" base ad:0x40500000 tree "UART3_GPRCM[%s]" base ad:0x40500800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40500000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_INT_EVENT0[%s]" base ad:0x40501020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT1[%s]" base ad:0x40501050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT2[%s]" base ad:0x40501080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40500000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G150*")) tree "UART3" base ad:0x40500000 tree "UART3_GPRCM[%s]" base ad:0x40500800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40500000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_INT_EVENT0[%s]" base ad:0x40501020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT1[%s]" base ad:0x40501050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT2[%s]" base ad:0x40501080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40500000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G151*")) tree "UART3" base ad:0x40500000 tree "UART3_DMA_TRIG_RX[%s]" base ad:0x40501050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_DMA_TRIG_TX[%s]" base ad:0x40501080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_GPRCM[%s]" base ad:0x40500800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40500000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_CPU_INT[%s]" base ad:0x40501020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40500000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end tree "UART4" base ad:0x40502000 tree "UART4_DMA_TRIG_RX[%s]" base ad:0x40503050 rgroup.long 0x0++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_DMA_TRIG_TX[%s]" base ad:0x40503080 rgroup.long 0x0++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_GPRCM[%s]" base ad:0x40502800 group.long 0x0++0x3 line.long 0x0 "UART4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART4_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART4_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40502000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART4_CPU_INT[%s]" base ad:0x40503020 rgroup.long 0x0++0x3 line.long 0x0 "UART4_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40502000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART4_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART4_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART4_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART4_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART4_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART4_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART4_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART4_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART4_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART4_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART4_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART4_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end tree "UART5" base ad:0x40504000 tree "UART5_DMA_TRIG_RX[%s]" base ad:0x40505050 rgroup.long 0x0++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART5_DMA_TRIG_TX[%s]" base ad:0x40505080 rgroup.long 0x0++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART5_GPRCM[%s]" base ad:0x40504800 group.long 0x0++0x3 line.long 0x0 "UART5_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART5_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART5_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART5_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40504000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART5_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART5_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART5_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART5_CPU_INT[%s]" base ad:0x40505020 rgroup.long 0x0++0x3 line.long 0x0 "UART5_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART5_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART5_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART5_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART5_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART5_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40504000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART5_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART5_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART5_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART5_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART5_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART5_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART5_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART5_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART5_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART5_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART5_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART5_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART5_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end tree "UART6" base ad:0x40506000 tree "UART6_DMA_TRIG_RX[%s]" base ad:0x40507050 rgroup.long 0x0++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART6_DMA_TRIG_TX[%s]" base ad:0x40507080 rgroup.long 0x0++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART6_GPRCM[%s]" base ad:0x40506800 group.long 0x0++0x3 line.long 0x0 "UART6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART6_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART6_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40506000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART6_CPU_INT[%s]" base ad:0x40507020 rgroup.long 0x0++0x3 line.long 0x0 "UART6_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART6_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART6_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART6_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART6_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART6_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40506000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART6_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART6_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART6_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART6_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART6_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART6_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART6_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART6_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART6_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART6_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART6_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART6_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G310*")) tree "UART3" base ad:0x40500000 tree "UART3_GPRCM[%s]" base ad:0x40500800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40500000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_INT_EVENT0[%s]" base ad:0x40501020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT1[%s]" base ad:0x40501050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT2[%s]" base ad:0x40501080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40500000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G350*")) tree "UART3" base ad:0x40500000 tree "UART3_GPRCM[%s]" base ad:0x40500800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40500000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_INT_EVENT0[%s]" base ad:0x40501020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT0_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT0_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT0_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT0_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT0_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT1[%s]" base ad:0x40501050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT1_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT1_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT1_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT1_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT1_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_INT_EVENT2[%s]" base ad:0x40501080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_INT_EVENT2_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_INT_EVENT2_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_INT_EVENT2_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_INT_EVENT2_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_INT_EVENT2_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_INT_EVENT2_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40500000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match .." "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. It is intended to support 9600..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?" newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7" line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 9.--10. "AGFSEL,Analog Glitch Suppression Pulse Width" "0: Pulses shorter then 5ns length are filtered.,1: Pulses shorter then 10ns length are filtered.,2: Pulses shorter then 25ns length are filtered.,3: Pulses shorter then 50ns length are filtered." bitfld.long 0xC 8. "AGFEN,Analog Glitch Suppression Enable" "0: Analog Glitch Filter disalbe,1: Analog Glitch Filter enalbe" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif sif (cpuis("MSPM0G351*")) tree "UART3" base ad:0x40500000 tree "UART3_DMA_TRIG_RX[%s]" base ad:0x40501050 rgroup.long 0x0++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_DMA_TRIG_TX[%s]" base ad:0x40501080 rgroup.long 0x0++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART3_GPRCM[%s]" base ad:0x40500800 group.long 0x0++0x3 line.long 0x0 "UART3_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART3_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART3_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40500000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART3_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART3_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART3_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART3_CPU_INT[%s]" base ad:0x40501020 rgroup.long 0x0++0x3 line.long 0x0 "UART3_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART3_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART3_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART3_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART3_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART3_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40500000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART3_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART3_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART3_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART3_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART3_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART3_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART3_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART3_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART3_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART3_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART3_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART3_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART3_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end tree "UART4" base ad:0x40502000 tree "UART4_DMA_TRIG_RX[%s]" base ad:0x40503050 rgroup.long 0x0++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_DMA_TRIG_TX[%s]" base ad:0x40503080 rgroup.long 0x0++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART4_GPRCM[%s]" base ad:0x40502800 group.long 0x0++0x3 line.long 0x0 "UART4_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART4_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART4_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART4_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40502000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART4_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART4_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART4_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART4_CPU_INT[%s]" base ad:0x40503020 rgroup.long 0x0++0x3 line.long 0x0 "UART4_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART4_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART4_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART4_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART4_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART4_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40502000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART4_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART4_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART4_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART4_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART4_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART4_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART4_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART4_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART4_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART4_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART4_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART4_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART4_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end tree "UART5" base ad:0x40504000 tree "UART5_DMA_TRIG_RX[%s]" base ad:0x40505050 rgroup.long 0x0++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART5_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART5_DMA_TRIG_TX[%s]" base ad:0x40505080 rgroup.long 0x0++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART5_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART5_GPRCM[%s]" base ad:0x40504800 group.long 0x0++0x3 line.long 0x0 "UART5_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART5_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART5_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART5_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40504000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART5_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART5_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART5_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART5_CPU_INT[%s]" base ad:0x40505020 rgroup.long 0x0++0x3 line.long 0x0 "UART5_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART5_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART5_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART5_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART5_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART5_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40504000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART5_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART5_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART5_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART5_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART5_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART5_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART5_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART5_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART5_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART5_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART5_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART5_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART5_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end tree "UART6" base ad:0x40506000 tree "UART6_DMA_TRIG_RX[%s]" base ad:0x40507050 rgroup.long 0x0++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_IMASK,Interrupt mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_RIS,Raw interrupt status" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_MIS,Masked interrupt status" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_ISET,Interrupt set" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART6_DMA_TRIG_RX_ICLR,Interrupt clear" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART6_DMA_TRIG_TX[%s]" base ad:0x40507080 rgroup.long 0x0++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_IMASK,Interrupt mask" bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_RIS,Raw interrupt status" bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_MIS,Masked interrupt status" bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_ISET,Interrupt set" bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART6_DMA_TRIG_TX_ICLR,Interrupt clear" bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end tree "UART6_GPRCM[%s]" base ad:0x40506800 group.long 0x0++0x3 line.long 0x0 "UART6_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "UART6_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" group.long 0x8++0x3 line.long 0x0 "UART6_CLKCFG,Peripheral Clock Configuration Register" bitfld.long 0x0 8. "BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART6_GPRCM_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40506000 newline group.long 0x1000++0x3 newline line.long 0x0 "UART6_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock" "0: Do not divide clock source,1: Divide clock source by 2,2: Divide clock source by 3,3: Divide clock source by 4,4: Divide clock source by 5,5: Divide clock source by 6,6: Divide clock source by 7,7: Divide clock source by 8" group.long 0x1008++0x3 line.long 0x0 "UART6_CLKSEL,Clock Select for Ultra Low Power peripherals" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: Does not select this clock as a source,1: Select this clock as a source" group.long 0x1018++0x3 line.long 0x0 "UART6_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 1. "SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: The peripheral will halt immediately even if the..,1: The peripheral blocks the debug freeze until it.." bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "UART6_CPU_INT[%s]" base ad:0x40507020 rgroup.long 0x0++0x3 line.long 0x0 "UART6_CPU_INT_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--7. 1. "STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved" group.long 0x8++0x3 line.long 0x0 "UART6_CPU_INT_IMASK,Interrupt mask" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 16. "DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 15. "DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt Mask" newline bitfld.long 0x0 14. "CTS,Enable UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Set Interrupt Mask" bitfld.long 0x0 13. "ADDR_MATCH,Enable Address Match Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 12. "EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 11. "TXINT,Enable UART Transmit Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 10. "RXINT,Enable UART Receive Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 6. "RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 5. "RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 4. "OVRERR,Enable UART Receive Overrun Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 3. "BRKERR,Enable UART Break Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" newline bitfld.long 0x0 2. "PARERR,Enable UART Parity Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 1. "FRMERR,Enable UART Framing Error Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" bitfld.long 0x0 0. "RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "UART6_CPU_INT_RIS,Raw interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,UART Clear to Send Modem Interrupt." "0: Interrupt disabled,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" rgroup.long 0x18++0x3 line.long 0x0 "UART6_CPU_INT_MIS,Masked interrupt status" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 16. "DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 15. "DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 14. "CTS,Masked UART Clear to Send Modem Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 13. "ADDR_MATCH,Masked Address Match Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 12. "EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 11. "TXINT,Masked UART Transmit Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 10. "RXINT,Masked UART Receive Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 6. "RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 5. "RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 4. "OVRERR,Masked UART Receive Overrun Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 3. "BRKERR,Masked UART Break Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" newline bitfld.long 0x0 2. "PARERR,Masked UART Parity Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 1. "FRMERR,Masked UART Framing Error Interrupt." "0: Interrupt did not occur,1: Interrupt occured" bitfld.long 0x0 0. "RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: Interrupt did not occur,1: Interrupt occured" wgroup.long 0x20++0x3 line.long 0x0 "UART6_CPU_INT_ISET,Interrupt set" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing this has no effect,1: Set the interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Set Interrupt" newline bitfld.long 0x0 14. "CTS,Set UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Set Address Match Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 12. "EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 11. "TXINT,Set UART Transmit Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 10. "RXINT,Set UART Receive Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 6. "RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 5. "RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 4. "OVRERR,Set UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 3. "BRKERR,Set UART Break Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" newline bitfld.long 0x0 2. "PARERR,Set UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 1. "FRMERR,Set UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" bitfld.long 0x0 0. "RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "UART6_CPU_INT_ICLR,Interrupt clear" bitfld.long 0x0 17. "NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 16. "DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" bitfld.long 0x0 15. "DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: Interrupt disabled,1: Clear Interrupt" newline bitfld.long 0x0 14. "CTS,Clear UART Clear to Send Modem Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 13. "ADDR_MATCH,Clear Address Match Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 12. "EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 11. "TXINT,Clear UART Transmit Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 10. "RXINT,Clear UART Receive Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 6. "RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 5. "RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 4. "OVRERR,Clear UART Receive Overrun Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 3. "BRKERR,Clear UART Break Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" newline bitfld.long 0x0 2. "PARERR,Clear UART Parity Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 1. "FRMERR,Clear UART Framing Error Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" bitfld.long 0x0 0. "RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40506000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "UART6_EVT_MODE,Event Mode" bitfld.long 0x0 4.--5. "INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_TX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" bitfld.long 0x0 2.--3. "INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.DMA_TRIG_RX]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" newline bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" wgroup.long 0x10E4++0x3 line.long 0x0 "UART6_INTCTL,Interrupt control register" bitfld.long 0x0 0. "INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode." group.long 0x1100++0x7 line.long 0x0 "UART6_CTL0,UART Control Register 0" bitfld.long 0x0 19. "MSBFIRST,Most Significant Bit First" "0: Least significant bit is sent first in the..,1: Most significant bit is sent first in the.." bitfld.long 0x0 18. "MAJVOTE,Majority Vote Enable" "0: Majority voting is disabled,1: Majority voting is enabled" newline bitfld.long 0x0 17. "FEN,UART Enable FIFOs" "0: The FIFOs are disabled (Character mode). The..,1: The transmit and receive FIFO buffers are.." bitfld.long 0x0 15.--16. "HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: 16x oversampling.,1: 8x oversampling.,2: 3x oversampling. IrDA Manchester and DALI not..,?" newline bitfld.long 0x0 14. "CTSEN,Enable Clear To Send" "0: CTS hardware flow control is disabled.,1: CTS hardware flow control is enabled. Data is.." bitfld.long 0x0 13. "RTSEN,Enable hardware controlled Request to Send" "0: RTS hardware flow control is disabled.,1: RTS hardware flow control is enabled. Data is.." newline bitfld.long 0x0 12. "RTS,Request to Send" "0: Signal not RTS,1: Signal RTS" bitfld.long 0x0 8.--10. "MODE,Set the communication mode and protocol used." "0: Normal operation,1: RS485 mode: UART needs to be IDLE with receiving..,2: The UART operates in IDLE Line Mode,3: The UART operates in 9 Bit Address mode,4: ISO7816 Smart Card Support The application must..,5: DALI Mode:,?,?" newline bitfld.long 0x0 6. "TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: TXD pin is low,1: TXD pin is high" bitfld.long 0x0 5. "TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: TXD pin can not be controlled by TXD_OUT,1: TXD pin can be controlled by TXD_OUT" newline bitfld.long 0x0 4. "TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: The transmit section of the UART is disabled.,1: The transmit section of the UART is enabled." bitfld.long 0x0 3. "RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: The receive section of the UART is disabled.,1: The receive section of the UART is enabled." newline bitfld.long 0x0 2. "LBE,UART Loop Back Enable" "0: Normal operation.,1: The UARTxTX path is fed through the UARTxRX path.." bitfld.long 0x0 0. "ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: Disable Module,1: Enable module" line.long 0x4 "UART6_LCRH,UART Line Control Register" hexmask.long.byte 0x4 21.--25. 1. "EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)" hexmask.long.byte 0x4 16.--20. 1. "EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send" newline bitfld.long 0x4 7. "SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: Disable Send Idle Pattern,1: Enable Send Idle Pattern" bitfld.long 0x4 6. "SPS,UART Stick Parity Select" "0: Disable Stick Parity,1: Enable Stick Parity" newline bitfld.long 0x4 4.--5. "WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: 5 bits (default),1: 6 bits,2: 7 bits,3: 8 bits" bitfld.long 0x4 3. "STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: One stop bit is transmitted at the end of a frame.,1: Two stop bits are transmitted at the end of a.." newline bitfld.long 0x4 2. "EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte" bitfld.long 0x4 1. "PEN,UART Parity Enable" "0: Parity is disabled and no parity bit is added to..,1: Parity checking and generation is enabled." newline bitfld.long 0x4 0. "BRK,UART Send Break (for LIN Protocol)" "0: Normal use.,1: A low level is continually output on the.." rgroup.long 0x1108++0x3 line.long 0x0 "UART6_STAT,UART Status Register" bitfld.long 0x0 9. "IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: IDLE has not been detected before last received..,1: IDLE has been detected before last received.." bitfld.long 0x0 8. "CTS,Clear To Send" "0: The CTS signal is not asserted (high).,1: The CTS signal is asserted (low)." newline bitfld.long 0x0 7. "TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter is not full.,1: If the FIFO is disabled (FEN is 0) the transmit.." bitfld.long 0x0 6. "TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The transmitter has data to transmit.,1: If the FIFO is disabled (FEN is 0) the transmit.." newline bitfld.long 0x0 3. "RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver can receive data.,1: If the FIFO is disabled (FEN is 0) the receive.." bitfld.long 0x0 2. "RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: The receiver is not empty.,1: If the FIFO is disabled (FEN is 0) the receive.." newline bitfld.long 0x0 0. "BUSY,UART Busy" "0: The UART is not busy.,1: The UART is busy transmitting data. This bit.." group.long 0x110C++0xF line.long 0x0 "UART6_IFLS,UART Interrupt FIFO Level Select Register" hexmask.long.byte 0x0 8.--11. 1. "RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function." bitfld.long 0x0 4.--6. "RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: RX FIFO >= 1/4 full,2: RX FIFO >= 1/2 full (default),3: RX FIFO >= 3/4 full,4: LVL_FULL,5: RX FIFO is full,?,7: RX FIFO >= 1 entry available Note: esp. required.." newline bitfld.long 0x0 0.--2. "TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: TX FIFO <= 3/4 empty,2: TX FIFO <= 1/2 empty (default),3: TX FIFO <= 1/4 empty,?,5: TX FIFO is empty,?,7: TX FIFO >= 1 entry free Note: esp. required for.." line.long 0x4 "UART6_IBRD,UART Integer Baud-Rate Divisor Register" hexmask.long.word 0x4 0.--15. 1. "DIVINT,Integer Baud-Rate Divisor" line.long 0x8 "UART6_FBRD,UART Fractional Baud-Rate Divisor Register" hexmask.long.byte 0x8 0.--5. 1. "DIVFRAC,Fractional Baud-Rate Divisor" line.long 0xC "UART6_GFCTL,Glitch Filter Control" bitfld.long 0xC 11. "CHAIN,Analog and digital noise filters chaining enable." "0: Disabled,1: Enabled" group.long 0x1120++0x3 line.long 0x0 "UART6_TXDATA,UART Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART." rgroup.long 0x1124++0x3 line.long 0x0 "UART6_RXDATA,UART Receive Data Register" bitfld.long 0x0 12. "NERR,Noise Error." "0: No noise error occured,1: Noise error occured during majority voting" bitfld.long 0x0 11. "OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data is.." "0: No data has been lost due to a receive overrun.,1: New data was received but could not be stored.." newline bitfld.long 0x0 10. "BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0 character.." "0: No break condition has occurred,1: A break condition has been detected indicating.." bitfld.long 0x0 9. "PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: No parity error has occurred,1: The parity of the received data character does.." newline bitfld.long 0x0 8. "FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: No framing error has occurred,1: The received character does not have a valid.." hexmask.long.byte 0x0 0.--7. 1. "DATA,Received Data. When read this field contains the data that was received by the UART." group.long 0x1148++0x7 line.long 0x0 "UART6_AMASK,Self Address Mask Register" hexmask.long.byte 0x0 0.--7. 1. "MSK,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register is don't.." line.long 0x4 "UART6_ADDR,Self Address Register" hexmask.long.byte 0x4 0.--7. 1. "ADDR,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh." tree.end endif tree.end tree "VREF (Voltage Reference)" base ad:0x40030000 tree "VREF_GPRCM[%s]" base ad:0x40030800 group.long 0x0++0x3 line.long 0x0 "VREF_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "VREF_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "VREF_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40030000 newline group.long 0x1000++0x3 newline line.long 0x0 "VREF_CLKDIV,Clock Divider" bitfld.long 0x0 0.--2. "RATIO,Selects divide ratio of module clock to be used in sample and hold logic" "0,1,2,3,4,5,6,7" group.long 0x1008++0x3 line.long 0x0 "VREF_CLKSEL,Clock Selection" bitfld.long 0x0 3. "BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0,1" bitfld.long 0x0 2. "MFCLK_SEL,Selects MFCLK as clock source if enabled" "0,1" newline bitfld.long 0x0 1. "LFCLK_SEL,Selects LFCLK as clock source if enabled" "0,1" sif (cpuis("MSPM0L110*")) rgroup.long 0x10FC++0x3 line.long 0x0 "VREF_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" endif sif (cpuis("MSPM0L130*")) rgroup.long 0x10FC++0x3 line.long 0x0 "VREF_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" endif sif (cpuis("MSPM0L134*")) rgroup.long 0x10FC++0x3 line.long 0x0 "VREF_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" endif group.long 0x1100++0xB line.long 0x0 "VREF_CTL0,Control 0" sif (cpuis("MSPM0L110*")) hexmask.long.byte 0x0 9.--12. 1. "SPARE,These bits are reserved" endif sif (cpuis("MSPM0L130*")) hexmask.long.byte 0x0 9.--12. 1. "SPARE,These bits are reserved" newline endif sif (cpuis("MSPM0L134*")) hexmask.long.byte 0x0 9.--12. 1. "SPARE,These bits are reserved" endif bitfld.long 0x0 8. "SHMODE,This bit enable sample and hold mode" "0: Sample and hold mode is disable,1: Sample and hold mode is enable" newline bitfld.long 0x0 7. "BUFCONFIG,These bits configure output buffer." "0: Configure Output Buffer to 2.5v,1: Configure Output Buffer to 1.4v" sif (cpuis("MSPM0L110*")) bitfld.long 0x0 2.--3. "IBPROG,There bits configure current bias." "0: Nominal Ibias setting.,1: Ibias Program Option b01: TheFlash: Increase..,2: Ibias Program Option b10: TheFlash: Reduce Ibias..,3: Ibias Program Option b11: TheFlash: Nominal.." newline bitfld.long 0x0 1. "ENABLEBIAS,This bit enables the VREF Bias." "0: IBIAS is disable,1: IBIAS is enable" endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 2.--3. "IBPROG,There bits configure current bias." "0: Nominal Ibias setting.,1: Ibias Program Option b01: TheFlash: Increase..,2: Ibias Program Option b10: TheFlash: Reduce Ibias..,3: Ibias Program Option b11: TheFlash: Nominal.." newline bitfld.long 0x0 1. "ENABLEBIAS,This bit enables the VREF Bias." "0: IBIAS is disable,1: IBIAS is enable" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 2.--3. "IBPROG,There bits configure current bias." "0: Nominal Ibias setting.,1: Ibias Program Option b01: TheFlash: Increase..,2: Ibias Program Option b10: TheFlash: Reduce Ibias..,3: Ibias Program Option b11: TheFlash: Nominal.." newline bitfld.long 0x0 1. "ENABLEBIAS,This bit enables the VREF Bias." "0: IBIAS is disable,1: IBIAS is enable" endif sif (cpuis("MSPM0L122*")) bitfld.long 0x0 1. "COMP_VREF_ENABLE,Comparator Vref Enable" "0: COMP VREF is disabled,1: COMP VREF is enabled" newline endif sif (cpuis("MSPM0L222*")) bitfld.long 0x0 1. "COMP_VREF_ENABLE,Comparator Vref Enable" "0: COMP VREF is disabled,1: COMP VREF is enabled" endif sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 1. "COMP_VREF_ENABLE,Comparator Vref Enable" "0: COMP VREF is disabled,1: COMP VREF is enabled" newline endif bitfld.long 0x0 0. "ENABLE,This bit enables the VREF module." "0: VREF is disabled,1: VREF is enabled" line.long 0x4 "VREF_CTL1,Control 1" sif (cpuis("MSPM0L110*")) bitfld.long 0x4 1. "VREFLOSEL,This bit select VREFLO pin" "0,1" endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 1. "VREFLOSEL,This bit select VREFLO pin" "0,1" newline endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 1. "VREFLOSEL,This bit select VREFLO pin" "0,1" endif rbitfld.long 0x4 0. "READY,These bits defines status of VREF" "0: VREF output is not ready,1: VREF output is ready" line.long 0x8 "VREF_CTL2,Control 2" hexmask.long.word 0x8 16.--31. 1. "HCYCLE,Hold cycle count" hexmask.long.word 0x8 0.--15. 1. "SHCYCLE,Sample and Hold cycle count" tree.end tree "WUC (Wake Up Controller)" base ad:0x40424000 group.long 0x400++0x7 line.long 0x0 "WUC_FSUB_0,Subscriber Port 0" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x0 0.--8. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L130*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x0 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x0 0.--3. 1. "CHANID,0 = disconnected." endif line.long 0x4 "WUC_FSUB_1,Subscriber Port 1" sif (cpuis("MSPM0C110*")||cpuis("MSPS003.*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0G110*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G150*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G151*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G310*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G350*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0G351*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." newline endif sif (cpuis("MSPM0L110*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L111*")) hexmask.long.word 0x4 0.--8. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L122*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif sif (cpuis("MSPM0L130*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L134*")) bitfld.long 0x4 0.--1. "CHANID,0 = disconnected." "0: disconnected,?,?,?" endif sif (cpuis("MSPM0L222*")) hexmask.long.byte 0x4 0.--3. 1. "CHANID,0 = disconnected." endif tree.end tree "WWDT (Window Watchdog Timer)" base ad:0x0 tree "WWDT0" base ad:0x40080000 tree "WWDT0_GPRCM[%s]" base ad:0x40080800 group.long 0x0++0x3 line.long 0x0 "WWDT0_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "WWDT0_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear [GPRCM.STAT.RESETSTKY]" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "WWDT0_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40080000 newline group.long 0x1018++0x3 newline line.long 0x0 "WWDT0_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "WWDT0_INT_EVENT[%s]" base ad:0x40081020 rgroup.long 0x0++0x3 line.long 0x0 "WWDT0_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--4. 1. "STAT,Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC." group.long 0x8++0x3 line.long 0x0 "WWDT0_IMASK,Interrupt mask" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "WWDT0_RIS,Raw interrupt status" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "WWDT0_MIS,Masked interrupt status" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "WWDT0_ISET,Interrupt set" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "WWDT0_ICLR,Interrupt clear" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40080000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "WWDT0_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "WWDT0_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "WWDT0_WWDTCTL0,Window Watchdog Timer Control Register 0" bitfld.long 0x0 17. "STISM,Stop In Sleep Mode." "0: The WWDT continues to function in Sleep mode.,1: The WWDT stops in Sleep mode and resumes where.." bitfld.long 0x0 16. "MODE,Window Watchdog Timer Mode" "0: Window Watchdog Timer Mode. The WWDT will..,1: Interval Timer Mode. The WWDT acts as an.." newline bitfld.long 0x0 12.--14. "WINDOW1,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: 0% (No closed Window),1: 12.50% of the total timer period is closed window,2: 18.75% of the total timer period is closed window,3: 25% of the total timer period is closed window,4: 50% of the total timer period is closed window,5: 75% of the total timer period is closed window,6: 81.25% of the total timer period is closed window,7: 87.50% of the total timer period is closed window" bitfld.long 0x0 8.--10. "WINDOW0,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: 0% (No closed Window),1: 12.50% of the total timer period is closed window,2: 18.75% of the total timer period is closed window,3: 25% of the total timer period is closed window,4: 50% of the total timer period is closed window,5: 75% of the total timer period is closed window,6: 81.25% of the total timer period is closed window,7: 87.50% of the total timer period is closed window" newline bitfld.long 0x0 4.--6. "PER,Timer Period of the WWDT. These bits select the total watchdog timer count." "0: Total timer count is 2^25,1: Total timer count is 2^21,2: Total timer count is 2^18,3: Total timer count is 2^15,4: Total timer count is 2^12 (default),5: Total timer count is 2^10,6: Total timer count is 2^8,7: Total timer count is 2^6" bitfld.long 0x0 0.--2. "CLKDIV,Module Clock Divider Divide the clock source by CLKDIV+1." "0,1,2,3,4,5,6,7" line.long 0x4 "WWDT0_WWDTCTL1,Window Watchdog Timer Control Register 0" bitfld.long 0x4 0. "WINSEL,Close Window Select" "0: In window mode field WINDOW0 of WDDTCTL0 defines..,1: In window mode field WINDOW1 of WDDTCTL0 defines.." line.long 0x8 "WWDT0_WWDTCNTRST,Window Watchdog Timer Counter Reset Register" hexmask.long 0x8 0.--31. 1. "RESTART,Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter." rgroup.long 0x110C++0x3 line.long 0x0 "WWDT0_WWDTSTAT,Window Watchdog Timer Status Register" bitfld.long 0x0 0. "RUN,Watchdog running status flag." "0: Watchdog counter stopped.,1: Watchdog running." tree.end sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G151*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0G351*")) tree "WWDT1" base ad:0x40082000 tree "WWDT1_GPRCM[%s]" base ad:0x40082800 group.long 0x0++0x3 line.long 0x0 "WWDT1_PWREN,Power enable" bitfld.long 0x0 0. "ENABLE,Enable the power" "0: Disable Power,1: Enable Power" wgroup.long 0x4++0x3 line.long 0x0 "WWDT1_RSTCTL,Reset Control" bitfld.long 0x0 1. "RESETSTKYCLR,Clear [GPRCM.STAT.RESETSTKY]" "0: Writing 0 has no effect,1: Clear reset sticky bit" bitfld.long 0x0 0. "RESETASSERT,Assert reset to the peripheral" "0: Writing 0 has no effect,1: Assert reset" rgroup.long 0x14++0x3 line.long 0x0 "WWDT1_STAT,Status Register" bitfld.long 0x0 16. "RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: The peripheral has not been reset since this bit..,1: The peripheral was reset since the last bit clear" tree.end base ad:0x40082000 newline group.long 0x1018++0x3 newline line.long 0x0 "WWDT1_PDBGCTL,Peripheral Debug Control" bitfld.long 0x0 0. "FREE,Free run control" "0: The peripheral freezes functionality while the..,1: The peripheral ignores the state of the Core.." tree "WWDT1_INT_EVENT[%s]" base ad:0x40083020 rgroup.long 0x0++0x3 line.long 0x0 "WWDT1_IIDX,Interrupt index" hexmask.long.byte 0x0 0.--4. 1. "STAT,Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC." group.long 0x8++0x3 line.long 0x0 "WWDT1_IMASK,Interrupt mask" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Clear Interrupt Mask,1: Set Interrupt Mask" rgroup.long 0x10++0x3 line.long 0x0 "WWDT1_RIS,Raw interrupt status" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Interrupt did not occur,1: Interrupt occurred" rgroup.long 0x18++0x3 line.long 0x0 "WWDT1_MIS,Masked interrupt status" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Interrupt did not occur,1: Interrupt occurred" wgroup.long 0x20++0x3 line.long 0x0 "WWDT1_ISET,Interrupt set" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Writing 0 has no effect,1: Set Interrupt" wgroup.long 0x28++0x3 line.long 0x0 "WWDT1_ICLR,Interrupt clear" bitfld.long 0x0 0. "INTTIM,Interval Timer Interrupt." "0: Writing 0 has no effect,1: Clear Interrupt" tree.end base ad:0x40082000 newline rgroup.long 0x10E0++0x3 newline line.long 0x0 "WWDT1_EVT_MODE,Event Mode" bitfld.long 0x0 0.--1. "INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: The interrupt or event line is disabled.,1: The interrupt or event line is in software mode.,2: The interrupt or event line is in hardware mode.,?" rgroup.long 0x10FC++0x3 line.long 0x0 "WWDT1_DESC,Module Description" hexmask.long.word 0x0 16.--31. 1. "MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness." hexmask.long.byte 0x0 12.--15. 1. "FEATUREVER,Feature Set for the module *instance*" newline hexmask.long.byte 0x0 8.--11. 1. "INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major rev of the IP" newline hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor rev of the IP" group.long 0x1100++0xB line.long 0x0 "WWDT1_WWDTCTL0,Window Watchdog Timer Control Register 0" bitfld.long 0x0 17. "STISM,Stop In Sleep Mode." "0: The WWDT continues to function in Sleep mode.,1: The WWDT stops in Sleep mode and resumes where.." bitfld.long 0x0 16. "MODE,Window Watchdog Timer Mode" "0: Window Watchdog Timer Mode. The WWDT will..,1: Interval Timer Mode. The WWDT acts as an.." newline bitfld.long 0x0 12.--14. "WINDOW1,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: 0% (No closed Window),1: 12.50% of the total timer period is closed window,2: 18.75% of the total timer period is closed window,3: 25% of the total timer period is closed window,4: 50% of the total timer period is closed window,5: 75% of the total timer period is closed window,6: 81.25% of the total timer period is closed window,7: 87.50% of the total timer period is closed window" bitfld.long 0x0 8.--10. "WINDOW0,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: 0% (No closed Window),1: 12.50% of the total timer period is closed window,2: 18.75% of the total timer period is closed window,3: 25% of the total timer period is closed window,4: 50% of the total timer period is closed window,5: 75% of the total timer period is closed window,6: 81.25% of the total timer period is closed window,7: 87.50% of the total timer period is closed window" newline bitfld.long 0x0 4.--6. "PER,Timer Period of the WWDT. These bits select the total watchdog timer count." "0: Total timer count is 2^25,1: Total timer count is 2^21,2: Total timer count is 2^18,3: Total timer count is 2^15,4: Total timer count is 2^12 (default),5: Total timer count is 2^10,6: Total timer count is 2^8,7: Total timer count is 2^6" bitfld.long 0x0 0.--2. "CLKDIV,Module Clock Divider Divide the clock source by CLKDIV+1." "0,1,2,3,4,5,6,7" line.long 0x4 "WWDT1_WWDTCTL1,Window Watchdog Timer Control Register 0" bitfld.long 0x4 0. "WINSEL,Close Window Select" "0: In window mode field WINDOW0 of WDDTCTL0 defines..,1: In window mode field WINDOW1 of WDDTCTL0 defines.." line.long 0x8 "WWDT1_WWDTCNTRST,Window Watchdog Timer Counter Reset Register" hexmask.long 0x8 0.--31. 1. "RESTART,Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter." rgroup.long 0x110C++0x3 line.long 0x0 "WWDT1_WWDTSTAT,Window Watchdog Timer Status Register" bitfld.long 0x0 0. "RUN,Watchdog running status flag." "0: Watchdog counter stopped.,1: Watchdog running." tree.end endif tree.end newline AUTOINDENT.OFF