; --------------------------------------------------------------------------------
; @Title: IMX93 Specific Menu
; @Props: Released
; @Author: NEJ, KRZ
; @Changelog: 2023-03-14 KRZ
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-A55, Cortex-M33F
; @Chip: IMX9311-CA55, IMX9311-CM33, IMX9312-CA55, IMX9312-CM33,
;        IMX9321-CA55, IMX9321-CM33, IMX9322-CA55, IMX9322-CM33,
;        IMX9331-CA55, IMX9331-CM33, IMX9332-CA55, IMX9332-CM33,
;        IMX9351-CA55, IMX9351-CM33, IMX9352-CA55, IMX9352-CM33
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menimx93.men 18835 2025-01-10 12:05:27Z kwisniewski $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)&&CPU.FEATURE(MPUTRANSLATION)
(
popup "[:mmu]MMU/MPU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU/MPU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU/MPU Table List" "MMU.List.PageTable"
IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
(
separator
)
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
ELSE
(
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
IF CPU.FEATURE(ITLBDUMP)||CPU.FEATURE(DTLBDUMP)||CPU.FEATURE(TLB0DUMP)||CPU.FEATURE(TLB1DUMP)
(
separator
)
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF CPU.FEATURE(MPUTRANSLATION)
(
popup "[:mmu]MPU"
(
menuitem "[:mmu]MPU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MPU Table List" "MMU.List.PageTable"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHEDUMP)||CPU.FEATURE(L1DCACHEDUMP)||CPU.FEATURE(L2CACHEDUMP)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXA55")
(
popup "[:chip]Core Registers (Cortex-A55)"
(
menuitem "[:chip]ID Registers[AArch64]"                                                     "per , ""Core Registers (Cortex-A55),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"                                 "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration"""
menuitem "[:chip]System Instructions[AArch64]"                                              "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration,System Instructions"""
menuitem "[:chip]Memory Management Unit[AArch64]"                                           "per , ""Core Registers (Cortex-A55),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                                        "per , ""Core Registers (Cortex-A55),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"                                  "per , ""Core Registers (Cortex-A55),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                                       "per , ""Core Registers (Cortex-A55),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                                           "per , ""Core Registers (Cortex-A55),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller System Registers[AArch64]"                    "per , ""Core Registers (Cortex-A55),AArch64,Generic Interrupt Controller System Registers"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                                                  "per , ""Core Registers (Cortex-A55),AArch64,Debug Registers"""
menuitem "[:chip]Activity Monitors Unit[AArch64]"                                           "per , ""AArch64,Activity Monitors Unit"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                                             "per , ""Core Registers (Cortex-A55),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch64]"                                             "per , ""Core Registers (Cortex-A55),AArch64,Watchpoint Registers"""
separator
menuitem "[:chip]LORegions Registers[AArch64]"                                              "per , ""Core Registers (Cortex-A55),AArch64,LORegions Registers"""
separator
menuitem "[:chip]DynamIQ Shared Unit[AArch64]"                                              "per , ""Core Registers (Cortex-A55),AArch64,DynamIQ Shared Unit"""
separator
menuitem "[:chip]ID Registers[AArch32]"                                                     "per , ""Core Registers (Cortex-A55),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"                                 "per , ""Core Registers (Cortex-A55),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                                           "per , ""Core Registers (Cortex-A55),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                                        "per , ""Core Registers (Cortex-A55),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"                                  "per , ""Core Registers (Cortex-A55),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                                       "per , ""Core Registers (Cortex-A55),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                                           "per , ""Core Registers (Cortex-A55),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller System Registers[AArch32]"                    "per , ""Core Registers (Cortex-A55),AArch32,Generic Interrupt Controller System Registers"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                                                  "per , ""Core Registers (Cortex-A55),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                                             "per , ""Core Registers (Cortex-A55),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch32]"                                             "per , ""Core Registers (Cortex-A55),AArch32,Watchpoint Registers"""
separator
menuitem "[:chip]DynamIQ Shared Unit[AArch32]"                                              "per , ""Core Registers (Cortex-A55),AArch32,DynamIQ Shared Unit"""
separator
menuitem "[:chip]Interrupt Controller"                                                      "per , ""Core Registers (Cortex-A55),Interrupt Controller"""
)
)
else if (CORENAME()=="CORTEXM33F")
(
popup "[:chip]Core Registers (Cortex-M33F)"
(
menuitem "[:chip]System Control"                                   "per , ""Core Registers (Cortex-M33F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                       "per , ""Core Registers (Cortex-M33F),Memory Protection Unit (MPU)"""
menuitem "[:chip]SAU;Security Attribution Unit"                    "per , ""Core Registers (Cortex-M33F),Security Attribution Unit (SAU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"        "per , ""Core Registers (Cortex-M33F),Nested Vectored Interrupt Controller (NVIC)"""
menuitem "[:chip]FPU;Floating-point Unit"                          "per , ""Core Registers (Cortex-M33F),Floating-point Unit (FPU)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                   "per , ""Core Registers (Cortex-M33F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"          "per , ""Core Registers (Cortex-M33F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"           "per , ""Core Registers (Cortex-M33F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
separator
menuitem "ANA_OSC"                                                          "per , ""ANA_OSC"""
menuitem "AXBS;Crossbar Switch"                                             "per , ""AXBS (Crossbar Switch)"""
menuitem "BBNSM;Battery-Backed Non-Secure Module"                           "per , ""BBNSM (Battery-Backed Non-Secure Module)"""
menuitem "BLK_CTRL_MLMIX;ML Mix Domain Block Control"                       "per , ""BLK_CTRL_MLMIX (ML Mix Domain Block Control)"""
menuitem "BLK_CTRL_NICMIX;NIC Mix Block Control"                            "per , ""BLK_CTRL_NICMIX (NIC Mix Block Control)"""
menuitem "BLK_CTRL_NS_AONMIX;Always-on Domain/Non-secure Block Control"     "per , ""BLK_CTRL_NS_AONMIX (Always-on Domain/Non-secure Block Control)"""
menuitem "BLK_CTRL_S_AONMIX;Always-on Domain/Secure Block Control"          "per , ""BLK_CTRL_S_AONMIX (Always-on Domain/Secure Block Control)"""
menuitem "BLK_CTRL_WAKEUPMIX;Wake-up Domain Block Control"                  "per , ""BLK_CTRL_WAKEUPMIX (Wake-up Domain Block Control)"""
menuitem "CACHE_ECC_MCM;ARM Cortex CM33 ECC MCM"                            "per , ""CACHE_ECC_MCM (ARM Cortex CM33 ECC MCM)"""
menuitem "CAN;FlexCAN"                                                      "per , ""CAN (FlexCAN)"""
menuitem "CCM;Clock Controller Module"                                      "per , ""CCM (Clock Controller Module)"""
menuitem "DDRC;DDR Memory Controller"                                       "per , ""DDRC (DDR Memory Controller)"""
menuitem "DDRMIX_BLK_CTRL;DDR Mix Domain Block Control"                     "per , ""DDRMIX_BLK_CTRL (DDR Mix Domain Block Control)"""
menuitem "EDMA3;Enhanced Direct Memory Access (eDMA3)"                      "per , ""EDMA3 (Enhanced Direct Memory Access (eDMA3))"""
menuitem "EDMA3_TCD;eDMA3 Transfer Control Descriptor"                      "per , ""EDMA3_TCD (eDMA3 Transfer Control Descriptor)"""
menuitem "EDMA4;Enhanced Direct Memory Access (eDMA4)"                      "per , ""EDMA4 (Enhanced Direct Memory Access (eDMA4))"""
menuitem "EDMA4_TCD;eDMA4 Transfer Control Descriptor"                      "per , ""EDMA4_TCD (eDMA4 Transfer Control Descriptor)"""
menuitem "ENET;Ethernet"                                                    "per , ""ENET (Ethernet)"""
menuitem "ENET_QOS_TSN;Ethernet Controller with TSN"                        "per , ""ENET_QOS_TSN (Ethernet Controller with TSN)"""
menuitem "FLEXIO;Flexible I/O"                                              "per , ""FLEXIO (Flexible I/O)"""
menuitem "FLEXSPI;Flexible Serial Peripheral Interface"                     "per , ""FLEXSPI (Flexible Serial Peripheral Interface)"""
menuitem "FSB"                                                              "per , ""FSB"""
menuitem "GPC_CPU_CTRL;General Power Controller (CPU Mode)"                 "per , ""GPC_CPU_CTRL (General Power Controller (CPU Mode))"""
menuitem "GPC_GLOBAL"                                                       "per , ""GPC_GLOBAL"""
menuitem "GPIO;General-Purpose Input/Output"                                "per , ""GPIO (General-Purpose Input/Output)"""
menuitem "I3C;Improved Inter-Integrated Circuit"                            "per , ""I3C (Improved Inter-Integrated Circuit)"""
menuitem "IOMUXC;IOMUX Controller"                                          "per , ""IOMUXC (IOMUX Controller)"""
menuitem "IPC;Integrated Peripheral Control"                                "per , ""IPC (Integrated Peripheral Control)"""
menuitem "ISI;Image Sensor Interface"                                       "per , ""ISI (Image Sensor Interface)"""
menuitem "LCDIF;LCD Interface"                                              "per , ""LCDIF (LCD Interface)"""
menuitem "LPI2C;Low Power Inter-Integrated Circuit"                         "per , ""LPI2C (Low Power Inter-Integrated Circuit)"""
menuitem "LPIT;Low Power Periodic Interrupt Timer"                          "per , ""LPIT (Low Power Periodic Interrupt Timer)"""
menuitem "LPSPI;Low Power Serial Peripheral Interface"                      "per , ""LPSPI (Low Power Serial Peripheral Interface)"""
menuitem "LPTMR;Low-Power Timer"                                            "per , ""LPTMR (Low-Power Timer)"""
menuitem "LPTPM;Low Power Timer/PWM"                                        "per , ""LPTPM (Low Power Timer/PWM)"""
menuitem "LPUART;Low Power Universal Asynchronous Receiver/Transmitter"     "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter)"""
menuitem "LPWDOG;Watchdog Timers"                                           "per , ""LPWDOG (Watchdog Timers)"""
menuitem "MCM;Miscellaneous Control Module"                                 "per , ""MCM (Miscellaneous Control Module)"""
menuitem "MECC256;Memory ECC Controller"                                    "per , ""MECC256 (Memory ECC Controller)"""
menuitem "MEDIAMIX_BLK_CTRL;Media Mix Domain Block Control"                 "per , ""MEDIAMIX_BLK_CTRL (Media Mix Domain Block Control)"""
menuitem "MIPI_CSI"                                                         "per , ""MIPI_CSI"""
menuitem "MIPI_DSI"                                                         "per , ""MIPI_DSI"""
menuitem "MU;Messaging Unit"                                                "per , ""MU (Messaging Unit)"""
menuitem "NPU;Neural Processing Unit"                                       "per , ""NPU (Neural Processing Unit)"""
menuitem "OTFAD;On-The-Fly AES Decryption"                                  "per , ""OTFAD (On-The-Fly AES Decryption)"""
menuitem "PDM;PDM Microphone Interface"                                     "per , ""PDM (PDM Microphone Interface)"""
menuitem "PLL"                                                              "per , ""PLL"""
menuitem "PXP;Pixel Pipeline"                                               "per , ""PXP (Pixel Pipeline)"""
menuitem "S3MUA"                                                            "per , ""S3MUA"""
menuitem "SAI;Synchronous Audio Interface"                                  "per , ""SAI (Synchronous Audio Interface)"""
menuitem "SAR_ADC;Analog-to-Digital Converter"                              "per , ""SAR_ADC (Analog-to-Digital Converter)"""
menuitem "SEMA42;Semaphores2"                                               "per , ""SEMA42 (Semaphores2)"""
menuitem "SPDIF;Audio Transceiver"                                          "per , ""SPDIF (Audio Transceiver)"""
menuitem "SRC;System Reset Controller"                                      "per , ""SRC (System Reset Controller)"""
menuitem "SYS_CTR;System Counter"                                           "per , ""SYS_CTR (System Counter)"""
menuitem "SYSPM;Performance Monitor"                                        "per , ""SYSPM (Performance Monitor)"""
menuitem "TCM_ECC_MCM;Tightly Coupled Memory"                               "per , ""TCM_ECC_MCM (Tightly Coupled Memory)"""
menuitem "TMU;Thermal Monitoring Unit"                                      "per , ""TMU (Thermal Monitoring Unit)"""
menuitem "TRDC;Trusted Resource Domain Control"                             "per , ""TRDC (Trusted Resource Domain Control)"""
menuitem "TRGMUX;Trigger Mux"                                               "per , ""TRGMUX (Trigger Mux)"""
menuitem "TSTMR;Timer"                                                      "per , ""TSTMR (Timer)"""
menuitem "USB;Universal Serial Bus Controller"                              "per , ""USB (Universal Serial Bus Controller)"""
menuitem "USBNC;USB Non-Core Memory"                                        "per , ""USBNC (USB Non-Core Memory)"""
menuitem "USDHC;Ultra Secured Digital Host Controller"                      "per , ""USDHC (Ultra Secured Digital Host Controller)"""
menuitem "WAKEUP_AHBRM"                                                     "per , ""WAKEUP_AHBRM"""
menuitem "XCACHE;Cache Memory Controller"                                   "per , ""XCACHE (Cache Memory Controller)"""
)
)