; -------------------------------------------------------------------------------- ; @Title: MAX32650 On-Chip Peripherals ; @Props: Released ; @Author: NEJ ; @Changelog: 2025-06-27 NEJ ; @Manufacturer: MAXIM - Maxim Integrated Products, Inc. ; @Doc: Generated (TRACE32, build: 180251.), based on: ; max32650.svd (MAX32650 1.0.6, 2018-07-11) ; @Core: Cortex-M4F ; @Chip: MAX32650, MAX32651, MAX32652 ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permax32650.per 19674 2025-07-01 12:37:46Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ADC (10-bit Analog to Digital Converter)" base ad:0x40034000 group.long 0x0++0x3 line.long 0x0 "CTRL,ADC Control" bitfld.long 0x0 17. "data_align,ADC Data Alignment Select" "0,1" bitfld.long 0x0 16. "adc_xref,Enable Use of ADC External Reference" "0,1" hexmask.long.byte 0x0 12.--15. 1. "ch_sel,ADC Channel Select" bitfld.long 0x0 11. "clk_en,ADC Clock Enable" "0,1" bitfld.long 0x0 10. "ref_sel,ADC Reference (VRef) Select (INTERNAL ONLY)" "0,1" bitfld.long 0x0 9. "scale,ADC Scale" "0,1" newline bitfld.long 0x0 8. "ref_scale,ADC Reference Scale" "0,1" bitfld.long 0x0 4. "chgpump_pwr,ADC Charge Pump Power Up" "0,1" bitfld.long 0x0 3. "refbuf_pwr,ADC Reference Buffer Power Up" "0,1" bitfld.long 0x0 1. "pwr,ADC Power Up" "0,1" bitfld.long 0x0 0. "start,Start ADC Conversion" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "STATUS,ADC Status" bitfld.long 0x0 3. "overflow,ADC Overflow" "0,1" bitfld.long 0x0 2. "afe_pwr_up_active,AFE Power Up Delay Active" "0,1" bitfld.long 0x0 0. "active,ADC Conversion In Progress" "0,1" line.long 0x4 "DATA,ADC Output Data" hexmask.long.word 0x4 0.--15. 1. "adc_data,ADC Converted Sample Data Output" group.long 0xC++0x3 line.long 0x0 "INTR,ADC Interrupt Control Register" rbitfld.long 0x0 22. "pending,ADC Interrupt Pending Status" "0,1" eventfld.long 0x0 20. "overflow_if,ADC Overflow Interrupt Flag" "0,1" eventfld.long 0x0 19. "lo_limit_if,ADC Lo Limit Monitor Interrupt Flag" "0,1" eventfld.long 0x0 18. "hi_limit_if,ADC Hi Limit Monitor Interrupt Flag" "0,1" eventfld.long 0x0 17. "ref_ready_if,ADC Reference Ready Interrupt Flag" "0,1" eventfld.long 0x0 16. "done_if,ADC Done Interrupt Flag" "0,1" newline bitfld.long 0x0 4. "overflow_ie,ADC Overflow Interrupt Enable" "0,1" bitfld.long 0x0 3. "lo_limit_ie,ADC Lo Limit Monitor Interrupt Enable" "0,1" bitfld.long 0x0 2. "hi_limit_ie,ADC Hi Limit Monitor Interrupt Enable" "0,1" bitfld.long 0x0 1. "ref_ready_ie,ADC Reference Ready Interrupt Enable" "0,1" bitfld.long 0x0 0. "done_ie,ADC Done Interrupt Enable" "0,1" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "LIMIT[$1],ADC Limit" bitfld.long 0x0 29. "ch_hi_limit_en,High Limit Monitoring Enable" "0,1" bitfld.long 0x0 28. "ch_lo_limit_en,Low Limit Monitoring Enable" "0,1" hexmask.long.byte 0x0 24.--27. 1. "ch_sel,ADC Channel Select" hexmask.long.word 0x0 12.--21. 1. "ch_hi_limit,High Limit Threshold" hexmask.long.word 0x0 0.--9. 1. "ch_lo_limit,Low Limit Threshold" repeat.end tree.end tree "AES_KEY (AES Key Registers)" base ad:0x40005000 group.long 0x0++0x3 line.long 0x0 "aes_key0,AES Key 0" group.long 0x80++0x3 line.long 0x0 "aes_key1,AES Key 1" group.long 0x100++0x3 line.long 0x0 "aes_key2,AES Key 2" group.long 0x180++0x3 line.long 0x0 "aes_key3,AES Key 3" tree.end tree "BBFC (Battery-Backed Function Control)" base ad:0x40005800 group.long 0x0++0x3 line.long 0x0 "BBFCR0,Function Control Register 0." bitfld.long 0x0 8. "RDSDLLEN,Hyperbus RDS DLL Power Up Control." "0: Disabled.,1: Enabled." hexmask.long.byte 0x0 4.--7. 1. "CKNPDRV,Hyperbus CKN Pad Driver Control." hexmask.long.byte 0x0 0.--3. 1. "CKPDRV,Hyperbus CK Pad Driver Control." tree.end tree "BBSIR (Battery-Backed Registers)" base ad:0x40005400 rgroup.long 0x8++0x7 line.long 0x0 "BB_SIR2,System Init. Configuration Register 2." line.long 0x4 "BB_SIR3,System Init. Configuration Register 3." tree.end tree "CLCD (Color LCD Controller)" base ad:0x40031000 group.long 0x0++0x13 line.long 0x0 "CLK,LCD Clock Register" bitfld.long 0x0 20. "PASCLK,Clock Active on Data" "0: Always Active,1: ACTIVE ON DATA" bitfld.long 0x0 19. "EDGE,Edge Selection" "0: Positve edge,1: Negative Edge" bitfld.long 0x0 18. "HPOL,H Polarity" "0: Active Low,1: Active Hi" newline bitfld.long 0x0 17. "VPOL,V Polarity" "0,1" bitfld.long 0x0 16. "DPOL,D Polarity" "0: Active Hi,1: Active Low" hexmask.long.byte 0x0 8.--15. 1. "ACB,ACB" newline hexmask.long.byte 0x0 0.--7. 1. "CLKDIV,Clock divsor" line.long 0x4 "VTIM_0,LCD Vertical Timing 0 Register" hexmask.long.byte 0x4 16.--23. 1. "VBACKPORCH,V BACK PORCH" hexmask.long.byte 0x4 0.--7. 1. "VLINES,V Lines" line.long 0x8 "VTIM_1,LCD Vertical Timing 1 Register" hexmask.long.byte 0x8 16.--23. 1. "VFRONTPORCH,V Front PORCH" hexmask.long.byte 0x8 0.--7. 1. "VSYNCWIDTH,V Sync Width" line.long 0xC "HTIM,LCD Horizontal Timing Register." hexmask.long.byte 0xC 24.--31. 1. "HBACKPORCH,Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP=(HBACKPORCH+1)" hexmask.long.byte 0xC 16.--23. 1. "HSIZE,Horizontal Front Porch Size in Pixels = (HSIZE + 1)*16" hexmask.long.byte 0xC 8.--15. 1. "HFRONTPORCH,Horizontal Front Porch size in lines from 1 to 256" newline hexmask.long.byte 0xC 0.--7. 1. "HSYNCWIDTH,Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks" line.long 0x10 "CTRL,LCD Control Register" bitfld.long 0x10 22. "PEN,PEN" "0,1" bitfld.long 0x10 21. "LPOL,LPOL" "0: ACTIVE HIGH,1: ACTIVE LOW" bitfld.long 0x10 19.--20. "BURST,BURST" "0: WORDS4,1: WORDS8,?,?" newline bitfld.long 0x10 15. "C24,C24" "0,1" bitfld.long 0x10 12.--13. "EMODE,EMODE" "0: LLBP,1: BBBP,2: LBBP,3: RFU" bitfld.long 0x10 11. "MODE565,MODE565" "0: MODE 555,1: MODE 565" newline bitfld.long 0x10 8.--10. "BPP,BPP" "0: BPP 1,1: BPP 2,2: BPP 4,3: BPP 8,4: BPP 16,5: BPP 24,?,?" hexmask.long.byte 0x10 4.--7. 1. "DISPTYPE,Display Type" bitfld.long 0x10 1.--2. "VISEL,VI Select" "0: On Vertical Sync,1: On Vertical Back Porch,2: On Active Video,3: On Vertical Front Porch" newline bitfld.long 0x10 0. "LCDEN,LCD Enable" "0: Disable,1: Enable" group.long 0x18++0x3 line.long 0x0 "FR,FR" group.long 0x20++0x7 line.long 0x0 "INT_EN,LCD Interrupt Enable Register." bitfld.long 0x0 3. "BERR,BERR Interupt Enable" "0,1" bitfld.long 0x0 2. "VCI,VCI Interupt Enable" "0,1" bitfld.long 0x0 1. "ADRRDY,Address Ready Interupt Enable" "0,1" newline bitfld.long 0x0 0. "UFLO,Under FLow Interupt Enable" "0,1" line.long 0x4 "STAT,LCD Status Register." bitfld.long 0x4 8. "LCDIDLE,LCD IDLE Staus" "0: BUSY,1: READY" bitfld.long 0x4 3. "BERR,BERR Interupt Status" "0: No interrupt pending,1: Clears the interrupt flag" bitfld.long 0x4 2. "VCI,VCI Interupt Status" "0: No interrupt pending,1: Clears the interrupt flag" newline bitfld.long 0x4 1. "ADRRDY,Address Ready Interupt Status" "0: No interrupt pending,1: Clears the interrupt flag" bitfld.long 0x4 0. "UFLO,Under FLow Interupt Status" "0: No interrupt pending,1: Clears the interrupt flag" group.long 0x30++0x3 line.long 0x0 "HV_PHASE,HV Phase" repeat 256. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "PALETTE[$1],Palette" repeat.end tree.end tree "CRYPTO (Cryptographic Engine)" base ad:0x40001000 group.long 0x0++0x1F line.long 0x0 "CTRL,Crypto Control Register." rbitfld.long 0x0 31. "DONE,Done. One or more cryptographic calculations complete (logical OR of done flags)." "0: Not Done.,1: Done." rbitfld.long 0x0 30. "RDY,Ready. Crypto block ready for more data." "0: Busy.,1: Ready." newline rbitfld.long 0x0 29. "ERR,AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set the DMA will stop. This bit can only be cleared by resetting the crypto block." "0: No Error.,1: Error." bitfld.long 0x0 28. "MAA_DONE,MAA Done. MAA operation is complete. This bit must be cleared before starting a new MAA operation. This bit is read only while the MAA is in progress. This bit is negate of MAA_CTRL.STC." "0: Not Done.,1: Done." newline bitfld.long 0x0 27. "CPH_DONE,Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation." "0: Not Done.,1: Done." bitfld.long 0x0 26. "HSH_DONE,Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation." "0: Not Done.,1: Done." newline bitfld.long 0x0 25. "GLS_DONE,Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization.." "0: Not Done.,1: Done." bitfld.long 0x0 24. "DMA_DONE,DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation." "0: Not Done.,1: Done." newline bitfld.long 0x0 15. "DMADNEMSK,DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored." "0: DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.,1: DMA_DONE used in setting CRYPTO_CTRL.DONE bit." bitfld.long 0x0 14. "FLAG_MODE,Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep i.e. once set it will remain set until a reset occurs." "0: Unrestricted write (0 or 1) of..,1: Access to CRYPTO_CTRL[27:24] are write 1 to.." newline bitfld.long 0x0 10.--11. "RDSRC,Read FIFO Source Select. This field selects the source of the read FIFO. Typically it is set to use the DMA. To implement a memset() function the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers the.." "0: DMA Disable.,1: DMA Or APB.,2: RNG.,?" bitfld.long 0x0 8.--9. "WRSRC,Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO it is always written out the DMA. To decrypt or encrypt data the write FIFO source should be set to the cipher.." "0: None.,1: Cipher Output.,2: Read FIFO.,3: Reserved. Do not use." newline bitfld.long 0x0 7. "WAIT_POL,Wait Pin Polarity. When the wait pin is enabled this bit selects its active state." "0: Active Low.,1: Active High." bitfld.long 0x0 6. "WAIT_EN,Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready." "0: Disable,1: Enable" newline bitfld.long 0x0 5. "BSI,Byte Swap Input. Note. No byte swap will occur if there is not a full word." "0: Disable,1: Enable" bitfld.long 0x0 4. "BSO,Byte Swap Output. Note. No byte swap will occur if there is not a full word." "0: Disable,1: Enable" newline bitfld.long 0x0 2. "SRC,Source Select. This bit selects the hash function and CRC generator input source." "0: Input FIFO,1: Output FIFO" bitfld.long 0x0 1. "INTR,Interrupt Enable. Generates an interrupt when done or error set." "0: Disable,1: Enable" newline bitfld.long 0x0 0. "RST,Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL CIPHER_CTRL HASH_CTRL CRC_CTRL MAA_CTRL (with the exception of.." "0: Reset complete.,1: Reset in progress." line.long 0x4 "CIPHER_CTRL,Cipher Control Register." bitfld.long 0x4 8.--10. "MODE,Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB OFB or CTR modes." "0: ECB Mode.,1: CBC Mode.,2: CFB (AES only).,3: OFB (AES only).,4: CTR (AES only).,?,?,?" bitfld.long 0x4 4.--6. "CIPHER,Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation." "0: Disabled.,1: AES 128.,2: AES 192.,3: AES 256.,4: DES.,5: Triple DES.,?,?" newline bitfld.long 0x4 2.--3. "SRC,Source of Random key." "0: User cipher key (0x4000_1060).,?,2: Key from battery-backed register file..,3: Key from battery-backed register file.." bitfld.long 0x4 1. "KEY,Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done it sets the appropriate crypto DMA Done flag." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x4 0. "ENC,Encrypt. Select encryption or decryption of input data." "0: Encrypt.,1: Decrypt." line.long 0x8 "HASH_CTRL,HASH Control Register." bitfld.long 0x8 5. "LAST,Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding which includes the trailing bit 1 .." "0: No Effect.,1: Last Message Data." bitfld.long 0x8 2.--4. "HASH,Hash function selection." "0: Disabled.,1: SHA-1.,2: SHA 224.,3: SHA 256.,4: SHA 384.,5: SHA 512.,?,?" newline bitfld.long 0x8 1. "XOR,XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad." "0: Disable.,1: Enable." bitfld.long 0x8 0. "INIT,Initialize. Initializes hash registers with standard constants." "0: No operation/complete.,1: Start operation." line.long 0xC "CRC_CTRL,CRC Control Register." bitfld.long 0xC 5. "HRST,Hamming Reset. Reset Hamming code ECC generator for next block." "0: Reserved. Do not use.,1: Starts reset operation." bitfld.long 0xC 4. "HAM,Hamming Code Enable. Enable hamming code calculation." "0: Disable.,1: Enable." newline bitfld.long 0xC 3. "ENT,Entropy Enable. If the PRNG is enabled this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the.." "0: Disable.,1: Enable." bitfld.long 0xC 2. "PRNG,Pseudo Random Number Generator Enable. If entropy is disabled this outputs one byte of pseudo random data per clock cycle. If entropy is enabled data is output at a rate of one bit per clock cycle." "0: Disable.,1: Enable." newline bitfld.long 0xC 1. "MSB,MSB select. This bit selects the order of calculating CRC on data." "0: LSB First.,1: MSB First." bitfld.long 0xC 0. "CRC,Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled." "0: Disable.,1: Enable." line.long 0x10 "DMA_SRC,Crypto DMA Source Address." hexmask.long 0x10 0.--31. 1. "ADDR,DMA Source Address." line.long 0x14 "DMA_DEST,Crypto DMA Destination Address." hexmask.long 0x14 0.--31. 1. "ADDR,DMA Destination Address." line.long 0x18 "DMA_CNT,Crypto DMA Byte Count." hexmask.long 0x18 0.--31. 1. "ADDR,DMA Byte Address." line.long 0x1C "MAA_CTRL,MAA Control Register." hexmask.long.byte 0x1C 28.--31. 1. "TMA,Temporary Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 't'." hexmask.long.byte 0x1C 24.--27. 1. "RMA,Result Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'r'." newline hexmask.long.byte 0x1C 20.--23. 1. "BMA,Multiplicand / Operand B Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'b'." hexmask.long.byte 0x1C 16.--19. 1. "AMA,Multiplier / Operand A Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'a'." newline bitfld.long 0x1C 14.--15. "MMS,Modulus Memory Select. These bits select the starting position of the parameter 'm' within the logical segment 5." "0,1,2,3" bitfld.long 0x1C 12.--13. "EMS,Exponent Memory Select. These bits select the starting position of the parameter 'e' within the logical segment specified by EMA." "0,1,2,3" newline bitfld.long 0x1C 10.--11. "BMS,Multiplicand B Memory Select. These bits select the starting position of the parameter 'b' within the logical segment specified by BMA." "0,1,2,3" bitfld.long 0x1C 8.--9. "AMS,Multiplier A Memory Select. These bits select the starting position of the parameter 'a' within the logical segment specified by AMA." "0,1,2,3" newline bitfld.long 0x1C 7. "MAAER,MAA Error. The MAAER bit defaults to 0 and can only be set by hardware. Once set it must be cleared by software otherwise no new operation can be initiated. Software writes 1 to this bit has no effect and MAAER will maintain its original state." "0: No Error.,1: Error." bitfld.long 0x1C 4. "OCALC,Optimized Calculation Control. For optimized calculation unnecessary multiply operations after normalizing the exponent are skipped." "0: Disable.,1: Enable." newline bitfld.long 0x1C 1.--3. "CLC,Calculation Configuration. These bits select desired calculation." "0: Exponentiation.,1: Square operation.,2: Multiplication.,3: Square followed by a multiplication.,4: Addition.,5: Subtraction.,?,?" bitfld.long 0x1C 0. "STC,Start Calculation. This bit functions as both the control and the status of the MAA. If the size value in the MAWS register is invalid the STC bit will be cleared by hardware immediately. Otherwise the STC bit is automatically cleared following the.." "0: No operation/complete.,1: Start operation." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x20)++0x3 line.long 0x0 "DIN[$1],Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any.." hexmask.long 0x0 0.--31. 1. "DATA,Crypto Data Input. Input can be written to this register instead of using DMA." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0x30)++0x3 line.long 0x0 "DOUT[$1],Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes. this register holds the result of most recent encryption or decryption.." hexmask.long 0x0 0.--31. 1. "DATA,Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm." repeat.end group.long 0x40++0x7 line.long 0x0 "CRC_POLY,CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit." hexmask.long 0x0 0.--31. 1. "POLY,CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit." line.long 0x4 "CRC_VAL,CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit." hexmask.long 0x4 0.--31. 1. "VAL,CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit." rgroup.long 0x48++0x3 line.long 0x0 "CRC_PRNG,Pseudo Random Value. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled." hexmask.long 0x0 0.--31. 1. "PRNG,Pseudo Random Value. Output of the Galois Field Shift Register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled." group.long 0x4C++0x3 line.long 0x0 "HAM_ECC,Hamming ECC Register." bitfld.long 0x0 16. "PAR,Parity. This is the parity of the entire array." "0: Even.,1: Odd." hexmask.long.word 0x0 0.--15. 1. "ECC,Hamming ECC Value. These bits are the even parity of their corresponding bit groups." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x50)++0x3 line.long 0x0 "CIPHER_INIT[$1],Initial Vector. For block cipher operations that use CBC. CFB. OFB. or CNTR modes. this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap.." hexmask.long 0x0 0.--31. 1. "IVEC,Initial Vector. For block cipher operations that use CBC CFB OFB or CNTR modes this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) wgroup.long ($2+0x60)++0x3 line.long 0x0 "CIPHER_KEY[$1],Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits." hexmask.long 0x0 0.--31. 1. "KEY,Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits." repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "HASH_DIGEST[$1],This register holds the calculated hash value. This register is affected by the endian swap bits." hexmask.long 0x0 0.--31. 1. "HASH,This register holds the calculated hash value. This register is affected by the endian swap bits." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "HASH_MSG_SZ[$1],Message Size. This register holds the lowest 32-bit of message size in bytes." hexmask.long 0x0 0.--31. 1. "MSGSZ,Message Size. This register holds the lowest 32-bit of message size in bytes." repeat.end group.long 0xD0++0x3 line.long 0x0 "MAA_MAWS,MAA Word Size. This register defines the number of bits for a modular operation. This register must be set to a valid value prior to the MAA operation start. Valid values are from 1 to 2048. Invalid values are ignored and will not initiate a MAA.." hexmask.long.word 0x0 0.--11. 1. "MAWS,MAA Word Size." tree.end tree "DMA (DMA Controller)" base ad:0x40028000 group.long 0x0++0x3 line.long 0x0 "CN,DMA Control Register." bitfld.long 0x0 15. "CH15_IEN,Channel 15 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 14. "CH14_IEN,Channel 14 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 13. "CH13_IEN,Channel 13 Interrupt Enable." "0: Disable.,1: Enable." newline bitfld.long 0x0 12. "CH12_IEN,Channel 12 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 11. "CH11_IEN,Channel 11 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 10. "CH10_IEN,Channel 10 Interrupt Enable." "0: Disable.,1: Enable." newline bitfld.long 0x0 9. "CH9_IEN,Channel 9 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 8. "CH8_IEN,Channel 8 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 7. "CH7_IEN,Channel 7 Interrupt Enable." "0: Disable.,1: Enable." newline bitfld.long 0x0 6. "CH6_IEN,Channel 6 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 5. "CH5_IEN,Channel 5 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 4. "CH4_IEN,Channel 4 Interrupt Enable." "0: Disable.,1: Enable." newline bitfld.long 0x0 3. "CH3_IEN,Channel 3 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 2. "CH2_IEN,Channel 2 Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 1. "CH1_IEN,Channel 1 Interrupt Enable." "0: Disable.,1: Enable." newline bitfld.long 0x0 0. "CH0_IEN,Channel 0 Interrupt Enable." "0: Disable.,1: Enable." rgroup.long 0x4++0x3 line.long 0x0 "INTR,DMA Interrupt Register." bitfld.long 0x0 15. "CH15_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 14. "CH14_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 13. "CH13_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." newline bitfld.long 0x0 12. "CH12_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 11. "CH11_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 10. "CH10_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." newline bitfld.long 0x0 9. "CH9_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 8. "CH8_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 7. "CH7_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." newline bitfld.long 0x0 6. "CH6_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 5. "CH5_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 4. "CH4_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." newline bitfld.long 0x0 3. "CH3_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 2. "CH2_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 1. "CH1_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." newline bitfld.long 0x0 0. "CH0_IPEND,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40028100 ad:0x40028104 ad:0x40028108 ad:0x4002810C ad:0x40028110 ad:0x40028114 ad:0x40028118 ad:0x4002811C ad:0x40028120 ad:0x40028124 ad:0x40028128 ad:0x4002812C ad:0x40028130 ad:0x40028134 ad:0x40028138 ad:0x4002813C) tree "CH[$1]" base $2 group.long ($2+0x100)++0x1F line.long 0x0 "CFG,DMA Channel Configuration Register." bitfld.long 0x0 31. "CTZIEN,Count-to-zero Interrupts Enable. When enabled the IPEND will be set to 1 whenever a count-to-zero event occurs." "0: Disable.,1: Enable." bitfld.long 0x0 30. "CHDIEN,Channel Disable Interrupt Enable. When enabled the IPEND will be set to 1 whenever CH_ST changes from 1 to 0." "0: Disable.,1: Enable." hexmask.long.byte 0x0 24.--28. 1. "BRST,Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field." newline bitfld.long 0x0 22. "DSTINC,Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals." "0: Disable.,1: Enable." bitfld.long 0x0 20.--21. "DSTWD,Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)." "0: Byte.,1: Halfword.,2: Word.,?" bitfld.long 0x0 18. "SRCINC,Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals." "0: Disable.,1: Enable." newline bitfld.long 0x0 16.--17. "SRCWD,Source Width. In most cases this will be the data width of each AHB transactions. However the width will be reduced in the cases where DMA_CNT indicates a smaller value." "0: Byte.,1: Halfword.,2: Word.,?" bitfld.long 0x0 14.--15. "PSSEL,Pre-Scale Select. Selects the Pre-Scale divider for timer clock input." "0: Disable timer.,1: hclk / 256.,2: hclk / 64k.,3: hclk / 16M." bitfld.long 0x0 11.--13. "TOSEL,Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers the actual number of.." "0: Timeout of 3 to 4 prescale clocks.,1: Timeout of 7 to 8 prescale clocks.,2: Timeout of 15 to 16 prescale clocks.,3: Timeout of 31 to 32 prescale clocks.,4: Timeout of 63 to 64 prescale clocks.,5: Timeout of 127 to 128 prescale clocks.,6: Timeout of 255 to 256 prescale clocks.,7: Timeout of 511 to 512 prescale clocks." newline bitfld.long 0x0 10. "REQWAIT,Request Wait Enable. When enabled delay timer start until DMA request transitions from active to inactive." "0: Disable.,1: Enable." hexmask.long.byte 0x0 4.--9. 1. "REQSEL,Request Select. Select DMA request line for this channel. If memory-to-memory is selected the channel operates as if the request is always active." bitfld.long 0x0 2.--3. "PRI,DMA Priority." "0: Highest Priority.,1: Medium High Priority.,2: Medium Low Priority.,3: Lowest Priority." newline bitfld.long 0x0 1. "RLDEN,Reload Enable. Setting this bit to 1 enables DMA_SRC DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer.." "0: Disable.,1: Enable." bitfld.long 0x0 0. "CHEN,Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0." "0: Disable.,1: Enable." line.long 0x4 "ST,DMA Channel Status Register." eventfld.long 0x4 6. "TO_ST,Time-Out Status." "0: The event has not occurred.,1: Clears the interrupt flag" eventfld.long 0x4 4. "BUS_ERR,Bus Error. Indicates that an AHB abort was received and the channel has been disabled." "0: The event has not occurred.,1: Clears the interrupt flag" eventfld.long 0x4 3. "RLD_ST,Reload Status." "0: The event has not occurred.,1: Clears the interrupt flag" newline eventfld.long 0x4 2. "CTZ_ST,Count-to-Zero (CTZ) Status" "0: The event has not occurred.,1: Clears the interrupt flag" rbitfld.long 0x4 1. "IPEND,Channel Interrupt." "0: No interrupt is pending.,1: An interrupt is pending." rbitfld.long 0x4 0. "CH_ST,Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration address and count registers for the channel. Whenever this bit is cleared by hardware the DMA_CFG.CHEN bit is also cleared (if not cleared.." "0: Disable.,1: Enable." line.long 0x8 "SRC,Source Device Address. If SRCINC=1. the counter bits are incremented by 1.2. or 4. depending on the data width of each AHB cycle. For peripheral transfers. some or all of the actual address bits are fixed. If SRCINC=0. this register remains constant." hexmask.long 0x8 0.--31. 1. "ADDR" line.long 0xC "DST,Destination Device Address. For peripheral transfers. some or all of the actual address bits are fixed. If DSTINC=1. this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1. 2. or 4. depending on the data width.." hexmask.long 0xC 0.--31. 1. "ADDR" line.long 0x10 "CNT,DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1. 2. or 4 depending on the data width of each AHB cycle. When the counter reaches 0. a.." hexmask.long.tbyte 0x10 0.--23. 1. "CNT,DMA Counter." line.long 0x14 "SRC_RLD,Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition." hexmask.long 0x14 0.--30. 1. "SRC_RLD,Source Address Reload Value." line.long 0x18 "DST_RLD,Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition." hexmask.long 0x18 0.--30. 1. "DST_RLD,Destination Address Reload Value." line.long 0x1C "CNT_RLD,DMA Channel Count Reload Register." bitfld.long 0x1C 31. "RLDEN,Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs." "0: Disable.,1: Enable." hexmask.long.tbyte 0x1C 0.--23. 1. "CNT_RLD,Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition." tree.end repeat.end tree.end tree "EMCC (External Memory Cache Controller)" base ad:0x40033000 rgroup.long 0x0++0x7 line.long 0x0 "CACHE_ID,Cache ID Register." hexmask.long.byte 0x0 10.--15. 1. "CCHID,Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter." hexmask.long.byte 0x0 6.--9. 1. "PARTNUM,Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter." newline hexmask.long.byte 0x0 0.--5. 1. "RELNUM,Release Number. Identifies the RTL release version." line.long 0x4 "MEMCFG,Memory Configuration Register." hexmask.long.word 0x4 16.--31. 1. "MEMSZ,Main Memory Size. Indicates the total size in units of 128 Kbytes of code memory accessible to the cache controller." hexmask.long.word 0x4 0.--15. 1. "CCHSZ,Cache Size. Indicates total size in Kbytes of cache." group.long 0x100++0x3 line.long 0x0 "CACHE_CTRL,Cache Control and Status Register." bitfld.long 0x0 16. "CACHE_RDY,Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0 the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line.." "0: Not Ready.,1: Ready." bitfld.long 0x0 2. "CWFST_DIS,Critical word first and streaming disable. This bit only writeable while the cache is disabled." "0: Critical word first and streaming enabled.,1: Critical word first and streaming disabled." newline bitfld.long 0x0 1. "WRITE_ALLOC_EN,Write Allocate Enable. This bit only writable while the cache is disabled." "0: Write-no-allocate.,1: Write-allocate enabled." bitfld.long 0x0 0. "CACHE_EN,Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated." "0: Cache Bypassed. Instruction data is stored in..,1: Cache Enabled." group.long 0x700++0x3 line.long 0x0 "INVALIDATE,Invalidate All Cache Contents. Any time this register location is written (regardless of the data value). the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the.." hexmask.long 0x0 0.--31. 1. "IA,Invalidate all cache contents." tree.end tree "FLC (Flash Controller)" base ad:0x40029000 group.long 0x0++0xB line.long 0x0 "ADDR,Flash Write Address." hexmask.long 0x0 0.--31. 1. "ADDR,Address for next operation." line.long 0x4 "CLKDIV,Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller." hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller." line.long 0x8 "CN,Flash Control Register." hexmask.long.byte 0x8 28.--31. 1. "UNLOCK,Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed." bitfld.long 0x8 27. "BRST,Burst Mode Enable." "0: Disable,1: Enable" rbitfld.long 0x8 25. "LVE,Low Voltage Read Enable" "0: Disabled,1: Enabled" newline rbitfld.long 0x8 24. "PEND,Flash Pending. When Flash operation is in progress (busy) Flash reads and writes will fail. When PEND is set write to all Flash registers with exception of the Flash interrupt register are ignored." "0: Idle.,1: Busy." hexmask.long.byte 0x8 8.--15. 1. "ERASE_CODE,Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete." bitfld.long 0x8 4. "WDTH,Data Width. This bits selects write data width." "0: 128-bit.,1: 32-bit." newline bitfld.long 0x8 2. "PGE,Page Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 1. "ME,Mass Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 0. "WR,Write. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation." group.long 0x24++0x3 line.long 0x0 "INTR,Flash Interrupt Register." bitfld.long 0x0 9. "AFIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 8. "DONEIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x0 1. "AF,Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware." "0: No Failure.,1: Failure occurs." newline bitfld.long 0x0 0. "DONE,Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion." "0: No interrupt is pending,1: An interrupt is pending" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DATA[$1],Flash Write Data." hexmask.long 0x0 0.--31. 1. "DATA,Data next operation." repeat.end wgroup.long 0x40++0x3 line.long 0x0 "ACNTL,Access Control Register. Writing the ACNTL register with the following values in the order shown. allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When.." hexmask.long 0x0 0.--31. 1. "ACNTL,Access control." tree.end tree "GCR (Global Control Registers)" base ad:0x40000000 group.long 0x0++0x1B line.long 0x0 "SCON,System Control." bitfld.long 0x0 16.--17. "OVR,Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range." "0: 0.9V +/- 10 Percent,1: 1.0V +/- 10 Percent,2: 1.1V +/- 10 Percent,?" bitfld.long 0x0 15. "CHKRES,ROM Checksum Result. This bit is only valid when CHKRD=1." "0: ROM Checksum Correct.,1: ROM Checksum Fail." newline bitfld.long 0x0 13. "CCHK,Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set software clearing this bit is ignored and the bit will remain set until the operation is completed." "0: No operation/complete.,1: Start operation." bitfld.long 0x0 9. "DCACHE_DIS,Data Cache Disable. The system cache(s) will be completely disabled when this bit is set." "0: Is enabled.,1: Is Disabled." newline bitfld.long 0x0 7. "DCACHE_FLUSH,Data Cache Flush. The system cache(s) will be flushed when this bit is set." "0: Normal System Cache Operation,1: System Cache is flushed" bitfld.long 0x0 6. "CCACHE_FLUSH,Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4." "0: Normal Code Cache Operation,1: Code Caches and CPU instruction buffer are flushed" newline bitfld.long 0x0 4. "FLASH_PAGE_FLIP,Flips the Flash bottom and top halves. (Depending on the total flash size each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer." "0: Physical layout matches logical layout.,1: Bottom half mapped to logical top half and vice.." bitfld.long 0x0 1.--2. "SBUSARB,System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset." "0: Fixed Burst abritration.,1: Round-robin scheme.,?,?" newline bitfld.long 0x0 0. "BSTAPEN,Boundary Scan TAP enable. When enabled the JTAG port is connected to the Boundary Scan TAP. Otherwise the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number." "0: Boundary Scan TAP port disabled.,1: Boundary Scan TAP port enabled." line.long 0x4 "RSTR0,Reset." bitfld.long 0x4 31. "SYSTEM,System Reset. Setting this bit to 1 resets the CPU core and all peripherals including the watchdog timer." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 30. "PRST,Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core the watchdog timer and all GPIO pins are unaffected by this reset." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 29. "SRST,Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 28. "UART2,UART2 Reset. Setting this bit to 1 resets all UART 2 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 26. "ADC,Analog to Digital Reset." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 25. "RSV_0x19,Reserved for Future Use" "0,1" newline bitfld.long 0x4 24. "TRNG,TRNG Reset." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 23. "USB,USB Reset. Setting this bit resets both USB blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 22. "CLCD,CLCD Reset. Setting this bit to 1 resets the CLCD clock." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 21. "HBC,Hyper Bus Controller Reset. Setting this bit to 1 resets the HBC clock." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 18. "CRYPTO,Cryptographic Reset. Setting this bit to 1 resets the AES block the SHA block and the DES block." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 17. "RTC,Real Time Clock Reset." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 16. "I2C0,I2C0 Reset." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 15. "SPI2,SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 14. "SPI1,SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 13. "SPI0,SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 12. "UART1,UART1 Reset. Setting this bit to 1 resets all UART 1 blocks." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 11. "UART0,UART0 Reset. Setting this bit to 1 resets all UART 0 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 10. "TIMER5,Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 9. "TIMER4,Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 8. "TIMER3,Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 7. "TIMER2,Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 6. "TIMER1,Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 5. "TIMER0,Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 4. "GPIO2,GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 3. "GPIO1,GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 2. "GPIO0,GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states." "0: Reset Complete,1: Reset Busy" bitfld.long 0x4 1. "WDT,Watchdog Timer Reset." "0: Reset Complete,1: Reset Busy" newline bitfld.long 0x4 0. "DMA,DMA Reset." "0: Reset Complete,1: Reset Busy" line.long 0x8 "CLKCN,Clock Control." bitfld.long 0x8 29. "LIRC8K_RDY,8kHz Low Frequency Reference Clock Ready." "0: Not Ready,1: Clock Ready" bitfld.long 0x8 28. "HIRC8M_RDY,8MHz HIRC Ready." "0: Not Ready,1: HIRC8M Ready" newline bitfld.long 0x8 27. "HIRC96M_RDY,96MHz HIRC Ready." "0: Not Ready,1: HIRC96M Ready" bitfld.long 0x8 26. "HIRC_RDY,60MHz HIRC Ready." "0: Not Ready,1: HIRC Ready" newline rbitfld.long 0x8 25. "X32K_RDY,32kHz Crystal Oscillator Ready" "0: Not Ready,1: X32K Ready" bitfld.long 0x8 20. "HIRC8M_EN,8MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled." newline bitfld.long 0x8 19. "HIRC96M_EN,96MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled." bitfld.long 0x8 18. "HIRC_EN,60MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled." newline bitfld.long 0x8 17. "X32K_EN,32kHz Crystal Oscillator Enable." "0: Is Disabled.,1: Is Enabled." rbitfld.long 0x8 15. "CCD,Cryptographic clock divider" "0: The cryptographic accelerator clock is running..,1: The cryptographic accelerator clock is running.." newline rbitfld.long 0x8 13. "CKRDY,Clock Ready. This read only bit reflects whether the currently selected system clock source is running." "0: Switchover to the new clock source (as selected..,1: System clock running from CLKSEL clock source." bitfld.long 0x8 9.--11. "CLKSEL,Clock Source Select. This 3 bit field selects the source for the system clock." "0: Crypto oscillator is used for the system clock.,?,2: HFXIN is used for the system clock.,3: The nano-ring output is used for the system clock.,4: The internal 96 MHz oscillator is used for the..,5: The internal 8 MHz oscillator is used for the..,?,?" newline bitfld.long 0x8 6.--8. "PSC,Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." line.long 0xC "PM,Power Management." bitfld.long 0xC 17. "HIRC8MPD,8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP." bitfld.long 0xC 16. "HIRC96MPD,96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP." newline bitfld.long 0xC 15. "HIRCPD,HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP." bitfld.long 0xC 6. "USBWKEN,USB Wake Up Enable. This bit enables USB activity as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable." newline bitfld.long 0xC 5. "RTCWKEN,RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled the desired RTC alarm must be configured via the RTC control registers." "0: Wake Up Disable.,1: Wake Up Enable." bitfld.long 0xC 4. "GPIOWKEN,GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set." "0: Wake Up Disable.,1: Wake Up Enable." newline bitfld.long 0xC 0.--2. "MODE,Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode." "0: Active Mode.,?,?,3: Shutdown Mode.,4: Backup Mode.,?,?,?" line.long 0x10 "PLL0CN,PLL 0 Control." hexmask.long 0x10 0.--31. 1. "RFU,Reserved for Future Use" line.long 0x14 "PLL1CN,PLL 1 Control." hexmask.long 0x14 0.--31. 1. "RFU,Reserved for Future Use" line.long 0x18 "PCKDIV,Peripheral Clock Divider." bitfld.long 0x18 14.--15. "AONCD,Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider." "0: PCLK divide by 4.,1: PCLK divide by 8.,2: PCLK divide by 16.,3: PCLK divide by 32." hexmask.long.byte 0x18 10.--13. 1. "ADCFRQ,ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ)." newline bitfld.long 0x18 7. "SDHCFRQ,SDHC Clock Frequency. This bits defines the clock frequency of SDHC." "0,1" bitfld.long 0x18 3. "PCFWEN,PCF Write Enable. This bit allows the PCF Register bits to be updated by Software." "0: Writes to PCF are blocked.,1: Writes to PCF are allowed" newline bitfld.long 0x18 0.--2. "PCF,These bits determine the clock frequency for the UART I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are.." "0,1,2,3,4,5,6,7" group.long 0x24++0xB line.long 0x0 "PERCKCN0,Peripheral Clock Disable." bitfld.long 0x0 31. "SPIMD,SPI XiP Master Controller Disable." "0: enable it.,1: disable it." bitfld.long 0x0 30. "SPIXIPD,SPI XiP Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 29. "PTD,PT Clock Disable." "0: enable it.,1: disable it." bitfld.long 0x0 28. "I2C1D,I2C 1 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 25. "RSV_0X19,Reserved for Future Use" "0,1" bitfld.long 0x0 23. "ADCD,ADC Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 20. "T5D,Timer 5 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 19. "T4D,Timer 4 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 18. "T3D,Timer 3 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 17. "T2D,Timer 2 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 16. "T1D,Timer 1 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 15. "T0D,Timer 0 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 14. "CRYPTOD,Crypto Disable." "0: enable it.,1: disable it." bitfld.long 0x0 13. "I2C0D,I2C 0 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 10. "UART1D,UART 1 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 9. "UART0D,UART 0 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 8. "SPI2D,SPI 2 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 7. "SPI1D,SPI 1 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 6. "SPI0D,SPI 0 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 5. "DMAD,DMA Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 4. "CLCDD,CLCD Disable." "0: enable it.,1: disable it." bitfld.long 0x0 3. "USBD,USB Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 2. "GPIO2D,GPIO2 Disable." "0: enable it.,1: disable it." bitfld.long 0x0 1. "GPIO1D,GPIO1 Disable." "0: enable it.,1: disable it." newline bitfld.long 0x0 0. "GPIO0D,GPIO0 Disable." "0: enable it.,1: disable it." line.long 0x4 "MEMCKCN,Memory Clock Control Register." bitfld.long 0x4 29. "ROMLS,ROM Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 28. "USBLS,USB FIFO Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." newline bitfld.long 0x4 27. "CRYPTOLS,CRYPTO RAM Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 26. "SCACHELS,SysCache RAM Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." newline bitfld.long 0x4 25. "ICACHEXIPLS,ICACHE-XIP RAM Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 24. "ICACHELS,ICache RAM Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." newline bitfld.long 0x4 22. "SYSRAM6LS,System RAM 6 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 21. "SYSRAM5LS,System RAM 5 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." newline bitfld.long 0x4 20. "SYSRAM4LS,System RAM 4 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 19. "SYSRAM3LS,System RAM 3 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." newline bitfld.long 0x4 18. "SYSRAM2LS,System RAM 2 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 17. "SYSRAM1LS,System RAM 1 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." newline bitfld.long 0x4 16. "SYSRAM0LS,System RAM 0 Light Sleep Mode." "0: Memory is active.,1: Memory is in Light Sleep mode." bitfld.long 0x4 0.--2. "FWS,Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2." "0,1,2,3,4,5,6,7" line.long 0x8 "MEMZCN,Memory Zeroize Control." bitfld.long 0x8 13. "USBFIFOZ,USB FIFO Zeroizatoin." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 12. "CRYPTOZ,Crypto (MAA) Memory." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 11. "SCACHETAGZ,System Cache Tag Zeroization." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 10. "SCACHEDATAZ,System Cache Data Ram Zeroization." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 9. "ICACHEXIPZ,Instruction Cache XIP Data and Tag Ram zeroizatoin." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 8. "ICACHEZ,Instruction Cache." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 6. "SRAM6Z,System RAM Block 6." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 5. "SRAM5Z,System RAM Block 5." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 4. "SRAM4Z,System RAM Block 4." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 3. "SRAM3Z,System RAM Block 3." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 2. "SRAM2Z,System RAM Block 2." "0: No operation/complete.,1: Start operation." bitfld.long 0x8 1. "SRAM1Z,System RAM Block 1." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 0. "SRAM0Z,System RAM Block 0." "0: No operation/complete.,1: Start operation." group.long 0x34++0x1B line.long 0x0 "SCCK,Smart Card Clock Control." line.long 0x4 "MPRI0,Master Priority Control Register 0." line.long 0x8 "MPRI1,Mater Priority Control Register 1." line.long 0xC "SYSST,System Status Register." bitfld.long 0xC 5. "SCMEMF,System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface." "0: Normal Operating Condition.,1: Memory Fault." bitfld.long 0xC 1. "CODEINTERR,Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface." "0: Normal Operating Condition.,1: Code Integrity Error." newline bitfld.long 0xC 0. "ICECLOCK,ARM ICE Lock Status." "0: ICE is unlocked.,1: ICE is locked." line.long 0x10 "RSTR1,Reset 1." bitfld.long 0x10 16. "SMPHR,SMPHR Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 15. "SPIXMEM,SPIXMEM Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 14. "SPIMS0,SPIMS0 Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 13. "SPIMM2,SPIMM2 Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 12. "SPIMM1,SPIMM1 Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 11. "SPIMM0,SPIMM0 Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 10. "I2S,I2S Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 9. "SPI3,SPI3 Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 8. "WDT1,WDT1 Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 7. "OWIRE,OWIRE Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 6. "SDHC,SDHC/SDIO Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 5. "GPIO3,GPIO3 Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 4. "XSPIM,GSPI XiP Master Controller Reset." "0: Reset complete.,1: Reset in progress." bitfld.long 0x10 3. "SPIXIP,SPI XiP Master Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 2. "RSV_0X02,Reserved for Future Use" "0,1" bitfld.long 0x10 1. "PT,PT Reset." "0: Reset complete.,1: Reset in progress." newline bitfld.long 0x10 0. "I2C1,I2C1 Reset." "0: Reset complete.,1: Reset in progress." line.long 0x14 "PERCKCN1,Peripheral Clock Disable." bitfld.long 0x14 20. "SPIXIPDD,SPI-XIP Data Clock Disable" "0: Enable.,1: Disable." bitfld.long 0x14 19. "SPIMS0,SPI Medical Slave 0 Clock Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 18. "SPIMM2,SPI Medical Master 2 Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 17. "SPIMM1,SPI Medical Master 1 Clock Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 16. "SPIMM0,SPI Medical Master 0 Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 15. "I2SD,I2S(SPI_MSS) Clock Disable" "0: Enable.,1: Disable." newline bitfld.long 0x14 14. "SPI3D,SPI3 Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 13. "OWIRED,One-Wire Clock Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 12. "ICACHEXIPD,ICache XIP Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 11. "ICACHED,ICache Clock Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 10. "SDHCD,SDHC/SDIO Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 9. "SMPHRD,Semaphore Clock Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 8. "SDMAD,SDMA Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 7. "SCACHED,System Cache Clock Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 6. "GPIO3D,GPIO3 Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 5. "RSV_0X05,Reserved for Future Use" "0,1" newline bitfld.long 0x14 4. "HBCD,Hyper Bus Controller Clock Disable." "0: Enable.,1: Disable." bitfld.long 0x14 3. "FLCD,Secure Flash Controller Disable." "0: Enable.,1: Disable." newline bitfld.long 0x14 2. "TRNGD,TRNG Disable." "0: Enable.,1: Disable." bitfld.long 0x14 1. "UART2D,BTLE Disable." "0: Enable.,1: Disable." line.long 0x18 "EVTEN,Event Enable Register." bitfld.long 0x18 2. "TXEVENT,Enable TXEV pin event. When this bit is set TXEV event from the CPU is output to GPIO[25]." "0,1" bitfld.long 0x18 1. "RXEVENT,Enable RXEV pin event. When this bit is set a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1" newline bitfld.long 0x18 0. "DMAEVENT,Enable DMA event. When this bit is set a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1" rgroup.long 0x50++0x3 line.long 0x0 "REVISION,Revision Register." hexmask.long.word 0x0 0.--15. 1. "REVISION,Manufacturer Chip Revision." group.long 0x54++0x3 line.long 0x0 "SYSSIE,System Status Interrupt Enable Register." bitfld.long 0x0 5. "SCMFIE,System Cache Memory Fault Interrupt Enable." "0: disabled.,1: enabled." bitfld.long 0x0 1. "CIEIE,Code Integrity Error Interrupt Enable." "0: disabled.,1: enabled." newline bitfld.long 0x0 0. "ICEULIE,ARM ICE Unlock Interrupt Enable." "0: disabled.,1: enabled." tree.end tree "GPIO (General-Purpose I/O)" base ad:0x0 tree "GPIO0" base ad:0x40008000 group.long 0x0++0x1B line.long 0x0 "EN,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port." hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port." line.long 0x4 "EN_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x8 "EN_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "OUT_EN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port." hexmask.long 0xC 0.--31. 1. "GPIO_OUT_EN,Mask of all of the pins on the port." line.long 0x10 "OUT_EN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "OUT_EN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers." hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port." wgroup.long 0x1C++0x7 line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port." line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port." rgroup.long 0x24++0x3 line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port." hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port." group.long 0x28++0x7 line.long 0x0 "INT_MOD,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_MOD,Mask of all of the pins on the port." line.long 0x4 "INT_POL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port." hexmask.long 0x4 0.--31. 1. "GPIO_INT_POL,Mask of all of the pins on the port." group.long 0x34++0xB line.long 0x0 "INT_EN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_EN,Mask of all of the pins on the port." line.long 0x4 "INT_EN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_INT_EN_SET,Mask of all of the pins on the port." line.long 0x8 "INT_EN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "GPIO_INT_EN_CLR,Mask of all of the pins on the port." rgroup.long 0x40++0x3 line.long 0x0 "INT_STAT,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_STAT,Mask of all of the pins on the port." group.long 0x48++0xF line.long 0x0 "INT_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x4 "WAKE_EN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_WAKE_EN,Mask of all of the pins on the port." line.long 0x8 "WAKE_EN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "WAKE_EN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0x5C++0x23 line.long 0x0 "INT_DUAL_EDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_DUAL_EDGE,Mask of all of the pins on the port." line.long 0x4 "PAD_CFG1,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_PAD_CFG1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0x8 "PAD_CFG2,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x8 0.--31. 1. "GPIO_PAD_CFG2,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port." line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port." line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register." hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register." hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xA8++0x13 line.long 0x0 "IS,Input Hysteresis Enable Register" line.long 0x4 "SR,Slew Rate Select Register." line.long 0x8 "DS,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0x8 0.--31. 1. "DS,Mask of all of the pins on the port." line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x10 "PS,GPIO Pull Select Mode." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xC0++0x3 line.long 0x0 "VSSEL,GPIO Voltage Select." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." tree.end tree "GPIO1" base ad:0x40009000 group.long 0x0++0x1B line.long 0x0 "EN,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port." hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port." line.long 0x4 "EN_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x8 "EN_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "OUT_EN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port." hexmask.long 0xC 0.--31. 1. "GPIO_OUT_EN,Mask of all of the pins on the port." line.long 0x10 "OUT_EN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "OUT_EN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers." hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port." wgroup.long 0x1C++0x7 line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port." line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port." rgroup.long 0x24++0x3 line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port." hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port." group.long 0x28++0x7 line.long 0x0 "INT_MOD,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_MOD,Mask of all of the pins on the port." line.long 0x4 "INT_POL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port." hexmask.long 0x4 0.--31. 1. "GPIO_INT_POL,Mask of all of the pins on the port." group.long 0x34++0xB line.long 0x0 "INT_EN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_EN,Mask of all of the pins on the port." line.long 0x4 "INT_EN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_INT_EN_SET,Mask of all of the pins on the port." line.long 0x8 "INT_EN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "GPIO_INT_EN_CLR,Mask of all of the pins on the port." rgroup.long 0x40++0x3 line.long 0x0 "INT_STAT,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_STAT,Mask of all of the pins on the port." group.long 0x48++0xF line.long 0x0 "INT_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x4 "WAKE_EN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_WAKE_EN,Mask of all of the pins on the port." line.long 0x8 "WAKE_EN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "WAKE_EN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0x5C++0x23 line.long 0x0 "INT_DUAL_EDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_DUAL_EDGE,Mask of all of the pins on the port." line.long 0x4 "PAD_CFG1,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_PAD_CFG1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0x8 "PAD_CFG2,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x8 0.--31. 1. "GPIO_PAD_CFG2,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port." line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port." line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register." hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register." hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xA8++0x13 line.long 0x0 "IS,Input Hysteresis Enable Register" line.long 0x4 "SR,Slew Rate Select Register." line.long 0x8 "DS,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0x8 0.--31. 1. "DS,Mask of all of the pins on the port." line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x10 "PS,GPIO Pull Select Mode." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xC0++0x3 line.long 0x0 "VSSEL,GPIO Voltage Select." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." tree.end tree "GPIO2" base ad:0x4000A000 group.long 0x0++0x1B line.long 0x0 "EN,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port." hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port." line.long 0x4 "EN_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x8 "EN_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "OUT_EN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port." hexmask.long 0xC 0.--31. 1. "GPIO_OUT_EN,Mask of all of the pins on the port." line.long 0x10 "OUT_EN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "OUT_EN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers." hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port." wgroup.long 0x1C++0x7 line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port." line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port." rgroup.long 0x24++0x3 line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port." hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port." group.long 0x28++0x7 line.long 0x0 "INT_MOD,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_MOD,Mask of all of the pins on the port." line.long 0x4 "INT_POL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port." hexmask.long 0x4 0.--31. 1. "GPIO_INT_POL,Mask of all of the pins on the port." group.long 0x34++0xB line.long 0x0 "INT_EN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_EN,Mask of all of the pins on the port." line.long 0x4 "INT_EN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_INT_EN_SET,Mask of all of the pins on the port." line.long 0x8 "INT_EN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "GPIO_INT_EN_CLR,Mask of all of the pins on the port." rgroup.long 0x40++0x3 line.long 0x0 "INT_STAT,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_STAT,Mask of all of the pins on the port." group.long 0x48++0xF line.long 0x0 "INT_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x4 "WAKE_EN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_WAKE_EN,Mask of all of the pins on the port." line.long 0x8 "WAKE_EN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "WAKE_EN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0x5C++0x23 line.long 0x0 "INT_DUAL_EDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_DUAL_EDGE,Mask of all of the pins on the port." line.long 0x4 "PAD_CFG1,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_PAD_CFG1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0x8 "PAD_CFG2,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x8 0.--31. 1. "GPIO_PAD_CFG2,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port." line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port." line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register." hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register." hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xA8++0x13 line.long 0x0 "IS,Input Hysteresis Enable Register" line.long 0x4 "SR,Slew Rate Select Register." line.long 0x8 "DS,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0x8 0.--31. 1. "DS,Mask of all of the pins on the port." line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x10 "PS,GPIO Pull Select Mode." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xC0++0x3 line.long 0x0 "VSSEL,GPIO Voltage Select." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." tree.end tree "GPIO3" base ad:0x4000B000 group.long 0x0++0x1B line.long 0x0 "EN,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port." hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port." line.long 0x4 "EN_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x8 "EN_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "OUT_EN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port." hexmask.long 0xC 0.--31. 1. "GPIO_OUT_EN,Mask of all of the pins on the port." line.long 0x10 "OUT_EN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "OUT_EN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers." hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port." wgroup.long 0x1C++0x7 line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port." line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port." rgroup.long 0x24++0x3 line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port." hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port." group.long 0x28++0x7 line.long 0x0 "INT_MOD,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_MOD,Mask of all of the pins on the port." line.long 0x4 "INT_POL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port." hexmask.long 0x4 0.--31. 1. "GPIO_INT_POL,Mask of all of the pins on the port." group.long 0x34++0xB line.long 0x0 "INT_EN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_EN,Mask of all of the pins on the port." line.long 0x4 "INT_EN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register." hexmask.long 0x4 0.--31. 1. "GPIO_INT_EN_SET,Mask of all of the pins on the port." line.long 0x8 "INT_EN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "GPIO_INT_EN_CLR,Mask of all of the pins on the port." rgroup.long 0x40++0x3 line.long 0x0 "INT_STAT,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_STAT,Mask of all of the pins on the port." group.long 0x48++0xF line.long 0x0 "INT_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x4 "WAKE_EN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_WAKE_EN,Mask of all of the pins on the port." line.long 0x8 "WAKE_EN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register." hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0xC "WAKE_EN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0x5C++0x23 line.long 0x0 "INT_DUAL_EDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port." hexmask.long 0x0 0.--31. 1. "GPIO_INT_DUAL_EDGE,Mask of all of the pins on the port." line.long 0x4 "PAD_CFG1,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x4 0.--31. 1. "GPIO_PAD_CFG1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0x8 "PAD_CFG2,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port." hexmask.long 0x8 0.--31. 1. "GPIO_PAD_CFG2,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode." line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port." line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register." hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port." hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port." line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register." hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register." hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xA8++0x13 line.long 0x0 "IS,Input Hysteresis Enable Register" line.long 0x4 "SR,Slew Rate Select Register." line.long 0x8 "DS,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0x8 0.--31. 1. "DS,Mask of all of the pins on the port." line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode." hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port." line.long 0x10 "PS,GPIO Pull Select Mode." hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port." group.long 0xC0++0x3 line.long 0x0 "VSSEL,GPIO Voltage Select." hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port." tree.end tree.end tree "HPB (HyperBus/Xccela External Memory Interface)" base ad:0x40039000 rgroup.long 0x0++0x3 line.long 0x0 "STATUS,Controller Status Register." bitfld.long 0x0 26. "WRSTOERR,RSTO Error in Write Transaction." "0,1" bitfld.long 0x0 24. "WDECERR,Decode Error in Write Transaction." "0,1" bitfld.long 0x0 16. "WACT,Write Transaction Active." "0,1" bitfld.long 0x0 11. "RDSSTALL,RDS Stall Error in Read Transaction." "0,1" bitfld.long 0x0 10. "RRSTOERR,RSTO Error in Read Transaction." "0,1" bitfld.long 0x0 8. "RDECERR,Decode Error in Read Transaction." "0,1" bitfld.long 0x0 0. "RACT,Read Transaction Active." "0,1" group.long 0x4++0x3 line.long 0x0 "INTEN,Interrupt Enable Control Register." bitfld.long 0x0 1. "ERRINTE,Error Interrupt Enable." "0,1" rgroup.long 0x8++0x3 line.long 0x0 "INTFL,Interrupt Status Register." bitfld.long 0x0 1. "ERRINTE,Error Interrupt Status." "0,1" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "MBR[$1],Memory Base Address Registers." hexmask.long.byte 0x0 24.--31. 1. "ADDR,Base address for memory space 0." repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "MCR[$1],Memory Configuration Registers." bitfld.long 0x0 31. "MAXEN,Maximum length Enable." "0,1" hexmask.long.word 0x0 18.--26. 1. "MAXLEN,Maximum Length." bitfld.long 0x0 7. "HSE,Halt Sleep Exit." "0,1" bitfld.long 0x0 6. "FRL,Fixed Read latency enable." "0,1" bitfld.long 0x0 5. "CRT,Configuration Register Target." "0,1" bitfld.long 0x0 3.--4. "DEVTYPE,Device Type." "0: Hyper flash device.,1: Hyper PSRAM device.,2: Hyper RAM device.,?" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "MTR[$1],Memory Timing Registers." hexmask.long.byte 0x0 28.--31. 1. "RCSHI,Read Chip Select High Between Operations." hexmask.long.byte 0x0 24.--27. 1. "WCSHI,Write Chip Select High Between Operations." hexmask.long.byte 0x0 20.--23. 1. "RCSS,Read Chip Select Setup To Next CK Rising Edge." hexmask.long.byte 0x0 16.--19. 1. "WCSS,Write Chip Select Setup To Next CK Rising Edge." hexmask.long.byte 0x0 12.--15. 1. "RCSH,Read Chip Select Hold After CK falling Edge." hexmask.long.byte 0x0 8.--11. 1. "WCSH,Write Chip Select Hold After CK falling Edge." hexmask.long.byte 0x0 0.--3. 1. "LTCY,Latency Cycle for HyperRAM mode." repeat.end tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0x0 tree "I2C0" base ad:0x4001D000 group.long 0x0++0x17 line.long 0x0 "CTRL,Control Register0." bitfld.long 0x0 15. "HS_MODE,Hs-mode Enable." "0: Hs-mode disabled.,1: Hs-mode enabled." newline bitfld.long 0x0 13. "SCL_PP_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.." newline bitfld.long 0x0 12. "SCL_CLK_STRECH_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled." newline rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read." newline bitfld.long 0x0 10. "SW_OUT_EN,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled." newline rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1" newline rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1" newline bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA." newline bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL." newline bitfld.long 0x0 4. "RX_MODE_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)." newline bitfld.long 0x0 3. "RX_MODE,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode." newline bitfld.long 0x0 2. "GEN_CALL_ADDR,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address." newline bitfld.long 0x0 1. "MST,Master Mode Enable." "0: Slave Mode.,1: Master Mode." newline bitfld.long 0x0 0. "I2C_EN,I2C Enable." "0: Disable I2C.,1: enable I2C." line.long 0x4 "STATUS,Status Register." hexmask.long.byte 0x4 8.--11. 1. "STATUS,Controller Status." newline rbitfld.long 0x4 5. "CLK_MODE,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.." newline bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty." newline bitfld.long 0x4 3. "TX_EMPTY,TX Empty." "0: Not Empty.,1: Empty." newline rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full." newline rbitfld.long 0x4 1. "RX_EMPTY,RX empty." "0: Not Empty.,1: Empty." newline rbitfld.long 0x4 0. "BUS,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy." line.long 0x8 "INT_FL0,Interrupt Status Register." bitfld.long 0x8 15. "TX_LOCK_OUT,Transmit Lock Out Interrupt." "0,1" newline bitfld.long 0x8 14. "STOP_ER,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 13. "START_ER,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 12. "DO_NOT_RESP_ER,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 11. "DATA_ER,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 10. "ADDR_NACK_ER,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 9. "TO_ER,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 8. "ARB_ER,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.." newline bitfld.long 0x8 5. "TX_THRESH,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.." newline bitfld.long 0x8 4. "RX_THRESH,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.." newline bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 2. "GEN_CALL_ADDR,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 1. "RX_MODE,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." line.long 0xC "INT_EN0,Interrupt Enable Register." bitfld.long 0xC 15. "TX_LOCK_OUT,TX FIFO Locked Out Interrupt." "0: Interrupt disabled.,1: Interrupt enabled when TXLOIE = 1." newline bitfld.long 0xC 14. "STOP_ER,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 13. "START_ER,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 12. "DO_NOT_RESP_ER,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 11. "DATA_ER,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 10. "ADDR_ER,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 9. "TO_ER,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 8. "ARB_ER,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1." newline bitfld.long 0xC 5. "TX_THRESH,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 4. "RX_THRESH,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1." newline bitfld.long 0xC 2. "GEN_CTRL_ADDR,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1." newline bitfld.long 0xC 1. "RX_MODE,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1." newline bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1." line.long 0x10 "INT_FL1,Interrupt Status Register 1." bitfld.long 0x10 1. "TX_UNDERFLOW,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x10 0. "RX_OVERFLOW,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending." line.long 0x14 "INT_EN1,Interrupt Staus Register 1." bitfld.long 0x14 1. "TX_UNDERFLOW,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x14 0. "RX_OVERFLOW,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "FIFO_LEN,FIFO Configuration Register." hexmask.long.byte 0x0 8.--15. 1. "TX_LEN,Transmit FIFO Length." newline hexmask.long.byte 0x0 0.--7. 1. "RX_LEN,Receive FIFO Length." group.long 0x1C++0x2F line.long 0x0 "RX_CTRL0,Receive Control Register 0." hexmask.long.byte 0x0 8.--11. 1. "RX_THRESH,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold." newline bitfld.long 0x0 7. "RX_FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO." newline bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.." line.long 0x4 "RX_CTRL1,Receive Control Register 1." hexmask.long.byte 0x4 8.--11. 1. "RX_FIFO,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0." newline hexmask.long.byte 0x4 0.--7. 1. "RX_CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction." line.long 0x8 "TX_CTRL0,Transmit Control Register 0." hexmask.long.byte 0x8 8.--11. 1. "TX_THRESH,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold." newline bitfld.long 0x8 7. "TX_FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO." newline bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled." newline bitfld.long 0x8 0. "TX_PRELOAD,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1" line.long 0xC "TX_CTRL1,Transmit Control Register 1." hexmask.long.byte 0xC 8.--11. 1. "TX_FIFO,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO." newline bitfld.long 0xC 1. "TX_LAST,Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware)." "0: Hold SCL low on TX_FIFO empty.,1: End transaction on TX_FIFO empty." newline bitfld.long 0xC 0. "TX_READY,Transmit FIFO Preload Ready." "0,1" line.long 0x10 "FIFO,Data Register." hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location." line.long 0x14 "MASTER_CTRL,Master Control Register." bitfld.long 0x14 11. "SCL_SPEED_UP,Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves." "0: Master monitors SCL state.,1: SCL state monitoring disabled." newline bitfld.long 0x14 8.--10. "MASTER_CODE,Master Code. These bits set the Master Code used in Hs-mode operation." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 7. "SL_EX_ADDR,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address." newline bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1" newline bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1" newline bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1" line.long 0x18 "CLK_LO,Clock Low Register." hexmask.long.word 0x18 0.--8. 1. "CLK_LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted." line.long 0x1C "CLK_HI,Clock high Register." hexmask.long.word 0x1C 0.--8. 1. "CKH,Clock High. In master mode these bits define the SCL high period." line.long 0x20 "HS_CLK,HS-Mode Clock Control Register" hexmask.long.byte 0x20 8.--15. 1. "HS_CLK_HI,Slave Address." newline hexmask.long.byte 0x20 0.--7. 1. "HS_CLK_LO,Slave Address." line.long 0x24 "TIMEOUT,Timeout Register" hexmask.long.word 0x24 0.--15. 1. "TO,Timeout" line.long 0x28 "SLAVE_ADDR,Slave Address Register." bitfld.long 0x28 15. "EX_ADDR,Extended Address Select." "0: 7-bit address.,1: 10-bit address." newline hexmask.long.byte 0x28 11.--14. 1. "SLAVE_ADDR_IDX,Slave Address Index." newline bitfld.long 0x28 10. "SLAVE_ADDR_DIS,Slave Address DIS." "0,1" newline hexmask.long.word 0x28 0.--9. 1. "SLAVE_ADDR,Slave Address." line.long 0x2C "DMA,DMA Register." bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable." newline bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable." tree.end tree "I2C1" base ad:0x4001E000 group.long 0x0++0x17 line.long 0x0 "CTRL,Control Register0." bitfld.long 0x0 15. "HS_MODE,Hs-mode Enable." "0: Hs-mode disabled.,1: Hs-mode enabled." newline bitfld.long 0x0 13. "SCL_PP_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.." newline bitfld.long 0x0 12. "SCL_CLK_STRECH_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled." newline rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read." newline bitfld.long 0x0 10. "SW_OUT_EN,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled." newline rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1" newline rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1" newline bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA." newline bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL." newline bitfld.long 0x0 4. "RX_MODE_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)." newline bitfld.long 0x0 3. "RX_MODE,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode." newline bitfld.long 0x0 2. "GEN_CALL_ADDR,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address." newline bitfld.long 0x0 1. "MST,Master Mode Enable." "0: Slave Mode.,1: Master Mode." newline bitfld.long 0x0 0. "I2C_EN,I2C Enable." "0: Disable I2C.,1: enable I2C." line.long 0x4 "STATUS,Status Register." hexmask.long.byte 0x4 8.--11. 1. "STATUS,Controller Status." newline rbitfld.long 0x4 5. "CLK_MODE,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.." newline bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty." newline bitfld.long 0x4 3. "TX_EMPTY,TX Empty." "0: Not Empty.,1: Empty." newline rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full." newline rbitfld.long 0x4 1. "RX_EMPTY,RX empty." "0: Not Empty.,1: Empty." newline rbitfld.long 0x4 0. "BUS,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy." line.long 0x8 "INT_FL0,Interrupt Status Register." bitfld.long 0x8 15. "TX_LOCK_OUT,Transmit Lock Out Interrupt." "0,1" newline bitfld.long 0x8 14. "STOP_ER,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 13. "START_ER,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 12. "DO_NOT_RESP_ER,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 11. "DATA_ER,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 10. "ADDR_NACK_ER,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 9. "TO_ER,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 8. "ARB_ER,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.." newline bitfld.long 0x8 5. "TX_THRESH,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.." newline bitfld.long 0x8 4. "RX_THRESH,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.." newline bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 2. "GEN_CALL_ADDR,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 1. "RX_MODE,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending." line.long 0xC "INT_EN0,Interrupt Enable Register." bitfld.long 0xC 15. "TX_LOCK_OUT,TX FIFO Locked Out Interrupt." "0: Interrupt disabled.,1: Interrupt enabled when TXLOIE = 1." newline bitfld.long 0xC 14. "STOP_ER,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 13. "START_ER,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 12. "DO_NOT_RESP_ER,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 11. "DATA_ER,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 10. "ADDR_ER,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 9. "TO_ER,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 8. "ARB_ER,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1." newline bitfld.long 0xC 5. "TX_THRESH,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 4. "RX_THRESH,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled." newline bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1." newline bitfld.long 0xC 2. "GEN_CTRL_ADDR,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1." newline bitfld.long 0xC 1. "RX_MODE,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1." newline bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1." line.long 0x10 "INT_FL1,Interrupt Status Register 1." bitfld.long 0x10 1. "TX_UNDERFLOW,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x10 0. "RX_OVERFLOW,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending." line.long 0x14 "INT_EN1,Interrupt Staus Register 1." bitfld.long 0x14 1. "TX_UNDERFLOW,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending." newline bitfld.long 0x14 0. "RX_OVERFLOW,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending." rgroup.long 0x18++0x3 line.long 0x0 "FIFO_LEN,FIFO Configuration Register." hexmask.long.byte 0x0 8.--15. 1. "TX_LEN,Transmit FIFO Length." newline hexmask.long.byte 0x0 0.--7. 1. "RX_LEN,Receive FIFO Length." group.long 0x1C++0x2F line.long 0x0 "RX_CTRL0,Receive Control Register 0." hexmask.long.byte 0x0 8.--11. 1. "RX_THRESH,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold." newline bitfld.long 0x0 7. "RX_FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO." newline bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.." line.long 0x4 "RX_CTRL1,Receive Control Register 1." hexmask.long.byte 0x4 8.--11. 1. "RX_FIFO,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0." newline hexmask.long.byte 0x4 0.--7. 1. "RX_CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction." line.long 0x8 "TX_CTRL0,Transmit Control Register 0." hexmask.long.byte 0x8 8.--11. 1. "TX_THRESH,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold." newline bitfld.long 0x8 7. "TX_FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO." newline bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled." newline bitfld.long 0x8 0. "TX_PRELOAD,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1" line.long 0xC "TX_CTRL1,Transmit Control Register 1." hexmask.long.byte 0xC 8.--11. 1. "TX_FIFO,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO." newline bitfld.long 0xC 1. "TX_LAST,Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware)." "0: Hold SCL low on TX_FIFO empty.,1: End transaction on TX_FIFO empty." newline bitfld.long 0xC 0. "TX_READY,Transmit FIFO Preload Ready." "0,1" line.long 0x10 "FIFO,Data Register." hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location." line.long 0x14 "MASTER_CTRL,Master Control Register." bitfld.long 0x14 11. "SCL_SPEED_UP,Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves." "0: Master monitors SCL state.,1: SCL state monitoring disabled." newline bitfld.long 0x14 8.--10. "MASTER_CODE,Master Code. These bits set the Master Code used in Hs-mode operation." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 7. "SL_EX_ADDR,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address." newline bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1" newline bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1" newline bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1" line.long 0x18 "CLK_LO,Clock Low Register." hexmask.long.word 0x18 0.--8. 1. "CLK_LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted." line.long 0x1C "CLK_HI,Clock high Register." hexmask.long.word 0x1C 0.--8. 1. "CKH,Clock High. In master mode these bits define the SCL high period." line.long 0x20 "HS_CLK,HS-Mode Clock Control Register" hexmask.long.byte 0x20 8.--15. 1. "HS_CLK_HI,Slave Address." newline hexmask.long.byte 0x20 0.--7. 1. "HS_CLK_LO,Slave Address." line.long 0x24 "TIMEOUT,Timeout Register" hexmask.long.word 0x24 0.--15. 1. "TO,Timeout" line.long 0x28 "SLAVE_ADDR,Slave Address Register." bitfld.long 0x28 15. "EX_ADDR,Extended Address Select." "0: 7-bit address.,1: 10-bit address." newline hexmask.long.byte 0x28 11.--14. 1. "SLAVE_ADDR_IDX,Slave Address Index." newline bitfld.long 0x28 10. "SLAVE_ADDR_DIS,Slave Address DIS." "0,1" newline hexmask.long.word 0x28 0.--9. 1. "SLAVE_ADDR,Slave Address." line.long 0x2C "DMA,DMA Register." bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable." newline bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable." tree.end tree.end tree "ICC (Instruction Cache Controller)" base ad:0x0 base ad:0x4002A000 rgroup.long 0x0++0x7 line.long 0x0 "CACHE_ID,Cache ID Register." hexmask.long.byte 0x0 10.--15. 1. "CCHID,Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter." hexmask.long.byte 0x0 6.--9. 1. "PARTNUM,Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter." hexmask.long.byte 0x0 0.--5. 1. "RELNUM,Release Number. Identifies the RTL release version." line.long 0x4 "MEMCFG,Memory Configuration Register." hexmask.long.word 0x4 16.--31. 1. "MEMSZ,Main Memory Size. Indicates the total size in units of 128 Kbytes of code memory accessible to the cache controller." hexmask.long.word 0x4 0.--15. 1. "CCHSZ,Cache Size. Indicates total size in Kbytes of cache." group.long 0x100++0x3 line.long 0x0 "CACHE_CTRL,Cache Control and Status Register." rbitfld.long 0x0 16. "CACHE_RDY,Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0 the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line.." "0: Not Ready.,1: Ready." bitfld.long 0x0 0. "CACHE_EN,Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated." "0: Cache Bypassed. Instruction data is stored in..,1: Cache Enabled." group.long 0x700++0x3 line.long 0x0 "INVALIDATE,Invalidate All Registers." base ad:0x4002F000 rgroup.long 0x0++0x7 line.long 0x0 "CACHE_ID,Cache ID Register." hexmask.long.byte 0x0 10.--15. 1. "CCHID,Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter." hexmask.long.byte 0x0 6.--9. 1. "PARTNUM,Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter." hexmask.long.byte 0x0 0.--5. 1. "RELNUM,Release Number. Identifies the RTL release version." line.long 0x4 "MEMCFG,Memory Configuration Register." hexmask.long.word 0x4 16.--31. 1. "MEMSZ,Main Memory Size. Indicates the total size in units of 128 Kbytes of code memory accessible to the cache controller." hexmask.long.word 0x4 0.--15. 1. "CCHSZ,Cache Size. Indicates total size in Kbytes of cache." group.long 0x100++0x3 line.long 0x0 "CACHE_CTRL,Cache Control and Status Register." rbitfld.long 0x0 16. "CACHE_RDY,Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0 the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line.." "0: Not Ready.,1: Ready." bitfld.long 0x0 0. "CACHE_EN,Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated." "0: Cache Bypassed. Instruction data is stored in..,1: Cache Enabled." group.long 0x700++0x3 line.long 0x0 "INVALIDATE,Invalidate All Registers." tree.end tree "NBBFC (Non Battery-Backed Function Control)" base ad:0x40000800 group.long 0x0++0xF line.long 0x0 "REG0,Register 0." bitfld.long 0x0 23. "I2C1DGEN1,I2C1 SCL Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled." bitfld.long 0x0 22. "I2C1DGEN0,I2C1 SDA Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled." bitfld.long 0x0 21. "I2C0DGEN1,I2C0 SCL Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled." newline bitfld.long 0x0 20. "I2C0DGEN0,I2C0 SDA Pad Deglitcher enable." "0: Deglitcher disabled.,1: Deglitcher enabled." bitfld.long 0x0 16. "USBRCKSEL,USB External Core Clock Select." "0: Generated clock from system clock.,1: Digital clock from a GPIO." line.long 0x4 "REG1,Register 1." hexmask.long.word 0x4 8.--19. 1. "MU,MU value." bitfld.long 0x4 4. "ATOMIC,Atomic mode." "0: Not Running.,1: Running." bitfld.long 0x4 3. "GAININV,Invert Gain." "0: Not Running.,1: Running." newline bitfld.long 0x4 2. "LDTRM,Load Trim." "0,1" bitfld.long 0x4 1. "ACRUN,Autocalibration Run." "0: Not Running.,1: Running." bitfld.long 0x4 0. "ACEN,Auto-calibration Enable." "0: Disabled.,1: Enabled." line.long 0x8 "REG2,Register 2." hexmask.long.word 0x8 20.--28. 1. "MAXTRM,Maximum Trim Setting." hexmask.long.word 0x8 10.--18. 1. "MINTRM,Minimum Trim Setting." hexmask.long.word 0x8 0.--8. 1. "INITTRM,Initial Trim Setting." line.long 0xC "REG3,Register 3." hexmask.long.byte 0xC 0.--7. 1. "DONECNT,Auto-callibration Done Counter Setting." tree.end tree "OTP (One Time Programmable Memory Controller)" base ad:0x40041000 group.long 0x0++0x7 line.long 0x0 "OCNTL,OTP Control Register." bitfld.long 0x0 9. "PROG_OP,Setting this bit to a 1 initiates a write of the OTP location specified in the PA field." "0: No Operation.,1: Initiate Write Operation." bitfld.long 0x0 8. "RD_OP,Setting this bit to a 1 initiates a read of the OTP location specified in the PA field." "0: No Operation.,1: Initiate Read Operation." hexmask.long.byte 0x0 0.--6. 1. "PA,This value is the address of the OTP 32-bit value." line.long 0x4 "CKDIV,Clock Divider Register." bitfld.long 0x4 0.--1. "CKDIV,The input clock(APB) is divided by this value." "0: Divide by 2.,1: Divide by 4.,2: Divide by 8.,3: Divide by 16." rgroup.long 0x8++0x7 line.long 0x0 "OTPRDATA,Read Data Register." hexmask.long 0x0 0.--31. 1. "RDATA,OTP Data Output from read operation." line.long 0x4 "STAT,OTP Status Register." bitfld.long 0x4 1. "FAIL,Description not available." "0: No failure.,1: Failure occurs." rbitfld.long 0x4 0. "BUSY,This flag indicates whether the OTP controller is currently performing a read or write operation." "0: OTP controller ready for new operation.,1: OTP controller busy either programming or reading." wgroup.long 0x30++0x3 line.long 0x0 "ODATA,Write Data Register." hexmask.long 0x0 0.--31. 1. "OTPDATA,OTP write data." group.long 0x40++0x3 line.long 0x0 "ACNTL,Access Control Register." hexmask.long 0x0 0.--31. 1. "ADATA,System Info Block Access Data." tree.end tree "OWM (1-Wire Master Interface)" base ad:0x4003D000 group.long 0x0++0x17 line.long 0x0 "CFG,1-Wire Master Configuration." bitfld.long 0x0 7. "int_pullup_enable,Enable intenral pullup." "0,1" bitfld.long 0x0 6. "overdrive,Enables overdrive speed for 1-Wire operations." "0,1" bitfld.long 0x0 5. "single_bit_mode,Enable Single Bit TX/RX Mode." "0,1" bitfld.long 0x0 4. "ext_pullup_enable,Enable External Pullup." "0,1" bitfld.long 0x0 3. "ext_pullup_mode,Provide an extra output control to control an external pullup." "0,1" bitfld.long 0x0 2. "bit_bang_en,Bit Bang Enable." "0,1" newline bitfld.long 0x0 1. "force_pres_det,Force Line During Presence Detect." "0,1" bitfld.long 0x0 0. "long_line_mode,Long Line Mode." "0,1" line.long 0x4 "CLK_DIV_1US,1-Wire Master Clock Divisor." hexmask.long.byte 0x4 0.--7. 1. "divisor,Clock Divisor for 1Mhz." line.long 0x8 "CTRL_STAT,1-Wire Master Control/Status." rbitfld.long 0x8 7. "presence_detect,Presence Pulse Detected." "0,1" rbitfld.long 0x8 3. "ow_input,OW Input State." "0,1" bitfld.long 0x8 2. "bit_bang_oe,Bit Bang Output Enable." "0,1" bitfld.long 0x8 1. "sra_mode,SRA Mode." "0,1" bitfld.long 0x8 0. "start_ow_reset,Start OW Reset." "0,1" line.long 0xC "DATA,1-Wire Master Data Buffer." hexmask.long.byte 0xC 0.--7. 1. "tx_rx,TX/RX Buffer." line.long 0x10 "INTFL,1-Wire Master Interrupt Flags." bitfld.long 0x10 4. "line_low,OW Line Low Detected Interrupt Flag." "0,1" bitfld.long 0x10 3. "line_short,OW Line Short Detected Interrupt Flag." "0,1" bitfld.long 0x10 2. "rx_data_ready,RX Data Ready Interrupt Flag" "0,1" bitfld.long 0x10 1. "tx_data_empty,TX Data Empty Interrupt Flag." "0,1" bitfld.long 0x10 0. "ow_reset_done,OW Reset Sequence Completed." "0,1" line.long 0x14 "INTEN,1-Wire Master Interrupt Enables." eventfld.long 0x14 4. "line_low,OW Line Low Detected Interrupt Enable." "0,1" eventfld.long 0x14 3. "line_short,OW Line Short Detected Interrupt Enable." "0,1" eventfld.long 0x14 2. "rx_data_ready,Rx Data Ready Interrupt Enable." "0,1" eventfld.long 0x14 1. "tx_data_empty,Tx Data Empty Interrupt Enable." "0,1" eventfld.long 0x14 0. "ow_reset_done,OW Reset Sequence Completed." "0,1" tree.end tree "PT (Pulse Train Engine)" base ad:0x0 tree "PT" base ad:0x4003C020 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT1" base ad:0x4003C040 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT2" base ad:0x4003C060 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT3" base ad:0x4003C080 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT4" base ad:0x4003C0A0 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT5" base ad:0x4003C0C0 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT6" base ad:0x4003C0E0 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT7" base ad:0x4003C100 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT8" base ad:0x4003C120 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT9" base ad:0x4003C140 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT10" base ad:0x4003C160 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT11" base ad:0x4003C180 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT12" base ad:0x4003C1A0 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT13" base ad:0x4003C1C0 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT14" base ad:0x4003C1E0 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PT15" base ad:0x4003C200 group.long 0x0++0xF line.long 0x0 "RATE_LENGTH,Pulse Train Configuration" hexmask.long.byte 0x0 27.--31. 1. "mode,Pulse Train Output Mode/Train Length" hexmask.long 0x0 0.--26. 1. "rate_control,Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train." line.long 0x4 "TRAIN,Write the repeating bit pattern that is shifted out. LSB first. when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length." line.long 0x8 "LOOP,Pulse Train Loop Count" hexmask.long.word 0x8 16.--27. 1. "delay,Delay between loops of the Pulse Train in PT Peripheral Clock cycles" hexmask.long.word 0x8 0.--15. 1. "count,Number of loops for this pulse train to repeat." line.long 0xC "RESTART,Pulse Train Auto-Restart Configuration." bitfld.long 0xC 15. "on_pt_y_loop_exit,Enable Auto-Restart on PT Y Loop Exit" "0,1" hexmask.long.byte 0xC 8.--12. 1. "pt_y_select,Auto-Restart PT Y Select" bitfld.long 0xC 7. "on_pt_x_loop_exit,Enable Auto-Restart on PT X Loop Exit" "0,1" hexmask.long.byte 0xC 0.--4. 1. "pt_x_select,Auto-Restart PT X Select" tree.end tree "PTG" base ad:0x4003C000 group.long 0x0++0xF line.long 0x0 "ENABLE,Global Enable/Disable Controls for All Pulse Trains" bitfld.long 0x0 15. "pt15,Enable/Disable control for PT15" "0,1" bitfld.long 0x0 14. "pt14,Enable/Disable control for PT14" "0,1" bitfld.long 0x0 13. "pt13,Enable/Disable control for PT13" "0,1" bitfld.long 0x0 12. "pt12,Enable/Disable control for PT12" "0,1" bitfld.long 0x0 11. "pt11,Enable/Disable control for PT11" "0,1" bitfld.long 0x0 10. "pt10,Enable/Disable control for PT10" "0,1" bitfld.long 0x0 9. "pt9,Enable/Disable control for PT9" "0,1" bitfld.long 0x0 8. "pt8,Enable/Disable control for PT8" "0,1" bitfld.long 0x0 7. "pt7,Enable/Disable control for PT7" "0,1" bitfld.long 0x0 6. "pt6,Enable/Disable control for PT6" "0,1" bitfld.long 0x0 5. "pt5,Enable/Disable control for PT5" "0,1" bitfld.long 0x0 4. "pt4,Enable/Disable control for PT4" "0,1" bitfld.long 0x0 3. "pt3,Enable/Disable control for PT3" "0,1" bitfld.long 0x0 2. "pt2,Enable/Disable control for PT2" "0,1" bitfld.long 0x0 1. "pt1,Enable/Disable control for PT1" "0,1" newline bitfld.long 0x0 0. "pt0,Enable/Disable control for PT0" "0,1" line.long 0x4 "RESYNC,Global Resync (All Pulse Trains) Control" bitfld.long 0x4 15. "pt15,Resync control for PT15" "0,1" bitfld.long 0x4 14. "pt14,Resync control for PT14" "0,1" bitfld.long 0x4 13. "pt13,Resync control for PT13" "0,1" bitfld.long 0x4 12. "pt12,Resync control for PT12" "0,1" bitfld.long 0x4 11. "pt11,Resync control for PT11" "0,1" bitfld.long 0x4 10. "pt10,Resync control for PT10" "0,1" bitfld.long 0x4 9. "pt9,Resync control for PT9" "0,1" bitfld.long 0x4 8. "pt8,Resync control for PT8" "0,1" bitfld.long 0x4 7. "pt7,Resync control for PT7" "0,1" bitfld.long 0x4 6. "pt6,Resync control for PT6" "0,1" bitfld.long 0x4 5. "pt5,Resync control for PT5" "0,1" bitfld.long 0x4 4. "pt4,Resync control for PT4" "0,1" bitfld.long 0x4 3. "pt3,Resync control for PT3" "0,1" bitfld.long 0x4 2. "pt2,Resync control for PT2" "0,1" bitfld.long 0x4 1. "pt1,Resync control for PT1" "0,1" newline bitfld.long 0x4 0. "pt0,Resync control for PT0" "0,1" line.long 0x8 "INTFL,Pulse Train Interrupt Flags" bitfld.long 0x8 15. "pt15,Pulse Train 15 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 14. "pt14,Pulse Train 14 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 13. "pt13,Pulse Train 13 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 12. "pt12,Pulse Train 12 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 11. "pt11,Pulse Train 11 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 10. "pt10,Pulse Train 10 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 9. "pt9,Pulse Train 9 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 8. "pt8,Pulse Train 8 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 7. "pt7,Pulse Train 7 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 6. "pt6,Pulse Train 6 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 5. "pt5,Pulse Train 5 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 4. "pt4,Pulse Train 4 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 3. "pt3,Pulse Train 3 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 2. "pt2,Pulse Train 2 Stopped Interrupt Flag" "0,1" bitfld.long 0x8 1. "pt1,Pulse Train 1 Stopped Interrupt Flag" "0,1" newline bitfld.long 0x8 0. "pt0,Pulse Train 0 Stopped Interrupt Flag" "0,1" line.long 0xC "INTEN,Pulse Train Interrupt Enable/Disable" bitfld.long 0xC 15. "pt15,Pulse Train 15 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 14. "pt14,Pulse Train 14 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 13. "pt13,Pulse Train 13 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 12. "pt12,Pulse Train 12 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 11. "pt11,Pulse Train 11 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 10. "pt10,Pulse Train 10 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 9. "pt9,Pulse Train 9 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 8. "pt8,Pulse Train 8 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 7. "pt7,Pulse Train 7 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 6. "pt6,Pulse Train 6 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 5. "pt5,Pulse Train 5 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 4. "pt4,Pulse Train 4 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 3. "pt3,Pulse Train 3 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 2. "pt2,Pulse Train 2 Stopped Interrupt Enable/Disable" "0,1" bitfld.long 0xC 1. "pt1,Pulse Train 1 Stopped Interrupt Enable/Disable" "0,1" newline bitfld.long 0xC 0. "pt0,Pulse Train 0 Stopped Interrupt Enable/Disable" "0,1" wgroup.long 0x10++0x7 line.long 0x0 "SAFE_EN,Pulse Train Global Safe Enable." bitfld.long 0x0 15. "PT15" "0,1" bitfld.long 0x0 14. "PT14" "0,1" bitfld.long 0x0 13. "PT13" "0,1" bitfld.long 0x0 12. "PT12" "0,1" bitfld.long 0x0 11. "PT11" "0,1" bitfld.long 0x0 10. "PT10" "0,1" bitfld.long 0x0 9. "PT9" "0,1" bitfld.long 0x0 8. "PT8" "0,1" bitfld.long 0x0 7. "PT7" "0,1" bitfld.long 0x0 6. "PT6" "0,1" bitfld.long 0x0 5. "PT5" "0,1" bitfld.long 0x0 4. "PT4" "0,1" bitfld.long 0x0 3. "PT3" "0,1" bitfld.long 0x0 2. "PT2" "0,1" bitfld.long 0x0 1. "PT1" "0,1" newline bitfld.long 0x0 0. "PT0" "0,1" line.long 0x4 "SAFE_DIS,Pulse Train Global Safe Disable." bitfld.long 0x4 15. "PT15" "0,1" bitfld.long 0x4 14. "PT14" "0,1" bitfld.long 0x4 13. "PT13" "0,1" bitfld.long 0x4 12. "PT12" "0,1" bitfld.long 0x4 11. "PT11" "0,1" bitfld.long 0x4 10. "PT10" "0,1" bitfld.long 0x4 9. "PT9" "0,1" bitfld.long 0x4 8. "PT8" "0,1" bitfld.long 0x4 7. "PT7" "0,1" bitfld.long 0x4 6. "PT6" "0,1" bitfld.long 0x4 5. "PT5" "0,1" bitfld.long 0x4 4. "PT4" "0,1" bitfld.long 0x4 3. "PT3" "0,1" bitfld.long 0x4 2. "PT2" "0,1" bitfld.long 0x4 1. "PT1" "0,1" newline bitfld.long 0x4 0. "PT0" "0,1" tree.end tree.end tree "PWRSEQ (Power Sequencer)" base ad:0x40006800 group.long 0x0++0x23 line.long 0x0 "LPCN,Low Power Control Register." bitfld.long 0x0 27. "VDDBMD,VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods." "0: Disabled.,1: Enabled." bitfld.long 0x0 26. "PORVDDIOHMD,VDDIOH Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIOH supply in all operating mods." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 25. "PORVDDIOMD,VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods." "0: Disabled.,1: Enabled." bitfld.long 0x0 24. "VDDIOHMD,VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes." "0: Enable if Bandgap is ON(default),1: Disabled." newline bitfld.long 0x0 23. "VDDIOMD,VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes." "0: Enable if Bandgap is ON(default),1: Disabled." bitfld.long 0x0 22. "VDDAMD,VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes." "0: Enable if Bandgap is ON(default),1: Disabled." newline bitfld.long 0x0 21. "VRTCMD,VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes." "0: Enable if Bandgap is ON(default),1: Disabled." bitfld.long 0x0 20. "VDDCMD,VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes." "0: Enable if Bandgap is ON(default),1: Disabled." newline bitfld.long 0x0 12. "PORVDDCMD,VDDC(VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 11. "BGOFF,Bandgap OFF. This controls the System Bandgap in DeepSleep mode." "0: Bandgap is always ON.,1: Bandgap is OFF in DeepSleep mode(default)." newline bitfld.long 0x0 10. "FWKM,Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical)." "0: Disabled.,1: Enabled." bitfld.long 0x0 9. "BCKGRND,Background Mode ENable. This bit allows low-power background mode operations while the CPU is in DeepSleep." "0: Disabled.,1: Enabled." newline bitfld.long 0x0 8. "RREGEN,Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode." "0: Disabled.,1: Enabled." bitfld.long 0x0 7. "FVDDEN,Flash VDD Enabled" "0,1" newline bitfld.long 0x0 6. "BLKDET,Block Auto-Detect" "0: enable,1: disable" bitfld.long 0x0 4.--5. "OVR,Operating Voltage Range" "0: 0.9V 24MHz,1: 1.0V 48MHz,2: 1.1V 96MHz,?" newline bitfld.long 0x0 0.--1. "RAMRET,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 0 retention.,2: Enable System RAM 0 and 1 retention.,3: Enable System RAM 0 and 1 retention if RREGEN=0.." line.long 0x4 "LPWKST0,Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0." bitfld.long 0x4 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1" line.long 0x8 "LPWKEN0,Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0." hexmask.long 0x8 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register." line.long 0xC "LPWKST1,Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1." bitfld.long 0xC 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1" line.long 0x10 "LPWKEN1,Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1." hexmask.long 0x10 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register." line.long 0x14 "LPWKST2,Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2." bitfld.long 0x14 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1" line.long 0x18 "LPWKEN2,Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2." hexmask.long 0x18 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register." line.long 0x1C "LPWKST3,Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3." bitfld.long 0x1C 0. "WAKEST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1" line.long 0x20 "LPWKEN3,Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3." hexmask.long 0x20 0.--30. 1. "WAKEEN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register." group.long 0x30++0x7 line.long 0x0 "LPPWST,Low Power Peripheral Wakeup Status Register." bitfld.long 0x0 16. "BBMODEST,Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode." "0,1" bitfld.long 0x0 3. "SDMAWKST,Smart DMA Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transition from low to high or on high to low." "0,1" newline bitfld.long 0x0 2. "USBVBUSWKST,USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off." "0,1" bitfld.long 0x0 0.--1. "USBLSWKST,USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN." "0,1,2,3" line.long 0x4 "LPPWEN,Low Power Peripheral Wakeup Enable Register." bitfld.long 0x4 3. "SDMAWKEN,Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ." "0,1" bitfld.long 0x4 2. "USBVBUSWKEN,USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status." "0,1" newline bitfld.long 0x4 0.--1. "USBLSWKEN,USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set." "0,1,2,3" group.long 0x40++0x3 line.long 0x0 "LPMEMSD,Low Power Memory Shutdown Control." bitfld.long 0x0 14. "IC1SD,ICache 1 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 13. "ROM1SD,ROM1 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 12. "ROMSD,ROM Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 11. "USBFIFOSD,USB FIFO Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 10. "CRYPTOSD,Crypto MAA RAM Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 9. "SCACHESD,System Cache RAM Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 8. "ICACHEXIPSD,XiP Instruction Cache RAM Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 7. "ICACHESD,Instruction Cache RAM Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 6. "SRAM6SD,System RAM block 6 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 5. "SRAM5SD,System RAM block 5 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 4. "SRAM4SD,System RAM block 4 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 3. "SRAM3SD,System RAM block 3 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 2. "SRAM2SD,System RAM block 2 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." bitfld.long 0x0 1. "SRAM1SD,System RAM block 1 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." newline bitfld.long 0x0 0. "SRAM0SD,System RAM block 0 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode." group.long 0x48++0xF line.long 0x0 "BB_GP0,Battery Backed General Purpose Register 0" line.long 0x4 "BB_GP1,Battery Backed General Purpose Register 1" line.long 0x8 "LPMCSTAT,Low Power Multi-Core Status" line.long 0xC "LPMCREQ,Low Power Multi-Core Request" tree.end tree "RTC (Real-Time Clock)" base ad:0x40006000 group.long 0x0++0x1B line.long 0x0 "SEC,RTC Second Counter. This register contains the 32-bit second counter." line.long 0x4 "SSEC,RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00." hexmask.long.byte 0x4 0.--7. 1. "RTSS,RTC Sub-second Counter." line.long 0x8 "RAS,Time-of-day Alarm." hexmask.long.tbyte 0x8 0.--19. 1. "RAS,Time-of-day Alarm." line.long 0xC "RSSA,RTC sub-second alarm. This register contains the reload value for the sub-second alarm." hexmask.long 0xC 0.--31. 1. "RSSA,This register contains the reload value for the sub-second alarm." line.long 0x10 "CTRL,RTC Control Register." bitfld.long 0x10 15. "WE,Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits." "0: Not active,1: Active" bitfld.long 0x10 11.--12. "X32KMD,32KHz Oscillator Mode." "0: Always operate in Noise Immune Mode. Oscillator..,1: Always operate in Quiet Mode. No oscillator..,2: Operate in Noise Immune Mode normally switch to..,3: Operate in Noise Immune Mode normally switch to.." newline bitfld.long 0x10 9.--10. "FT,Frequency Output Selection. When SQE=1 these bits specify the output frequency on the SQW pin." "0: 1 Hz (Compensated).,1: 512 Hz (Compensated).,2: 4 KHz.,3: RTC Input Clock / 8." bitfld.long 0x10 8. "SQE,Square Wave Output Enable." "0: Not active,1: Active" newline rbitfld.long 0x10 7. "ALSF,Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor." "0: Not active,1: Active" rbitfld.long 0x10 6. "ALDF,Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor." "0: Not active,1: Active" newline bitfld.long 0x10 5. "RDYE,RTC Ready Interrupt Enable." "0: Disable.,1: Enable." bitfld.long 0x10 4. "RDY,RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register." "0: Register has not updated.,1: Ready." newline rbitfld.long 0x10 3. "BUSY,RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware." "0: Idle.,1: Busy." bitfld.long 0x10 2. "ASE,Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable." newline bitfld.long 0x10 1. "ADE,Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable." bitfld.long 0x10 0. "RTCE,Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable." line.long 0x14 "TRIM,RTC Trim Register." hexmask.long.tbyte 0x14 8.--31. 1. "VBATTMR,VBAT Timer Value. When RTC is running off of VBAT this field is incremented every 32 seconds." hexmask.long.byte 0x14 0.--7. 1. "TRIM,RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value with a maximum correction of +/- 127ppm." line.long 0x18 "OSCCTRL,RTC Oscillator Control Register." bitfld.long 0x18 5. "32KOUT,RTC 32kHz Square Wave Output" "0,1" bitfld.long 0x18 4. "BYPASS,RTC Crystal Bypass" "0,1" newline bitfld.long 0x18 3. "IBIAS_EN,RTC Oscillator Bias Current Enable" "0,1" bitfld.long 0x18 2. "HYST_EN,RTC Oscillator Hysteresis Buffer Enable" "0,1" newline bitfld.long 0x18 1. "IBIAS_SEL,RTC Oscillator 4X Bias Current Select" "0: Selects 2X bias current for RTC oscillator,1: Selects 4X bias current for RTC oscillator" bitfld.long 0x18 0. "FLITER_EN,RTC Oscillator Filter Enable" "0,1" tree.end tree "SDHC (SDHC/SDIO Controller)" base ad:0x40037000 group.long 0x0++0x3 line.long 0x0 "SDMA,SDMA System Address / Argument 2." hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address / Argument 2 of Auto CMD23." group.word 0x4++0x3 line.word 0x0 "BLK_SIZE,Block Size." bitfld.word 0x0 12.--14. "HOST_BUFF,Host SDMA Buffer Boundary." "0,1,2,3,4,5,6,7" hexmask.word 0x0 0.--11. 1. "TRANS,Transfer Block Size." line.word 0x2 "BLK_CNT,Block Count." hexmask.word 0x2 0.--15. 1. "COUNT,Blocks Count For Current Transfer." group.long 0x8++0x3 line.long 0x0 "ARG_1,Argument 1." hexmask.long 0x0 0.--31. 1. "CMD,Command Argument 1." group.word 0xC++0x3 line.word 0x0 "TRANS,Transfer Mode." bitfld.word 0x0 5. "MULTI,Multi / Single Block Select." "0,1" bitfld.word 0x0 4. "READ_WRITE,Data Transfer Direction Select." "0,1" bitfld.word 0x0 2.--3. "AUTO_CMD_EN,Auto CMD Enable." "0,1,2,3" bitfld.word 0x0 1. "BLK_CNT_EN,Block Count Enable." "0,1" newline bitfld.word 0x0 0. "DMA_EN,DMA Enable." "0,1" line.word 0x2 "CMD,Command." hexmask.word.byte 0x2 8.--13. 1. "IDX,Command Index." bitfld.word 0x2 6.--7. "TYPE,Command Type." "0,1,2,3" bitfld.word 0x2 5. "DATA_PRES_SEL,Data Present Select." "0,1" bitfld.word 0x2 4. "IDX_CHK_EN,Command Index Check Enable." "0,1" newline bitfld.word 0x2 3. "CRC_CHK_EN,Command CRC Check Enable." "0,1" bitfld.word 0x2 0.--1. "RESP_TYPE,Response Type Select." "0,1,2,3" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "RESP[$1],Response 0 Register 0-15." hexmask.long 0x0 0.--31. 1. "CMD_RESP,Command Response." repeat.end group.long 0x20++0x3 line.long 0x0 "BUFFER,Buffer Data Port." hexmask.long 0x0 0.--31. 1. "DATA,Buffer Data." rgroup.long 0x24++0x3 line.long 0x0 "PRESENT,Present State." bitfld.long 0x0 24. "CMD_SIGNAL_LEVEL,CMD Line Signal Level." "0,1" hexmask.long.byte 0x0 20.--23. 1. "DAT_SIGNAL_LEVEL,DAT[3:0] Line Signal Level." rbitfld.long 0x0 19. "WP,Write Protect Switch Pin Level." "0,1" rbitfld.long 0x0 18. "CARD_DETECT,Card Detect Pin Level." "0,1" newline rbitfld.long 0x0 17. "CARD_STATE,Card State Stable." "0,1" rbitfld.long 0x0 16. "CARD_INSERTED,Card Inserted." "0,1" rbitfld.long 0x0 11. "BUFFER_READ,Buffer Read Enable." "0,1" rbitfld.long 0x0 10. "BUFFER_WRITE,Buffer Write Enable." "0,1" newline rbitfld.long 0x0 9. "READ_TRANSFER,Read Transfer Active." "0,1" rbitfld.long 0x0 8. "WRITE_TRANSFER,Write Transfer Active." "0,1" rbitfld.long 0x0 3. "RETUNING,Re-Tuning Request." "0,1" rbitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active." "0,1" newline rbitfld.long 0x0 1. "DAT,Command Inhibit (DAT)." "0,1" rbitfld.long 0x0 0. "CMD,Command Inhibit (CMD)." "0,1" group.byte 0x28++0x3 line.byte 0x0 "HOST_CN_1,Host Control 1." bitfld.byte 0x0 7. "CARD_DETECT_SIGNAL,Card Detect Signal Selection." "0,1" bitfld.byte 0x0 6. "CARD_DETECT_TEST,Card Detect Test Level." "0,1" bitfld.byte 0x0 5. "EXT_DATA_TRANSFER_WIDTH,Extended Data Transfer Width." "0,1" bitfld.byte 0x0 3.--4. "DMA_SELECT,DMA Select." "0,1,2,3" newline bitfld.byte 0x0 2. "HS_EN,High Speed Enable." "0,1" bitfld.byte 0x0 1. "DATA_TRANSFER_WIDTH,Data Transfer Width." "0,1" bitfld.byte 0x0 0. "LED_CN,LED Control." "0,1" line.byte 0x1 "PWR,Power Control." bitfld.byte 0x1 1.--3. "BUS_VOLT_SEL,SD Bus Voltage Select." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 0. "BUS_POWER,SD Bus Power." "0,1" line.byte 0x2 "BLK_GAP,Block Gap Control." bitfld.byte 0x2 3. "INTR,Interrupt At Block Gap." "0,1" bitfld.byte 0x2 2. "READ_WAIT,Read Wait Control." "0,1" bitfld.byte 0x2 1. "CONT,Continue Request." "0,1" bitfld.byte 0x2 0. "STOP,Stop At Block Gap Request." "0,1" line.byte 0x3 "WAKEUP,Wakeup Control." bitfld.byte 0x3 2. "CARD_REM,Wakeup Event Enable On SD Card Removal." "0,1" bitfld.byte 0x3 1. "CARD_INS,Wakeup Event Enable On SD Card Insertion." "0,1" bitfld.byte 0x3 0. "CARD_INT,Wakeup Event Enable On Card Interrupt." "0,1" group.word 0x2C++0x1 line.word 0x0 "CLK_CN,Clock Control." hexmask.word.byte 0x0 8.--15. 1. "SDCLK_FREQ_SEL,SDCLK Frequency Select." bitfld.word 0x0 6.--7. "UPPER_SDCLK_FREQ_SEL,Upper Bits of SDCLK Frequency Select." "0,1,2,3" rbitfld.word 0x0 5. "CLK_GEN_SEL,Clock Generator Select." "0,1" bitfld.word 0x0 2. "SD_CLK_EN,SD Clock Enable." "0,1" newline rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable." "0,1" bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable." "0,1" group.byte 0x2E++0x1 line.byte 0x0 "TO,Timeout Control." bitfld.byte 0x0 0.--2. "DATA_COUNT_VALUE,Data Timeout Counter Value." "0,1,2,3,4,5,6,7" line.byte 0x1 "SW_RESET,Software Reset." bitfld.byte 0x1 2. "RESET_DAT,Software Reset For DAT Line." "0,1" bitfld.byte 0x1 1. "RESET_CMD,Software Reset For CMD Line." "0,1" bitfld.byte 0x1 0. "RESET_ALL,Software Reset For All." "0,1" group.word 0x30++0xF line.word 0x0 "INT_STAT,Normal Interrupt Status." bitfld.word 0x0 15. "ERR_INTR,Error Interrupt." "0,1" bitfld.word 0x0 12. "RETUNING,Re-Tuning Event." "0,1" bitfld.word 0x0 8. "CARD_INTR,Card Interrupt." "0,1" bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal." "0,1" newline bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion." "0,1" bitfld.word 0x0 5. "BUFF_RD_READY,Buffer Read Ready." "0,1" bitfld.word 0x0 4. "BUFF_WR_READY,Buffer Write Ready." "0,1" bitfld.word 0x0 3. "DMA,DMA Interrupt." "0,1" newline bitfld.word 0x0 2. "BLK_GAP_EVENT,Block Gap Event." "0,1" bitfld.word 0x0 1. "TRANS_COMP,Transfer Complete." "0,1" bitfld.word 0x0 0. "CMD_COMP,Command Complete." "0,1" line.word 0x2 "ER_INT_STAT,Error Interrupt Status." bitfld.word 0x2 12. "DMA,DMA Error." "0,1" bitfld.word 0x2 9. "ADMA,ADMA Error." "0,1" bitfld.word 0x2 8. "AUTO_CMD_12,Auto CMD Error." "0,1" bitfld.word 0x2 7. "CURRENT_LIMIT,Current Limit Error." "0,1" newline bitfld.word 0x2 6. "DATA_END_BIT,Data End Bit Error." "0,1" bitfld.word 0x2 5. "DATA_CRC,Data CRC Error." "0,1" bitfld.word 0x2 4. "DATA_TO,Data Timeout Error." "0,1" bitfld.word 0x2 3. "CMD_IDX,Command Index Error." "0,1" newline bitfld.word 0x2 2. "CMD_END_BIT,Command End Bit Error." "0,1" bitfld.word 0x2 1. "CMD_CRC,Command CRC Error." "0,1" bitfld.word 0x2 0. "CMD_TO,Command Timeout Error." "0,1" line.word 0x4 "INT_EN,Normal Interrupt Status Enable." bitfld.word 0x4 12. "RETUNING,Re-Tuning Event Status Enable." "0,1" bitfld.word 0x4 8. "CARD_INT,Card Interrupt Status Enable." "0,1" bitfld.word 0x4 7. "CARD_REMOVAL,Card Removal Status Enable." "0,1" bitfld.word 0x4 6. "CARD_INSERT,Card Insertion Status Enable." "0,1" newline bitfld.word 0x4 5. "BUFFER_RD,Buffer Read Ready Status Enable." "0,1" bitfld.word 0x4 4. "BUFFER_WR,Buffer Write Ready Status Enable." "0,1" bitfld.word 0x4 3. "DMA,DMA Interrupt Status Enable." "0,1" bitfld.word 0x4 2. "BLK_GAP,Block Gap Event Status Enable." "0,1" newline bitfld.word 0x4 1. "TRANS_COMP,Transfer Complete Status Enable." "0,1" bitfld.word 0x4 0. "CMD_COMP,Command Complete Status Enable." "0,1" line.word 0x6 "ER_INT_EN,Error Interrupt Status Enable." bitfld.word 0x6 12. "VENDOR,Vendor Specific Error Status Enable." "0,1" bitfld.word 0x6 10. "TUNING,Tuning Error Status Enable." "0,1" bitfld.word 0x6 9. "ADMA,ADMA Error Status Enable." "0,1" bitfld.word 0x6 8. "AUTO_CMD,Auto CMD Error Status Enable." "0,1" newline bitfld.word 0x6 6. "DATA_END_BIT,Data End Bit Error Status Enable." "0,1" bitfld.word 0x6 5. "DATA_CRC,Data CRC Error Status Enable." "0,1" bitfld.word 0x6 4. "DATA_TO,Data Timeout Error Status Enable." "0,1" bitfld.word 0x6 3. "CMD_IDX,Command Index Error Status Enable." "0,1" newline bitfld.word 0x6 2. "CMD_END_BIT,Command End Bit Error Status Enable." "0,1" bitfld.word 0x6 1. "CMD_CRC,Command CRC Error Status Enable." "0,1" bitfld.word 0x6 0. "CMD_TO,Command Timeout Error Status Enable." "0,1" line.word 0x8 "INT_SIGNAL,Normal Interrupt Signal Enable." bitfld.word 0x8 12. "RETUNING,Re-Tuning Event Signal Enable." "0,1" bitfld.word 0x8 8. "CARD_INT,Card Interrupt Signal Enable." "0,1" bitfld.word 0x8 7. "CARD_REMOVAL,Card Removal Signal Enable." "0,1" bitfld.word 0x8 6. "CARD_INSERT,Card Insertion Signal Enable." "0,1" newline bitfld.word 0x8 5. "BUFFER_RD,Buffer Read Ready Signal Enable." "0,1" bitfld.word 0x8 4. "BUFFER_WR,Buffer Write Ready Signal Enable." "0,1" bitfld.word 0x8 3. "DMA,DMA Interrupt Signal Enable." "0,1" bitfld.word 0x8 2. "BLK_GAP,Block Gap Event Signal Enable." "0,1" newline bitfld.word 0x8 1. "TRANS_COMP,Transfer Complete Signal Enable." "0,1" bitfld.word 0x8 0. "CMD_COMP,Command Complete Signal Enable." "0,1" line.word 0xA "ER_INT_SIGNAL,Error Interrupt Signal Enable." bitfld.word 0xA 12. "TAR_RESP,Target Response Error Signal Enable." "0,1" bitfld.word 0xA 10. "TUNING,Tuning Error Signal Enable." "0,1" bitfld.word 0xA 9. "ADMA,ADMA Error Signal Enable." "0,1" bitfld.word 0xA 8. "AUTO_CMD,Auto CMD Error Signal Enable." "0,1" newline bitfld.word 0xA 7. "CURR_LIM,Current Limit Error Signal Enable." "0,1" bitfld.word 0xA 6. "DATA_END_BIT,Data End Bit Error Signal Enable." "0,1" bitfld.word 0xA 5. "DATA_CRC,Data CRC Error Signal Enable." "0,1" bitfld.word 0xA 4. "DATA_TO,Data Timeout Error Signal Enable." "0,1" newline bitfld.word 0xA 3. "CMD_IDX,Command Index Error Signal Enable." "0,1" bitfld.word 0xA 2. "CMD_END_BIT,Command End Bit Error Signal Enable." "0,1" bitfld.word 0xA 1. "CMD_CRC,Command CRC Error Signal Enable." "0,1" bitfld.word 0xA 0. "CMD_TO,Command Timeout Error Signal Enable." "0,1" line.word 0xC "AUTO_CMD_ER,Auto CMD Error Status." bitfld.word 0xC 7. "NOT_ISSUED,Command Not Issued By Auto CMD12 Error." "0,1" bitfld.word 0xC 4. "INDEX,Auto CMD Index Error." "0,1" bitfld.word 0xC 3. "END_BIT,Auto CMD End Bit Error." "0,1" bitfld.word 0xC 2. "CRC,Auto CMD CRC Error." "0,1" newline bitfld.word 0xC 1. "TO,Auto CMD Timeout Error." "0,1" bitfld.word 0xC 0. "NOT_EXCUTED,Auto CMD12 Not Executed." "0,1" line.word 0xE "HOST_CN_2,Host Control 2." bitfld.word 0xE 15. "PRESET_VAL_EN,Preset Value Enable." "0,1" bitfld.word 0xE 14. "ASYNCH_INT,Asynchronous Interrupt Enable." "0,1" bitfld.word 0xE 7. "SAMPLING_CLK,Sampling Clock Select." "0,1" bitfld.word 0xE 6. "EXCUTE,Execute Tuning." "0,1" newline bitfld.word 0xE 4.--5. "DRIVER_STRENGTH,Driver Strength Select." "0,1,2,3" bitfld.word 0xE 3. "SIGNAL_V1_8,1.8V Signaling Enable." "0,1" bitfld.word 0xE 0.--1. "UHS,UHS Mode Select." "0,1,2,3" rgroup.long 0x40++0xB line.long 0x0 "CFG_0,Capabilities 0-31." bitfld.long 0x0 30.--31. "SLOT_TYPE,Slot Type." "0,1,2,3" bitfld.long 0x0 29. "ASYNC_INT,Asynchronous Interrupt Support." "0,1" bitfld.long 0x0 28. "BIT_64_SYS_BUS,64-bit System Bus Support." "0,1" bitfld.long 0x0 26. "V1_8,Voltage Support 1.8V." "0,1" newline bitfld.long 0x0 25. "V3_0,Voltage Support 3.0V." "0,1" bitfld.long 0x0 24. "V3_3,Voltage Support 3.3V." "0,1" bitfld.long 0x0 23. "SUSPEND,Suspend/Resume Support." "0,1" bitfld.long 0x0 22. "SDMA,SDMA Support." "0,1" newline bitfld.long 0x0 21. "HS,High Speed Support." "0,1" bitfld.long 0x0 19. "ADMA2,ADMA2 Support." "0,1" bitfld.long 0x0 18. "BIT_8,8-bit Support for Embedded Device." "0,1" bitfld.long 0x0 16.--17. "MAX_BLK_LEN,Max Block Length." "0,1,2,3" newline hexmask.long.byte 0x0 8.--15. 1. "CLK_FREQ,Base Clock Frequency For SD Clock." bitfld.long 0x0 7. "TO_CLK_UNIT,Timeout Clock Unit." "0,1" hexmask.long.byte 0x0 0.--5. 1. "TO_CLK_FREQ,Timeout Clock Frequency." line.long 0x4 "CFG_1,Capabilities 32-63." hexmask.long.byte 0x4 16.--23. 1. "CLK_MULTI,Clock Multiplier." bitfld.long 0x4 14.--15. "RETUNING,Re-Tuning Modes." "0,1,2,3" bitfld.long 0x4 13. "TUNING_SDR50,Use Tuning for SDR50." "0,1" hexmask.long.byte 0x4 8.--11. 1. "TIMER_CNT_TUNING,Timer Count for Re-Tuning." newline bitfld.long 0x4 6. "DRIVER_D,Driver Type D Support." "0,1" bitfld.long 0x4 5. "DRIVER_C,Driver Type C Support." "0,1" bitfld.long 0x4 4. "DRIVER_A,Driver Type A Support." "0,1" bitfld.long 0x4 2. "DDR50,DDR50 Support." "0,1" newline bitfld.long 0x4 1. "SDR104,SDR104 Support." "0,1" bitfld.long 0x4 0. "SDR50,SDR50 Support." "0,1" line.long 0x8 "MAX_CURR_CFG,Maximum Current Capabilities." hexmask.long.byte 0x8 16.--23. 1. "V1_8,Maximum Current for 1.8V." hexmask.long.byte 0x8 8.--15. 1. "V3_0,Maximum Current for 3.0V." hexmask.long.byte 0x8 0.--7. 1. "V3_3,Maximum Current for 3.3V." wgroup.word 0x50++0x1 line.word 0x0 "FORCE_CMD,Force Event for Auto CMD Error Status." bitfld.word 0x0 7. "NOT_ISSUED,Force Event for Command Not Issued By Auto CMD12 Error." "0,1" bitfld.word 0x0 4. "INDEX,Force Event for Auto CMD Index Error." "0,1" bitfld.word 0x0 3. "END_BIT,Force Event for Auto CMD End Bit Error." "0,1" bitfld.word 0x0 2. "CRC,Force Event for Auto CMD CRC Error." "0,1" newline bitfld.word 0x0 1. "TO,Force Event for Auto CMD Timeout Error." "0,1" bitfld.word 0x0 0. "NOT_EXCU,Force Event for Auto CMD12 Not Executed." "0,1" group.word 0x52++0x1 line.word 0x0 "FORCE_EVENT_INT_STAT,Force Event for Error Interrupt Status." bitfld.word 0x0 12.--14. "VENDOR,Force Event for Vendor Specific Error Status." "0,1,2,3,4,5,6,7" bitfld.word 0x0 9. "ADMA,Force Event for ADMA Error." "0,1" rbitfld.word 0x0 8. "AUTO_CMD,Force Event for Auto CMD Error." "0,1" rbitfld.word 0x0 7. "CURR_LIMIT,Force Event for Current Limit Error." "0,1" newline rbitfld.word 0x0 6. "DATA_END_BIT,Force Event for Data End Bit Error." "0,1" rbitfld.word 0x0 5. "DATA_CRC,Force Event for Data CRC Error." "0,1" rbitfld.word 0x0 4. "DATA_TO,Force Event for Data Timeout Error." "0,1" rbitfld.word 0x0 3. "CMD_INDEX,Force Event for Command Index Error." "0,1" newline rbitfld.word 0x0 2. "CMD_END_BIT,Force Event for Command End Bit Error." "0,1" rbitfld.word 0x0 1. "CMD_CRC,Force Event for Command CRC Error." "0,1" rbitfld.word 0x0 0. "CMD_TO,Force Event for Command Timeout Error." "0,1" group.byte 0x54++0x0 line.byte 0x0 "ADMA_ER,ADMA Error Status." bitfld.byte 0x0 2. "LEN_MISMATCH,ADMA Length Mismatch Error." "0,1" bitfld.byte 0x0 0.--1. "STATE,ADMA Error State." "0,1,2,3" group.long 0x58++0x7 line.long 0x0 "ADMA_ADDR_0,ADMA System Address 0-31." hexmask.long 0x0 0.--31. 1. "ADDR,ADMA System Address Part 1 (part 2 is ADMA_ADDR_1)." line.long 0x4 "ADMA_ADDR_1,ADMA System Address 32-63." hexmask.long 0x4 0.--31. 1. "ADDR,ADMA System Address Part 1 (part 2 is ADMA_ADDR_1)." rgroup.word 0x60++0xF line.word 0x0 "PRESET_0,Preset Value for Initialization." bitfld.word 0x0 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0x0 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0x0 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0x2 "PRESET_1,Preset Value for Default Speed." bitfld.word 0x2 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0x2 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0x2 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0x4 "PRESET_2,Preset Value for High Speed." bitfld.word 0x4 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0x4 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0x4 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0x6 "PRESET_3,Preset Value for SDR12." bitfld.word 0x6 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0x6 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0x6 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0x8 "PRESET_4,Preset Value for SDR25." bitfld.word 0x8 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0x8 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0x8 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0xA "PRESET_5,Preset Value for SDR50." bitfld.word 0xA 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0xA 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0xA 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0xC "PRESET_6,Preset Value for SDR104." bitfld.word 0xC 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0xC 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0xC 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." line.word 0xE "PRESET_7,Preset Value for DDR50." bitfld.word 0xE 14.--15. "DRIVER_STRENGTH,Driver Strength Select Value." "0,1,2,3" bitfld.word 0xE 10. "CLK_GEN,Clock Generator Select Value." "0,1" hexmask.word 0xE 0.--9. 1. "SDCLK_FREQ,SDCLK Frequency Select Value." group.long 0xE0++0x3 line.long 0x0 "SHARED_BUS,Shared Bus Control." rgroup.word 0xFC++0x1 line.word 0x0 "SLOT_INT,Slot Interrupt Status." bitfld.word 0x0 0. "INT_SIGNALS,Interrupt Signal For Each Slot." "0,1" group.word 0xFE++0x1 line.word 0x0 "HOST_CN_VER,Host Controller Version." hexmask.word.byte 0x0 8.--15. 1. "VEND_VER,Vendor Version Number." hexmask.word.byte 0x0 0.--7. 1. "SPEC_VER,Specification Version Number." tree.end tree "SDMA (Smart DMA)" base ad:0x40036000 rgroup.long 0x0++0x33 line.long 0x0 "IP,Q30E Instruction Pointer." line.long 0x4 "SP,Q30E Stack Pointer." line.long 0x8 "DP0,Q30E Data Pointer 0." line.long 0xC "DP1,Q30E Data Pointer 1." line.long 0x10 "BP,Q30E Frame Pointer Base." line.long 0x14 "OFFS,Q30E Frame Pointer Offset." line.long 0x18 "LC0,Q30E Loop Counter 0." line.long 0x1C "LC1,Q30E Loop Counter 1." line.long 0x20 "A0,Q30E Accumulator 0." line.long 0x24 "A1,Q30E Accumulator 1." line.long 0x28 "A2,Q30E Accumulator 2." line.long 0x2C "A3,Q30E Accumulator 3." line.long 0x30 "WDCN,Q30E Watchdog Control." group.long 0x80++0x17 line.long 0x0 "INT_MUX_CTRL0,Interrupt Mux Control 0." hexmask.long.byte 0x0 24.--31. 1. "INTSEL19,Interrupt Selection For 19th Interrupt." hexmask.long.byte 0x0 16.--23. 1. "INTSEL18,Interrupt Selection For 18th Interrupt." hexmask.long.byte 0x0 8.--15. 1. "INTSEL17,Interrupt Selection For 17th Interrupt." hexmask.long.byte 0x0 0.--7. 1. "INTSEL16,Interrupt Selection For 16th Interrupt." line.long 0x4 "INT_MUX_CTRL1,Interrupt Mux Control 1." hexmask.long.byte 0x4 24.--31. 1. "INTSEL23,Interrupt Selection For 23rd Interrupt." hexmask.long.byte 0x4 16.--23. 1. "INTSEL22,Interrupt Selection For 22nd Interrupt." hexmask.long.byte 0x4 8.--15. 1. "INTSEL21,Interrupt Selection For 21st Interrupt." hexmask.long.byte 0x4 0.--7. 1. "INTSEL20,Interrupt Selection For 20th Interrupt." line.long 0x8 "INT_MUX_CTRL2,Interrupt Mux Control 2." hexmask.long.byte 0x8 24.--31. 1. "INTSEL27,Interrupt Selection For 27th Interrupt." hexmask.long.byte 0x8 16.--23. 1. "INTSEL26,Interrupt Selection For 26th Interrupt." hexmask.long.byte 0x8 8.--15. 1. "INTSEL25,Interrupt Selection For 25th Interrupt." hexmask.long.byte 0x8 0.--7. 1. "INTSEL24,Interrupt Selection For 24th Interrupt." line.long 0xC "INT_MUX_CTRL3,Interrupt Mux Control 3." hexmask.long.byte 0xC 24.--31. 1. "INTSEL31,Interrupt Selection For 31st Interrupt." hexmask.long.byte 0xC 16.--23. 1. "INTSEL30,Interrupt Selection For 30th Interrupt." hexmask.long.byte 0xC 8.--15. 1. "INTSEL29,Interrupt Selection For 29th Interrupt." hexmask.long.byte 0xC 0.--7. 1. "INTSEL28,Interrupt Selection For 28th Interrupt." line.long 0x10 "IP_ADDR,Configurable starting IP address for Q30E." hexmask.long 0x10 0.--31. 1. "START_IP_ADDR,Starting IP address for Q30E" line.long 0x14 "CTRL,Control Register." bitfld.long 0x14 0. "EN,Enable SDMA." "0: Disable SDMA.,1: Enable SDMA." group.long 0xA0++0xB line.long 0x0 "INT_IN_CTRL,Interrupt Input From CPU Control Register." bitfld.long 0x0 0. "INTSET,Set Interrupt Flag." "0: Set interrupt Flag to 0.,1: Set Interrupt Flag to 1." line.long 0x4 "INT_IN_FLAG,Interrupt Input From CPU Flag." bitfld.long 0x4 0. "INTFLAG,Interrupt Flag." "0: No Effect.,1: INT_IN_FLAG =0" line.long 0x8 "INT_IN_IE,Interrupt Input From CPU Enable." bitfld.long 0x8 0. "INT_IN_EN,Interrupt Enable." "0,1" group.long 0xB0++0x7 line.long 0x0 "IRQ_FLAG,Interrupt Output To CPU Flag." bitfld.long 0x0 0. "IRQ_FLAG,Interrupt Flag." "0,1" line.long 0x4 "IRQ_IE,Interrupt Output To CPU Control Register." bitfld.long 0x4 0. "IRQ_EN,Interrupt Enable." "0,1" tree.end tree "SEMA (Semaphore)" base ad:0x4003E000 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "SEMAPHORES[$1],Read to test and set. returns prior value. Write 0 to clear semaphore." bitfld.long 0x0 0. "sema" "0,1" repeat.end group.long 0x100++0x3 line.long 0x0 "status,Semaphore status bits. 0 indicates the semaphore is free. 1 indicates taken." hexmask.long.byte 0x0 0.--7. 1. "STATUS" tree.end tree "SIR (System Initialization Registers)" base ad:0x40000400 rgroup.long 0x0++0x7 line.long 0x0 "SISTAT,System Initialization Status Register." bitfld.long 0x0 1. "CRCERR,CRC Error Status. This bit is set by the system initialization block following power-up." "0: No CRC errors occurred during the read of the..,1: A CRC error occurred while reading the OTP. The.." bitfld.long 0x0 0. "MAGIC,Magic Word Validation. This bit is set by the system initialization block following power-up." "0: Magic word was not set (OTP has not been..,1: Magic word was set (OTP contains valid settings)." line.long 0x4 "ERRADDR,Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)." hexmask.long 0x4 0.--31. 1. "ERRADDR" rgroup.long 0x100++0x7 line.long 0x0 "FSTAT,funcstat register." bitfld.long 0x0 8. "SCACHE,System Cache function." "0,1" bitfld.long 0x0 7. "SMPHR,SMPHR function." "0,1" bitfld.long 0x0 6. "SDHC,SDHC function." "0,1" bitfld.long 0x0 5. "HBC,HBC function." "0,1" newline bitfld.long 0x0 4. "PBM,PBM function." "0,1" bitfld.long 0x0 3. "XIP,XiP function." "0,1" bitfld.long 0x0 2. "ADC,10-bit Sigma Delta ADC." "0,1" bitfld.long 0x0 1. "USB,USB Device." "0,1" newline bitfld.long 0x0 0. "FPU,FPU Function." "0,1" line.long 0x4 "SFSTAT,secfuncstat register." bitfld.long 0x4 5. "MAA,MAA function." "0,1" bitfld.long 0x4 4. "SHA,SHA function." "0,1" bitfld.long 0x4 3. "AES,AES function." "0,1" bitfld.long 0x4 2. "TRNG,TRNG function." "0,1" tree.end tree "SMON (Security Monitor)" base ad:0x40004000 group.long 0x0++0xB line.long 0x0 "EXTSCN,External Sensor Control Register." bitfld.long 0x0 31. "LOCK,Lock Register. Once locked the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register." "0: Unlocked.,1: Locked." rbitfld.long 0x0 30. "BUSY,Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain." "0: Idle.,1: Update in Progress." bitfld.long 0x0 24.--26. "DIVCLK,Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits the error count threshold table and output.." "0: Divide by 1 (8000 Hz).,1: Divide by 2 (4000 Hz).,2: Divide by 4 (2000 Hz).,3: Divide by 8 (1000 Hz).,4: Divide by 16 (500 Hz).,5: Divide by 32 (250 Hz).,6: Divide by 64 (125 Hz).,?" newline bitfld.long 0x0 21.--23. "EXTFRQ,External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair." "0: Div 4 (2000Hz).,1: Div 8 (1000Hz).,2: Div 16 (500Hz).,3: Div 32 (250Hz).,4: Div 64 (125Hz).,5: Div 128 (63Hz).,6: Div 256 (31Hz).,7: Reserved. Do not use." hexmask.long.byte 0x0 16.--20. 1. "EXTCNT,External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered." bitfld.long 0x0 5. "EXTS_EN5,External Sensor Enable for input/output pair 5." "0: Disable.,1: Enable." newline bitfld.long 0x0 4. "EXTS_EN4,External Sensor Enable for input/output pair 4." "0: Disable.,1: Enable." bitfld.long 0x0 3. "EXTS_EN3,External Sensor Enable for input/output pair 3." "0: Disable.,1: Enable." bitfld.long 0x0 2. "EXTS_EN2,External Sensor Enable for input/output pair 2." "0: Disable.,1: Enable." newline bitfld.long 0x0 1. "EXTS_EN1,External Sensor Enable for input/output pair 1." "0: Disable.,1: Enable." bitfld.long 0x0 0. "EXTS_EN0,External Sensor Enable for input/output pair 0." "0: Disable.,1: Enable." line.long 0x4 "INTSCN,Internal Sensor Control Register." bitfld.long 0x4 31. "LOCK,Lock Register. Once locked the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register." "0: Unlocked.,1: Locked." bitfld.long 0x4 22. "VGLEN,Voltage Glitch Detection Enable." "0: Disable.,1: Enable." bitfld.long 0x4 21. "VDDHIEN,VDD Overvoltage Detect Enable." "0: Disable.,1: Enable." newline bitfld.long 0x4 20. "VDDLOEN,VDD Undervoltage Detect Enable." "0: Disable.,1: Enable." bitfld.long 0x4 19. "VCOREHIEN,VCORE Overvoltage Detect Enable." "0: Disable.,1: Enable." bitfld.long 0x4 18. "VCORELOEN,VCORE Undervoltage Detect Enable." "0: Disable.,1: Enable." newline bitfld.long 0x4 16. "LOTEMP_SEL,Low Temperature Detection Select." "0: -50 degrees C.,1: -30 degrees C." bitfld.long 0x4 2. "VBAT_EN,Battery Monitor Enable." "0: Disable.,1: Enable." bitfld.long 0x4 1. "TEMP_EN,Temperature Sensor Enable." "0: Disable.,1: Enable." newline bitfld.long 0x4 0. "SHIELD_EN,Die Shield Enable." "0: Disable.,1: Enable." line.long 0x8 "SECALM,Security Alarm Register." bitfld.long 0x8 29. "EXTSWARN5,External Sensor 5 Warning Ready flag. The tamper detect warning flags are set regardless of whether the external sensors are enabled." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 28. "EXTSWARN4,External Sensor 4 Warning Ready flag. The tamper detect warning flags are set regardless of whether the external sensors are enabled." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 27. "EXTSWARN3,External Sensor 3 Warning Ready flag. The tamper detect warning flags are set regardless of whether the external sensors are enabled." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 26. "EXTSWARN2,External Sensor 2 Warning Ready flag. The tamper detect warning flags are set regardless of whether the external sensors are enabled." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 25. "EXTSWARN1,External Sensor 1 Warning Ready flag. The tamper detect warning flags are set regardless of whether the external sensors are enabled." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 24. "EXTSWARN0,External Sensor 0 Warning Ready flag. The tamper detect warning flags are set regardless of whether the external sensors are enabled." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 21. "EXTSTAT5,External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 20. "EXTSTAT4,External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 19. "EXTSTAT3,External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 18. "EXTSTAT2,External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 17. "EXTSTAT1,External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 16. "EXTSTAT0,External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 12. "VGL,Voltage Glitch Detection Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 11. "VDDHI,VDD Overvoltage Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 10. "VCOREHI,VCORE Overvoltage Detect Flag." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 9. "VCORELO,VCORE Undervoltage Detect Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 8. "VDDLO,VDD Undervoltage Detect Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 7. "EXTF,External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 6. "BATHI,Battery Overvoltage Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 5. "BATLO,Battery Undervoltage Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 4. "HITEMP,High Temperature Detect." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x8 3. "LOTEMP,Low Temperature Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 2. "SHIELDF,Die Shield Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x8 1. "KEYWIPE,Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x8 0. "DRS,Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware." "0: No operation/complete.,1: Start operation." rgroup.long 0xC++0x7 line.long 0x0 "SECDIAG,Security Diagnostic Register." bitfld.long 0x0 21. "EXTSTAT5,External Sensor 5 Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 20. "EXTSTAT4,External Sensor 4 Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 19. "EXTSTAT3,External Sensor 3 Detect." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x0 18. "EXTSTAT2,External Sensor 2 Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 17. "EXTSTAT1,External Sensor 1 Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 16. "EXTSTAT0,External Sensor 0 Detect." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x0 8. "AESKT,AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR." "0: Key has not been transferred.,1: Key has been transferred." bitfld.long 0x0 7. "DYNF,Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 6. "BATHI,Battery Overvoltage Detect." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x0 5. "BATLO,Battery Undervoltage Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 4. "HITEMP,High Temperature Detect." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 3. "LOTEMP,Low Temperature Detect." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x0 2. "SHIELDF,Die Shield Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 0. "BORF,Battery-On-Reset Flag. This bit is set once the back up battery is conneted." "0: The event has not occurred.,1: The event has occurred." line.long 0x4 "DLRTC,DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred." hexmask.long 0x4 0.--31. 1. "DLRTC,DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured." rgroup.long 0x34++0x3 line.long 0x0 "SECST,Security Monitor Status Register." bitfld.long 0x0 2. "SECALRS,Security Alarm Register Status." "0: Access authorized.,1: Access not authorized." bitfld.long 0x0 1. "INTSRS,Internal Sensor Control Register Status." "0: Access authorized.,1: Access not authorized." bitfld.long 0x0 0. "EXTSRS,External Sensor Control Register Status." "0: Access authorized.,1: Access not authorized." tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI0" base ad:0x40046000 group.long 0x0++0x3 line.long 0x0 "DATA32,Register for reading and writing the FIFO." hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2)++0x1 line.word 0x0 "DATA16[$1],Register for reading and writing the FIFO." hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "DATA8[$1],Register for reading and writing the FIFO." hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end group.long 0x4++0x13 line.long 0x0 "CTRL0,Register for controlling SPI peripheral." hexmask.long.byte 0x0 16.--19. 1. "SS,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected." bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.." newline bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.." bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1." newline bitfld.long 0x0 1. "MASTER,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode." bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled." line.long 0x4 "CTRL1,Register for controlling SPI peripheral." hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive." hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit." line.long 0x8 "CTRL2,Register for controlling SPI peripheral." hexmask.long.byte 0x8 24.--31. 1. "SRPOL,Slave Ready Polarity each Slave Ready can have unique polarity." hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity." newline bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode." bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?" newline hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character." bitfld.long 0x8 4. "SCLK_INV,Reserved - Must Always Be Cleared to 0." "0,1" newline bitfld.long 0x8 1. "CPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3" bitfld.long 0x8 0. "CPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.." line.long 0xC "SS_TIME,Register for controlling SPI peripheral/Slave Select Timing." hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay." hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2." newline hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1." line.long 0x10 "CLK_CFG,Register for controlling SPI clock rate." hexmask.long.byte 0x10 16.--19. 1. "SCALE,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock." hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]." newline hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]." group.long 0x1C++0x13 line.long 0x0 "DMA,Register for controlling DMA." bitfld.long 0x0 31. "RX_DMA_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled." hexmask.long.byte 0x0 24.--29. 1. "RX_FIFO_CNT,Count of entries in RX FIFO." newline bitfld.long 0x0 23. "RX_FIFO_CLEAR,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.." bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled." newline hexmask.long.byte 0x0 16.--20. 1. "RX_FIFO_LEVEL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered." bitfld.long 0x0 15. "TX_DMA_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled." newline hexmask.long.byte 0x0 8.--13. 1. "TX_FIFO_CNT,Count of entries in TX FIFO." bitfld.long 0x0 7. "TX_FIFO_CLEAR,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. ." "?,1: Clear the Transmit FIFO clears any pending TX.." newline bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled." hexmask.long.byte 0x0 0.--4. 1. "TX_FIFO_LEVEL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered." line.long 0x4 "INT_FL,Register for reading and clearing interrupt flags. All bits are write 1 to clear." bitfld.long 0x4 15. "RX_UND,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 14. "RX_OVR,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 13. "TX_UND,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 12. "TX_OVR,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 11. "M_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 2. "RX_THRESH,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 1. "TX_EMPTY,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 0. "TX_THRESH,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x8 "INT_EN,Register for enabling interrupts." bitfld.long 0x8 15. "RX_UND,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 14. "RX_OVR,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 13. "TX_UND,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 12. "TX_OVR,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 11. "M_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 2. "RX_THRESH,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 1. "TX_EMPTY,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 0. "TX_THRESH,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0xC "WAKE_FL,Register for wake up flags. All bits in this register are write 1 to clear." bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0xC 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0xC 1. "TX_EMPTY,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0xC 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x10 "WAKE_EN,Register for wake up enable." bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x10 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." newline bitfld.long 0x10 1. "TX_EMPTY,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x10 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." rgroup.long 0x30++0x3 line.long 0x0 "STAT,SPI Status register." bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active." tree.end tree "SPI1" base ad:0x40047000 group.long 0x0++0x3 line.long 0x0 "DATA32,Register for reading and writing the FIFO." hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2)++0x1 line.word 0x0 "DATA16[$1],Register for reading and writing the FIFO." hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "DATA8[$1],Register for reading and writing the FIFO." hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end group.long 0x4++0x13 line.long 0x0 "CTRL0,Register for controlling SPI peripheral." hexmask.long.byte 0x0 16.--19. 1. "SS,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected." bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.." newline bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.." bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1." newline bitfld.long 0x0 1. "MASTER,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode." bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled." line.long 0x4 "CTRL1,Register for controlling SPI peripheral." hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive." hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit." line.long 0x8 "CTRL2,Register for controlling SPI peripheral." hexmask.long.byte 0x8 24.--31. 1. "SRPOL,Slave Ready Polarity each Slave Ready can have unique polarity." hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity." newline bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode." bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?" newline hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character." bitfld.long 0x8 4. "SCLK_INV,Reserved - Must Always Be Cleared to 0." "0,1" newline bitfld.long 0x8 1. "CPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3" bitfld.long 0x8 0. "CPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.." line.long 0xC "SS_TIME,Register for controlling SPI peripheral/Slave Select Timing." hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay." hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2." newline hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1." line.long 0x10 "CLK_CFG,Register for controlling SPI clock rate." hexmask.long.byte 0x10 16.--19. 1. "SCALE,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock." hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]." newline hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]." group.long 0x1C++0x13 line.long 0x0 "DMA,Register for controlling DMA." bitfld.long 0x0 31. "RX_DMA_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled." hexmask.long.byte 0x0 24.--29. 1. "RX_FIFO_CNT,Count of entries in RX FIFO." newline bitfld.long 0x0 23. "RX_FIFO_CLEAR,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.." bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled." newline hexmask.long.byte 0x0 16.--20. 1. "RX_FIFO_LEVEL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered." bitfld.long 0x0 15. "TX_DMA_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled." newline hexmask.long.byte 0x0 8.--13. 1. "TX_FIFO_CNT,Count of entries in TX FIFO." bitfld.long 0x0 7. "TX_FIFO_CLEAR,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. ." "?,1: Clear the Transmit FIFO clears any pending TX.." newline bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled." hexmask.long.byte 0x0 0.--4. 1. "TX_FIFO_LEVEL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered." line.long 0x4 "INT_FL,Register for reading and clearing interrupt flags. All bits are write 1 to clear." bitfld.long 0x4 15. "RX_UND,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 14. "RX_OVR,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 13. "TX_UND,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 12. "TX_OVR,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 11. "M_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 2. "RX_THRESH,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 1. "TX_EMPTY,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 0. "TX_THRESH,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x8 "INT_EN,Register for enabling interrupts." bitfld.long 0x8 15. "RX_UND,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 14. "RX_OVR,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 13. "TX_UND,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 12. "TX_OVR,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 11. "M_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 2. "RX_THRESH,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 1. "TX_EMPTY,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 0. "TX_THRESH,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0xC "WAKE_FL,Register for wake up flags. All bits in this register are write 1 to clear." bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0xC 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0xC 1. "TX_EMPTY,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0xC 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x10 "WAKE_EN,Register for wake up enable." bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x10 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." newline bitfld.long 0x10 1. "TX_EMPTY,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x10 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." rgroup.long 0x30++0x3 line.long 0x0 "STAT,SPI Status register." bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active." tree.end tree "SPI2" base ad:0x40048000 group.long 0x0++0x3 line.long 0x0 "DATA32,Register for reading and writing the FIFO." hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2)++0x1 line.word 0x0 "DATA16[$1],Register for reading and writing the FIFO." hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "DATA8[$1],Register for reading and writing the FIFO." hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end group.long 0x4++0x13 line.long 0x0 "CTRL0,Register for controlling SPI peripheral." hexmask.long.byte 0x0 16.--19. 1. "SS,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected." bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.." newline bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.." bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1." newline bitfld.long 0x0 1. "MASTER,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode." bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled." line.long 0x4 "CTRL1,Register for controlling SPI peripheral." hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive." hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit." line.long 0x8 "CTRL2,Register for controlling SPI peripheral." hexmask.long.byte 0x8 24.--31. 1. "SRPOL,Slave Ready Polarity each Slave Ready can have unique polarity." hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity." newline bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode." bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?" newline hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character." bitfld.long 0x8 4. "SCLK_INV,Reserved - Must Always Be Cleared to 0." "0,1" newline bitfld.long 0x8 1. "CPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3" bitfld.long 0x8 0. "CPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.." line.long 0xC "SS_TIME,Register for controlling SPI peripheral/Slave Select Timing." hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay." hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2." newline hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1." line.long 0x10 "CLK_CFG,Register for controlling SPI clock rate." hexmask.long.byte 0x10 16.--19. 1. "SCALE,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock." hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]." newline hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]." group.long 0x1C++0x13 line.long 0x0 "DMA,Register for controlling DMA." bitfld.long 0x0 31. "RX_DMA_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled." hexmask.long.byte 0x0 24.--29. 1. "RX_FIFO_CNT,Count of entries in RX FIFO." newline bitfld.long 0x0 23. "RX_FIFO_CLEAR,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.." bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled." newline hexmask.long.byte 0x0 16.--20. 1. "RX_FIFO_LEVEL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered." bitfld.long 0x0 15. "TX_DMA_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled." newline hexmask.long.byte 0x0 8.--13. 1. "TX_FIFO_CNT,Count of entries in TX FIFO." bitfld.long 0x0 7. "TX_FIFO_CLEAR,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. ." "?,1: Clear the Transmit FIFO clears any pending TX.." newline bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled." hexmask.long.byte 0x0 0.--4. 1. "TX_FIFO_LEVEL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered." line.long 0x4 "INT_FL,Register for reading and clearing interrupt flags. All bits are write 1 to clear." bitfld.long 0x4 15. "RX_UND,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 14. "RX_OVR,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 13. "TX_UND,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 12. "TX_OVR,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 11. "M_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 2. "RX_THRESH,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x4 1. "TX_EMPTY,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x4 0. "TX_THRESH,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x8 "INT_EN,Register for enabling interrupts." bitfld.long 0x8 15. "RX_UND,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 14. "RX_OVR,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 13. "TX_UND,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 12. "TX_OVR,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 11. "M_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 2. "RX_THRESH,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x8 1. "TX_EMPTY,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x8 0. "TX_THRESH,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0xC "WAKE_FL,Register for wake up flags. All bits in this register are write 1 to clear." bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0xC 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0xC 1. "TX_EMPTY,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0xC 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x10 "WAKE_EN,Register for wake up enable." bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x10 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." newline bitfld.long 0x10 1. "TX_EMPTY,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x10 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." rgroup.long 0x30++0x3 line.long 0x0 "STAT,SPI Status register." bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active." tree.end tree.end tree "SPIMSS (SPIMSS for I2S)" base ad:0x40018000 group.word 0x0++0x1 line.word 0x0 "DATA16,SPI 16-bit Data Access" hexmask.word 0x0 0.--15. 1. "DATA,SPI data." repeat 2. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "DATA8[$1],SPI Data 8-bit access" hexmask.byte 0x0 0.--7. 1. "DATA,SPI data." repeat.end group.long 0x4++0xB line.long 0x0 "CTRL,SPI Control Register." bitfld.long 0x0 7. "IRQE,Interrupt Request Enable." "0,1" bitfld.long 0x0 6. "STR,Start SPI Interrupt." "0: No operation/complete.,1: Start operation." newline bitfld.long 0x0 5. "BIRQ,Baud Rate Generator Timer Interrupt Request." "0,1" bitfld.long 0x0 4. "PHASE,Phase Select." "0: Transmit on active edge of SCLK.,1: Transmit on inactive edge of SCLK." newline bitfld.long 0x0 3. "CLKPOL,Clock Polarity." "0: SCLK idles Low (0) after character..,1: SCLK idles High (1) after character.." bitfld.long 0x0 2. "WOR,Wired OR (open drain) Enable." "0,1" newline bitfld.long 0x0 1. "MMEN,SPI Master Mode Enable." "0,1" bitfld.long 0x0 0. "SPIEN,SPI Enable." "0,1" line.long 0x4 "STATUS,SPI Status Register." eventfld.long 0x4 7. "IRQ,SPI Interrupt Request." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x4 6. "TOVR,Transmit Overrun." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x4 5. "COL,Collision." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x4 4. "ABT,Slave Mode Transaction Abort." "0: The event has not occurred.,1: The event has occurred." newline bitfld.long 0x4 3. "ROVR,Receive Overrun." "0: The event has not occurred.,1: The event has occurred." eventfld.long 0x4 2. "TUND,Transmit Underrun." "0: The event has not occurred.,1: The event has occurred." newline rbitfld.long 0x4 1. "TXST,Transmit Status." "0,1" rbitfld.long 0x4 0. "SLAS,Slave Select. If the SPI is in slave mode this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning." "0,1" line.long 0x8 "MOD,SPI Mode Register." bitfld.long 0x8 10. "SSL3,Slave Select 3. If SPI is enabled and in master mode the SSEL_3 is driven according to this bit." "0: High.,1: Low." bitfld.long 0x8 9. "SSL2,Slave Select 2. If SPI is enabled and in master mode the SSEL_2 is driven according to this bit." "0: High.,1: Low." newline bitfld.long 0x8 8. "SSL1,Slave Select 1. If SPI is enabled and in master mode the SSEL_1 is driven according to this bit." "0: High.,1: Low." bitfld.long 0x8 7. "TX_LJ,Transmit Left Justify." "0,1" newline hexmask.long.byte 0x8 2.--5. 1. "NUMBITS" bitfld.long 0x8 1. "SSIO,Slave Select I/O." "0,1" newline bitfld.long 0x8 0. "SSV,Slave Select Value." "0: The SSEL pin will be driven low.,1: The SSEL pin will be driven high." group.long 0x14++0xB line.long 0x0 "BRG,Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4)." hexmask.long.word 0x0 0.--15. 1. "BRG,Baud Rate Reload Value." line.long 0x4 "DMA,SPI DMA Register." bitfld.long 0x4 31. "RX_DMA_EN,Receive DMA Enable." "0,1" hexmask.long.byte 0x4 24.--27. 1. "RX_FIFO_CNT,Receive FIFO Count." newline bitfld.long 0x4 20. "RX_FIFO_CLEAR,Receive FIFO Clear." "0: No operation/complete.,1: Start operation." bitfld.long 0x4 16.--18. "RX_FIFO_LEVEL,Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 15. "TX_DMA_EN,Transmit DMA Enable." "0,1" hexmask.long.byte 0x4 8.--11. 1. "TX_FIFO_CNT,Transmit FIFO Count." newline bitfld.long 0x4 4. "TX_FIFO_CLEAR,Transmit FIFO Clear." "0: No operation/complete.,1: Start operation." bitfld.long 0x4 0.--2. "TX_FIFO_LEVEL,Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs." "0,1,2,3,4,5,6,7" line.long 0x8 "I2S_CTRL,I2S Control Register." bitfld.long 0x8 4. "I2S_LJ,I2S Left Justify." "0: Normal I2S audio protocol.,1: Audio data is synchronized with SSEL." bitfld.long 0x8 3. "I2S_MONO,I2S Monophonic Audio Mode." "0: Stereophonic audio.,1: Monophonic audio format.Each transmit data word.." newline bitfld.long 0x8 2. "I2S_PAUSE,I2S Pause transmit/receive." "0: Normal Transmit.,1: Halt transmit and receive FIFO and DMA access.." bitfld.long 0x8 1. "I2S_MUTE,I2S Mute transmit." "0: Normal Transmit.,1: Transmit data is replaced with 0." newline bitfld.long 0x8 0. "I2S_EN,I2S Mode Enable." "0,1" tree.end tree "SPIXF (SPI Execute-in-Place FLASH Master)" base ad:0x40026000 group.long 0x0++0x13 line.long 0x0 "CFG,SPIX Configuration Register." bitfld.long 0x0 18.--19. "SSIACT,Slave Select Inactive Timing." "0: 1 system clocks.,1: 3 System clocks.,2: 5 System clocks.,3: 9 System clocks." bitfld.long 0x0 16.--17. "SSACT,Slave Select Active Timing." "0: 0 system clocks.,1: 2 System clocks.,2: 4 System clocks.,3: 8 System clocks." newline hexmask.long.byte 0x0 12.--15. 1. "HI_CLK,Number of system clocks that SCLK will be high when SCLK pulses are generated." hexmask.long.byte 0x0 8.--11. 1. "LO_CLK,Number of system clocks that SCLK will be low when SCLK pulses are generated." newline bitfld.long 0x0 4.--6. "SSEL,Slave Select. Only valid value is zero." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SSPOL,Slave Select Polarity." "0: Slave Select is Active High.,1: Slave Select is Active Low." newline bitfld.long 0x0 0.--1. "MODE,Defines SPI Mode Only valid values are 0 and 3." "0: Description not available.,?,?,3: Description not available." line.long 0x4 "FETCH_CTRL,SPIX Fetch Control Register." bitfld.long 0x4 16. "FOUR_BYTE_ADDR,Four Byte Address Mode. Enables 4-byte Flash Address Mode." "0: 3 Byte Address Mode.,1: 4 Byte Address Mode." bitfld.long 0x4 12.--13. "DATA_WIDTH,Data Width. Number of data I/O used to receive data." "0: Single SDIO.,1: Dual SDIO.,2: Quad SDIO.,3: Invalid." newline bitfld.long 0x4 10.--11. "ADDR_WIDTH,Address Width. Number of data I/O used to send address and mode/dummy clocks." "0: Single SDIO.,1: Dual SDIO.,2: Quad SDIO.,3: Invalid." bitfld.long 0x4 8.--9. "CMD_WIDTH,Command Width. Number of data I/O used to send commands." "0: Single SDIO.,1: Dual SDIO.,2: Quad SDIO.,3: Invalid." newline hexmask.long.byte 0x4 0.--7. 1. "CMDVAL,Command Value sent to target to initiate fetching from SPI flash." line.long 0x8 "MODE_CTRL,SPIX Mode Control Register." bitfld.long 0x8 8. "NO_CMD,No Command Mode." "0: Send read command every time SPI transaction is..,1: Send read command only once. NO read command in.." hexmask.long.byte 0x8 0.--3. 1. "MDCLK,Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch." line.long 0xC "MODE_DATA,SPIX Mode Data Register." hexmask.long.word 0xC 16.--31. 1. "OUT_EN,Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off I/O is tristate and 1: Output enable on I/O is driving MD_DATA." hexmask.long.word 0xC 0.--15. 1. "DATA,Mode Data. Specifies the data to send with the Dummy/Mode clocks." line.long 0x10 "SCLK_FB_CTRL,SPIX Feedback Control Register." hexmask.long.byte 0x10 12.--17. 1. "IGNORE_CLKS_NO_CMD,Number of clocks to ignore after SS asertion prior to reading data when a read command is not explicitly sent." hexmask.long.byte 0x10 4.--9. 1. "IGNORE_CLKS,Number of clocks to ignore after SS asertion prior to reading data." newline bitfld.long 0x10 1. "INVERT_EN,Invert SCLK in feedback mode." "0: Disable Invert SCLK feedback mode.,1: Enable Invert SCLK feedback mode." bitfld.long 0x10 0. "FB_EN,Enable SCLK feedback mode." "0: Disable SCLK feedback mode.,1: Enable SCLK feedback mode." group.long 0x1C++0x7 line.long 0x0 "IO_CTRL,SPIX IO Control Register." bitfld.long 0x0 3.--4. "PU_PD_CTRL,IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins." "0: Tristate.,1: Pull-Up.,2: Pull-Down.,?" bitfld.long 0x0 2. "SDIO_DS,SDIO Drive Strength. This bit controls the drive strength of all SDIO pins." "0: Low drive strength.,1: High drive strength." newline bitfld.long 0x0 1. "SS_DS,Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin." "0: Low drive strength.,1: High drive strength." bitfld.long 0x0 0. "SCLK_DS,SCLK drive Strength. This bit controls the drive strength on the SCLK pin." "0: Low drive strength.,1: High drive strength." line.long 0x4 "MEMSECCN,SPIX Memory Security Control Register." bitfld.long 0x4 0. "DECEN,Decryption Enable." "0: Disable decryption of SPIX data.,1: Enable decryption of SPIX data." tree.end tree "SPIXF_FIFO (SPIXF Master Controller FIFO)" base ad:0x400BC000 group.byte 0x0++0x0 line.byte 0x0 "TX_8,SPI TX FIFO 8-Bit Write" group.word 0x0++0x1 line.word 0x0 "TX_16,SPI TX FIFO 16-Bit Write" group.long 0x0++0x3 line.long 0x0 "TX_32,SPI TX FIFO 32-Bit Write" group.byte 0x4++0x0 line.byte 0x0 "RX_8,SPI RX FIFO 8-Bit Access" group.word 0x4++0x1 line.word 0x0 "RX_16,SPI RX FIFO 16-Bit Access" group.long 0x4++0x3 line.long 0x0 "RX_32,SPI RX FIFO 32-Bit Access" tree.end tree "SPIXFC (SPI Execute-in-Place FLASH Master Controller)" base ad:0x40027000 group.long 0x0++0x1B line.long 0x0 "CFG,Configuration Register." bitfld.long 0x0 18.--19. "SS_INACT,Slaves Select Inactive Timing." "0: 4 sytem clocks.,1: 6 sytem clocks.,2: 8 sytem clocks.,3: 12 sytem clocks." bitfld.long 0x0 16.--17. "SS_ACT,Slaves Select Activate Timing." "0: 0 sytem clocks.,1: 2 sytem clocks.,2: 4 sytem clocks.,3: 8 sytem clocks." newline hexmask.long.byte 0x0 12.--15. 1. "LO_CLK,SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and all other values defines the number of system clock taht SCLK will be held low." hexmask.long.byte 0x0 8.--11. 1. "HI_CLK,SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and all other values defines the number of system clock taht SCLK will be held high." newline bitfld.long 0x0 6.--7. "PAGE_SIZE,Page Size." "0: 4 bytes.,1: 8 bytes.,2: 16 bytes.,3: 32 bytes." bitfld.long 0x0 4.--5. "MODE,Defines SPI Mode Only valid values are 0 and 3." "0: SPIX Mode 0. CLK Polarity = 0 CLK Phase = 0.,?,?,3: SPIX Mode 3. CLK Polarity = 1 CLK Phase = 1." newline bitfld.long 0x0 0.--2. "SSEL,Slaves Select." "0: Slave 0 is selected.,1: Slave 1 is selected.,?,?,?,?,?,?" line.long 0x4 "SS_POL,SPIX Controller Slave Select Polarity Register." bitfld.long 0x4 0. "SS_POLARITY,Slave Select Polarity." "0: Active Low.,1: Active High." line.long 0x8 "GEN_CTRL,SPIX Controller General Controller Register." bitfld.long 0x8 24. "SCLK_FB,Enable SCLK Feedback Mode." "0,1" hexmask.long.byte 0x8 16.--19. 1. "BB_DATA_OUT_EN,Bit Bang SDIO Output Enable." newline hexmask.long.byte 0x8 12.--15. 1. "BB_DATA,No description available." hexmask.long.byte 0x8 8.--11. 1. "SDIO_DATA_IN,SDIO Input Data Value." newline bitfld.long 0x8 6. "SCLK_DR,SSCLK Drive and State." "0: SCLK is 0.,1: SCLK is 1." bitfld.long 0x8 4. "SSDR,This bits reflects the state of the currently selected slave select." "0: Selected Slave select output = 0.,1: Selected Slave select output = 1." newline bitfld.long 0x8 3. "BBMODE,Bit-Bang Mode." "0: Disable Bit-Bang Mode.,1: Enable Bit-Bang Mode." bitfld.long 0x8 2. "RX_FIFO_EN,Result FIFO Enable." "0: Disable Result FIFO.,1: Enable Result FIFO." newline bitfld.long 0x8 1. "TX_FIFO_EN,Transaction FIFO Enable." "0: Disable Transaction FIFO.,1: Enable Transaction FIFO." bitfld.long 0x8 0. "ENABLE,SPI Master enable." "0: Disable SPI Master putting a reset state.,1: Enable SPI Master for processing transactions." line.long 0xC "FIFO_CTRL,SPIX Controller FIFO Control and Status Register." hexmask.long.byte 0xC 24.--29. 1. "RX_FIFO_CNT,Result FIFO Used." hexmask.long.byte 0xC 16.--20. 1. "RX_FIFO_AF_LVL,Results FIFO Almost Full Level." newline hexmask.long.byte 0xC 8.--12. 1. "TX_FIFO_CNT,Transaction FIFO Used." hexmask.long.byte 0xC 0.--3. 1. "TX_FIFO_AE_LVL,Transaction FIFO Almost Empty Level." line.long 0x10 "SPCTRL,SPIX Controller Special Control Register." bitfld.long 0x10 16. "SCLKINH3,SCLK Inhibit Mode3. In SPI Mode 3 some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3 the.." "0: Allow trailing SCLK low pulse prior to Slave..,1: Inhibit trailing SCLK low pulse prior to Slave.." line.long 0x14 "INTFL,SPIX Controller Interrupt Status Register." bitfld.long 0x14 5. "RX_FIFO_AF,Results FIFO Almost Full Flag." "0: Results FIFO level below the Almost Full level.,1: Results FIFO level at Almost Full level." bitfld.long 0x14 4. "TX_FIFO_AE,Transaction FIFO Almost Empty Flag." "0: Transaction FIFO not Almost Empty.,1: Transaction FIFO Almost Empty." newline bitfld.long 0x14 3. "RX_DONE,Results Done Interrupt Status." "0: Results FIFO ready.,1: Results FIFO Not ready." bitfld.long 0x14 2. "TX_READY,Transaction Ready Interrupt Status." "0: FIFO Transaction not ready.,1: FIFO Transaction ready." newline bitfld.long 0x14 1. "RX_STALLED,Results Stalled Interrupt Flag." "0: Normal FIFO Operation.,1: Stalled FIFO." bitfld.long 0x14 0. "TX_STALLED,Transaction Stalled Interrupt Flag." "0: Normal FIFO Transaction.,1: Stalled FIFO Transaction." line.long 0x18 "INTEN,SPIX Controller Interrupt Enable Register." bitfld.long 0x18 5. "RX_FIFO_AF,Results FIFO Almost Full Interrupt Enable." "0: Disable Results FIFO Almost Full Interrupt.,1: Enable Results FIFO Almost Full Interrupt." bitfld.long 0x18 4. "TX_FIFO_AE,Transaction FIFO Almost Empty Interrupt Enable." "0: Disable Transaction FIFO Almost Empty Interrupt.,1: Enable Transaction FIFO Almost Empty Interrupt." newline bitfld.long 0x18 3. "RX_DONE,Results Done Interrupt Enable." "0: Disable Results Done Interrupt.,1: Enable Results Done Interrupt." bitfld.long 0x18 2. "TX_READY,Transaction Ready Interrupt Enable." "0: Disable FIFO Transaction Ready Interrupt.,1: Enable FIFO Transaction Ready Interrupt." newline bitfld.long 0x18 1. "RX_STALLED,Results Stalled Interrupt Enable." "0: Disable Results Stalled Interrupt.,1: Enable Results Stalled Interrupt." bitfld.long 0x18 0. "TX_STALLED,Transaction Stalled Interrupt Enable." "0: Disable Transaction Stalled Interrupt.,1: Enable Transaction Stalled Interrupt." tree.end tree "SPIXR (SPI Execute-in-Place RAM)" base ad:0x4003A000 group.long 0x0++0x3 line.long 0x0 "DATA32,Register for reading and writing the FIFO." hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2)++0x1 line.word 0x0 "DATA16[$1],Register for reading and writing the FIFO." hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "DATA8[$1],Register for reading and writing the FIFO." hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO." repeat.end group.long 0x4++0x2B line.long 0x0 "ctrl1,Register for controlling SPI peripheral." hexmask.long.byte 0x0 16.--23. 1. "SS,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected." bitfld.long 0x0 8. "SS_CTRL,Slave Select Control." "0: SPI de-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.." newline bitfld.long 0x0 5. "TX_START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.." bitfld.long 0x0 4. "SSIO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1." newline bitfld.long 0x0 3. "FL_EN,Flow Control Mode Enable." "0: Flow Control mode is disabled.,1: Flow Control Mode is enabled." bitfld.long 0x0 2. "TIMER,Timer Enable." "0: Timer is disabled.,1: Timer is enabled only valid if SPIEN=0." newline bitfld.long 0x0 1. "MMEN,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode." bitfld.long 0x0 0. "SPIEN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled." line.long 0x4 "ctrl2,Register for controlling SPI peripheral." hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive." hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit." line.long 0x8 "ctrl3,Register for controlling SPI peripheral." hexmask.long.byte 0x8 24.--31. 1. "SRPOL,Slave Ready Polarity each Slave Ready can have unique polarity." hexmask.long.byte 0x8 16.--23. 1. "SSPOL,Slave Select Polarity each Slave Select can have unique polarity." newline bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode." bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?" newline hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character." bitfld.long 0x8 4. "SCLK_FB_INV,Invert SCLK Feedback in Master Mode." "0: SCLK is not inverted to Line Receiver.,1: SCLK is inverted to Line Receiver." newline bitfld.long 0x8 1. "CPOL,Clock Polarity." "0,1" bitfld.long 0x8 0. "CPHA,Clock Phase." "0,1" line.long 0xC "ctrl4,Register for controlling SPI peripheral." hexmask.long.byte 0xC 16.--23. 1. "SSINACT,Slave Select Inactive delay." hexmask.long.byte 0xC 8.--15. 1. "SSACT2,Slave Select Action delay 2." newline hexmask.long.byte 0xC 0.--7. 1. "SSACT1,Slave Select Action delay 1." line.long 0x10 "BRG_CTRL,Register for controlling SPI clock rate." hexmask.long.byte 0x10 16.--19. 1. "SCALE,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock." hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]." newline hexmask.long.byte 0x10 0.--7. 1. "LOW,Low duty cycle control. In timer mode reload[7:0]." line.long 0x14 "I2S_CTRL,Register for controlling I2C mode." bitfld.long 0x14 4. "I2S_LJ,I2S Left Justify." "0: Normal I 2 S audio protocol audio data lags..,1: Audio data is synchronized with SSEL (left/right.." bitfld.long 0x14 3. "I2S_MONO,I2S Monotone." "0: Stereophonic audio format.,1: Monophonic audio format. Each transmit data word.." newline bitfld.long 0x14 2. "I2S_PAUSE,I2S Pause." "0: Normal Transmit/Receive.,1: Halt Transmit and Receive FIFO and DMA accesses.." bitfld.long 0x14 1. "I2S_MUTE,I2S Mute." "0: Normal Transmit.,1: Transmit data is replaced with 0." newline bitfld.long 0x14 0. "I2S_EN,Low duty cycle control. In timer mode reload[7:0]." "0: I2C mode is disabled.,1: I2C mode is enabled." line.long 0x18 "DMA,Register for controlling DMA." bitfld.long 0x18 31. "RX_DMA_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled." hexmask.long.byte 0x18 24.--29. 1. "RX_FIFO_CNT,Count of entries in RX FIFO." newline bitfld.long 0x18 23. "RX_FIFO_CLEAR,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFIO clears any pending RX.." bitfld.long 0x18 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled." newline hexmask.long.byte 0x18 16.--21. 1. "RX_FIFO_LEVEL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered." bitfld.long 0x18 15. "TX_DMA_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled." newline hexmask.long.byte 0x18 8.--12. 1. "TX_FIFO_CNT,Count of entries in TX FIFO." bitfld.long 0x18 7. "TX_FIFO_CLEAR,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.." newline bitfld.long 0x18 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled." hexmask.long.byte 0x18 0.--5. 1. "TX_FIFO_LEVEL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered." line.long 0x1C "IRQ,Register for reading and clearing interrupt flags. All bits are write 1 to clear." bitfld.long 0x1C 23. "SR7A,Slave Ready 7 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 22. "SR6A,Slave Ready 6 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 21. "SR5A,Slave Ready 5 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 20. "SR4A,Slave Ready 4 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 19. "SR3A,Slave Ready 3 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 18. "SR2A,Slave Ready 2 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 17. "SR1A,Slave Ready 1 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 16. "SR0A,Slave Ready 0 Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 15. "RX_UND,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 14. "RX_OVR,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 13. "TX_UND,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 12. "TX_OVR,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 11. "M_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 10. "TIMEOUT,Timeout." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 2. "RX_THRESH,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x1C 1. "TX_EMPTY,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x1C 0. "TX_THRESH,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x20 "IRQE,Register for enabling interrupts." bitfld.long 0x20 23. "SR7A,Slave Ready 7 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 22. "SR6A,Slave Ready 6 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 21. "SR5A,Slave Ready 5 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 20. "SR4A,Slave Ready 4 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 19. "SR3A,Slave Ready 3 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 18. "SR2A,Slave Ready 2 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 17. "SR1A,Slave Ready 1 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 16. "SR0A,Slave Ready 0 Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 15. "RX_UND,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 14. "RX_OVR,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 13. "TX_UND,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 12. "TX_OVR,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 11. "M_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 10. "TIMEOUT,Timeout interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 2. "RX_THRESH,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." newline bitfld.long 0x20 1. "TX_EMPTY,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." bitfld.long 0x20 0. "TX_THRESH,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled." line.long 0x24 "WAKE,Register for wake up flags. All bits in this register are write 1 to clear." bitfld.long 0x24 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x24 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." newline bitfld.long 0x24 1. "TX_EMPTY,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.." bitfld.long 0x24 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.." line.long 0x28 "WAKEE,Register for wake up enable." bitfld.long 0x28 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x28 2. "RX_THRESH,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." newline bitfld.long 0x28 1. "TX_EMPTY,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." bitfld.long 0x28 0. "TX_THRESH,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled." rgroup.long 0x30++0x3 line.long 0x0 "STAT,SPI Status register." bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active." group.long 0x34++0x3 line.long 0x0 "XMEM_CTRL,Register to control external memory." bitfld.long 0x0 31. "XMEM_EN,XMEM enable." "0,1" hexmask.long.byte 0x0 16.--23. 1. "DUMMY_CLK,Dummy clocks." newline hexmask.long.byte 0x0 8.--15. 1. "WR_CMD,Write command." hexmask.long.byte 0x0 0.--7. 1. "RD_CMD,Read command." tree.end tree "TMR (Timers)" base ad:0x0 tree "TMR0" base ad:0x40010000 group.long 0x0++0x17 line.long 0x0 "CNT,Count. This register stores the current timer count." line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001." line.long 0x8 "PWM,PWM. This register stores the value that is compared to the current timer count." line.long 0xC "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt." bitfld.long 0xC 0. "IRQ_CLR,Clear Interrupt." "0,1" line.long 0x10 "CN,Timer Control Register." bitfld.long 0x10 12. "PWMCKBD,Timer PWM output 0A Mode Disable." "0: Enable.,1: Disable." bitfld.long 0x10 11. "NOLLPOL,Timer PWM output 0A' polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 10. "NOLHPOL,Timer PWM output 0A polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 9. "PWMSYNC,Timer PWM Synchronization Mode Enable." "0: Disable.,1: Enable." bitfld.long 0x10 8. "PRES3,MSB of prescaler value." "0,1" newline bitfld.long 0x10 7. "TEN,Timer Enable." "0: Disable.,1: Enable." bitfld.long 0x10 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low." bitfld.long 0x10 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." bitfld.long 0x10 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,3: PWM Mode.,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode." line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register." hexmask.long.byte 0x14 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A." hexmask.long.byte 0x14 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'." tree.end tree "TMR1" base ad:0x40011000 group.long 0x0++0x17 line.long 0x0 "CNT,Count. This register stores the current timer count." line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001." line.long 0x8 "PWM,PWM. This register stores the value that is compared to the current timer count." line.long 0xC "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt." bitfld.long 0xC 0. "IRQ_CLR,Clear Interrupt." "0,1" line.long 0x10 "CN,Timer Control Register." bitfld.long 0x10 12. "PWMCKBD,Timer PWM output 0A Mode Disable." "0: Enable.,1: Disable." bitfld.long 0x10 11. "NOLLPOL,Timer PWM output 0A' polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 10. "NOLHPOL,Timer PWM output 0A polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 9. "PWMSYNC,Timer PWM Synchronization Mode Enable." "0: Disable.,1: Enable." bitfld.long 0x10 8. "PRES3,MSB of prescaler value." "0,1" newline bitfld.long 0x10 7. "TEN,Timer Enable." "0: Disable.,1: Enable." bitfld.long 0x10 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low." bitfld.long 0x10 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." bitfld.long 0x10 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,3: PWM Mode.,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode." line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register." hexmask.long.byte 0x14 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A." hexmask.long.byte 0x14 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'." tree.end tree "TMR2" base ad:0x40012000 group.long 0x0++0x17 line.long 0x0 "CNT,Count. This register stores the current timer count." line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001." line.long 0x8 "PWM,PWM. This register stores the value that is compared to the current timer count." line.long 0xC "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt." bitfld.long 0xC 0. "IRQ_CLR,Clear Interrupt." "0,1" line.long 0x10 "CN,Timer Control Register." bitfld.long 0x10 12. "PWMCKBD,Timer PWM output 0A Mode Disable." "0: Enable.,1: Disable." bitfld.long 0x10 11. "NOLLPOL,Timer PWM output 0A' polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 10. "NOLHPOL,Timer PWM output 0A polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 9. "PWMSYNC,Timer PWM Synchronization Mode Enable." "0: Disable.,1: Enable." bitfld.long 0x10 8. "PRES3,MSB of prescaler value." "0,1" newline bitfld.long 0x10 7. "TEN,Timer Enable." "0: Disable.,1: Enable." bitfld.long 0x10 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low." bitfld.long 0x10 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." bitfld.long 0x10 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,3: PWM Mode.,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode." line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register." hexmask.long.byte 0x14 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A." hexmask.long.byte 0x14 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'." tree.end tree "TMR3" base ad:0x40013000 group.long 0x0++0x17 line.long 0x0 "CNT,Count. This register stores the current timer count." line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001." line.long 0x8 "PWM,PWM. This register stores the value that is compared to the current timer count." line.long 0xC "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt." bitfld.long 0xC 0. "IRQ_CLR,Clear Interrupt." "0,1" line.long 0x10 "CN,Timer Control Register." bitfld.long 0x10 12. "PWMCKBD,Timer PWM output 0A Mode Disable." "0: Enable.,1: Disable." bitfld.long 0x10 11. "NOLLPOL,Timer PWM output 0A' polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 10. "NOLHPOL,Timer PWM output 0A polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 9. "PWMSYNC,Timer PWM Synchronization Mode Enable." "0: Disable.,1: Enable." bitfld.long 0x10 8. "PRES3,MSB of prescaler value." "0,1" newline bitfld.long 0x10 7. "TEN,Timer Enable." "0: Disable.,1: Enable." bitfld.long 0x10 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low." bitfld.long 0x10 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." bitfld.long 0x10 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,3: PWM Mode.,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode." line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register." hexmask.long.byte 0x14 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A." hexmask.long.byte 0x14 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'." tree.end tree "TMR4" base ad:0x40014000 group.long 0x0++0x17 line.long 0x0 "CNT,Count. This register stores the current timer count." line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001." line.long 0x8 "PWM,PWM. This register stores the value that is compared to the current timer count." line.long 0xC "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt." bitfld.long 0xC 0. "IRQ_CLR,Clear Interrupt." "0,1" line.long 0x10 "CN,Timer Control Register." bitfld.long 0x10 12. "PWMCKBD,Timer PWM output 0A Mode Disable." "0: Enable.,1: Disable." bitfld.long 0x10 11. "NOLLPOL,Timer PWM output 0A' polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 10. "NOLHPOL,Timer PWM output 0A polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 9. "PWMSYNC,Timer PWM Synchronization Mode Enable." "0: Disable.,1: Enable." bitfld.long 0x10 8. "PRES3,MSB of prescaler value." "0,1" newline bitfld.long 0x10 7. "TEN,Timer Enable." "0: Disable.,1: Enable." bitfld.long 0x10 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low." bitfld.long 0x10 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." bitfld.long 0x10 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,3: PWM Mode.,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode." line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register." hexmask.long.byte 0x14 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A." hexmask.long.byte 0x14 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'." tree.end tree "TMR5" base ad:0x40015000 group.long 0x0++0x17 line.long 0x0 "CNT,Count. This register stores the current timer count." line.long 0x4 "CMP,Compare. This register stores the compare value. which is used to set the maximum count value to initiate a reload of the timer to 0x0001." line.long 0x8 "PWM,PWM. This register stores the value that is compared to the current timer count." line.long 0xC "INTR,Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt." bitfld.long 0xC 0. "IRQ_CLR,Clear Interrupt." "0,1" line.long 0x10 "CN,Timer Control Register." bitfld.long 0x10 12. "PWMCKBD,Timer PWM output 0A Mode Disable." "0: Enable.,1: Disable." bitfld.long 0x10 11. "NOLLPOL,Timer PWM output 0A' polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 10. "NOLHPOL,Timer PWM output 0A polarity bit." "0: Disable.,1: Enable." bitfld.long 0x10 9. "PWMSYNC,Timer PWM Synchronization Mode Enable." "0: Disable.,1: Enable." bitfld.long 0x10 8. "PRES3,MSB of prescaler value." "0,1" newline bitfld.long 0x10 7. "TEN,Timer Enable." "0: Disable.,1: Enable." bitfld.long 0x10 6. "TPOL,Timer input/output polarity bit." "0: Active High.,1: Active Low." bitfld.long 0x10 3.--5. "PRES,Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128." bitfld.long 0x10 0.--2. "TMODE,Timer Mode." "0: One Shot Mode.,1: Continuous Mode.,2: Counter Mode.,3: PWM Mode.,4: Capture Mode.,5: Compare Mode.,6: Gated Mode.,7: Capture/Compare Mode." line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register." hexmask.long.byte 0x14 8.--15. 1. "NOLHCMP,Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A." hexmask.long.byte 0x14 0.--7. 1. "NOLLCMP,Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'." tree.end tree.end tree "TRNG (True Random Number Generator)" base ad:0x400B5000 group.long 0x0++0x3 line.long 0x0 "CN,TRNG Control Register." bitfld.long 0x0 6. "AESKG,AES Key Generate. When enabled the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the.." "0: No operation/complete.,1: Start operation." rbitfld.long 0x0 5. "RNG_IS,Random Number Word Status. This bit is set when at least one 32 bit random number is ready to be read. This bit is cleared by hardware if all the random words have been read. It is needed to poll this bit before reading the TRNG Data Register." "0: Result not ready.,1: Operation complete and result ready." rbitfld.long 0x0 4. "RNG_I4S,Random Number 4 Word Status. This bit is set when a new 128 bit random number is ready to be read (using 4 consecutive reads of the TRNG Data Register). When set an interrupt will be generated if the RNG_IE bit is also set. This bit is cleared.." "0: Result not ready.,1: Operation complete and result ready." newline bitfld.long 0x0 3. "RNG_ISC,Random Number Interrupt Status Clear. Setting this bit to 1 clears the RNG_I4S bit and acknowledges the interrupt if enabled. This bit is a write only bit and always reads as zero." "0: No Effect.,1: Clear the Status bit." bitfld.long 0x0 2. "RNG_IE,Random Number Interrupt Enable. This bit enables an interrupt to be generated when a new 128 bit random number is ready to be read." "0: Disable.,1: Enable." rgroup.long 0x4++0x3 line.long 0x0 "DATA,Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled. read returns 0x0000 0000." hexmask.long 0x0 0.--31. 1. "DATA,Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled read returns 0x0000 0000." tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x0 tree "UART0" base ad:0x40042000 group.long 0x0++0x7 line.long 0x0 "CTRL,Control Register." hexmask.long.byte 0x0 16.--23. 1. "RX_TO,RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read." newline bitfld.long 0x0 15. "CLKSEL,Baud Rate Clock Source Select. Selects the baud rate clock." "0: System clock.,1: Alternate 7.3727MHz internal clock. Useful in.." newline bitfld.long 0x0 14. "BREAK,Break control bit. It causes a break condition to be transmitted to receiving UART." "0: Break characters are not generated.,1: Break characters are sent(all the bits are at.." newline bitfld.long 0x0 13. "NULL_MODEM,NULL Modem Support (RTS/CTS and TXD/RXD swap)." "0: Direct convention.,1: Null Modem Mode." newline bitfld.long 0x0 12. "FLOW_POL,RTS/CTS polarity." "0: RTS/CTS asserted is logic 0.,1: RTS/CTS asserted is logic 1." newline bitfld.long 0x0 11. "FLOW_CTRL,Enables/disables hardware flow control." "0: HW Flow Control disabled,1: HW Flow Control with RTS/CTS enabled" newline bitfld.long 0x0 10. "STOPBITS,Selects the number of stop bits that will be generated." "0: 1 stop bit.,1: 1.5 stop bits." newline bitfld.long 0x0 8.--9. "CHAR_SIZE,Selects UART character size." "0: 5 bits.,1: 6 bits.,2: 7 bits.,3: 8 bits." newline bitfld.long 0x0 7. "BITACC,If set bit accuracy is selected in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear frame accuracy is selected .." "0: Frame accuracy.,1: Bit accuracy." newline bitfld.long 0x0 6. "RX_FLUSH,Flushes the RX FIFO buffer." "0,1" newline bitfld.long 0x0 5. "TX_FLUSH,Flushes the TX FIFO buffer." "0,1" newline bitfld.long 0x0 4. "PARMD,Selects parity based on 1s or 0s count (when PARITY_EN=1)." "0: Parity calculation is based on number of 1s in..,1: Parity calculation is based on number of 0s in.." newline bitfld.long 0x0 2.--3. "PARITY,When PARITY_EN=1 selects odd even Mark or Space parity. Mark parity = always 1; Space parity = always 0." "0: Even parity selected.,1: Odd parity selected.,2: Mark parity selected.,3: Space parity selected." newline bitfld.long 0x0 1. "PARITY_EN,Enable/disable Parity bit (9th character)." "0: No Parity,1: Parity enabled as 9th bit" newline bitfld.long 0x0 0. "ENABLE,UART enabled to enable UART block it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled." "0: UART disabled. FIFOs are flushed. Clock is gated..,1: UART enabled." line.long 0x4 "THRESH_CTRL,Threshold Control register." hexmask.long.byte 0x4 16.--21. 1. "RTS_FIFO_THRESH,RTS threshold control. When the RX FIFO reaches this many bytes or higher the RTS output signal is deasserted informing the transmitting UART to stop sending data to this UART." newline hexmask.long.byte 0x4 8.--13. 1. "TX_FIFO_THRESH,TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher UARTn_INTFL.tx_fifo_level is set." newline hexmask.long.byte 0x4 0.--5. 1. "RX_FIFO_THRESH,RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher UARTn_INFTL.rx_fifo_level is set." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,Status Register." bitfld.long 0x0 24. "RX_TO,RX Timeout status." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "TX_FIFO_CNT,Indicates the number of bytes currently in the TX FIFO." newline hexmask.long.byte 0x0 8.--13. 1. "RX_FIFO_CNT,Indicates the number of bytes currently in the RX FIFO." newline bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state." "0,1" newline bitfld.long 0x0 6. "TX_EMPTY,Read-only flag indicating the TX FIFO state." "0,1" newline bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state." "0,1" newline bitfld.long 0x0 4. "RX_EMPTY,Read-only flag indicating the RX FIFO state." "0,1" newline bitfld.long 0x0 3. "BREAK,Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is the total time of Start bit + data bits + Parity + Stop bits)." "0,1" newline bitfld.long 0x0 2. "PARITY,9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3." "0,1" newline bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UARTreceiver status." "0,1" newline bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status." "0,1" group.long 0xC++0x1B line.long 0x0 "INT_EN,Interrupt Enable Register." bitfld.long 0x0 9. "LAST_BREAK,Enable for Last break character interrupt." "0,1" newline bitfld.long 0x0 8. "RX_TIMEOUT,Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO)." "0,1" newline bitfld.long 0x0 7. "BREAK,Enable for received BREAK character interrupt." "0,1" newline bitfld.long 0x0 6. "TX_FIFO_THRESH,Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field." "0,1" newline bitfld.long 0x0 5. "TX_FIFO_ALMOST_EMPTY,Enable for interrupt when TX FIFO has only one byte remaining." "0,1" newline bitfld.long 0x0 4. "RX_FIFO_THRESH,Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN,Enable for RX FIFO OVerrun interrupt." "0,1" newline bitfld.long 0x0 2. "CTS_CHANGE,Enable for CTS signal change interrupt." "0,1" newline bitfld.long 0x0 1. "RX_PARITY_ERROR,Enable for RX Parity Error interrupt." "0,1" newline bitfld.long 0x0 0. "RX_FRAME_ERROR,Enable for RX Frame Error Interrupt." "0,1" line.long 0x4 "INT_FL,Interrupt Status Flags." bitfld.long 0x4 9. "LAST_BREAK,FLAG for Last break character interrupt." "0,1" newline bitfld.long 0x4 8. "RX_TIMEOUT,FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO)." "0,1" newline bitfld.long 0x4 7. "BREAK,FLAG for received BREAK character interrupt." "0,1" newline bitfld.long 0x4 6. "TX_FIFO_THRESH,FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field." "0,1" newline bitfld.long 0x4 5. "TX_FIFO_ALMOST_EMPTY,FLAG for interrupt when TX FIFO has only one byte remaining." "0,1" newline bitfld.long 0x4 4. "RX_FIFO_THRESH,FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1" newline bitfld.long 0x4 3. "RX_OVERRUN,FLAG for RX FIFO Overrun interrupt." "0,1" newline bitfld.long 0x4 2. "CTS_CHANGE,FLAG for CTS signal change interrupt." "0,1" newline bitfld.long 0x4 1. "RX_PARITY_ERROR,FLAG for RX Parity Error interrupt." "0,1" newline bitfld.long 0x4 0. "RX_FRAME_ERROR,FLAG for RX Frame Error Interrupt." "0,1" line.long 0x8 "BAUD0,Baud rate register. Integer portion." bitfld.long 0x8 16.--17. "FACTOR,FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR." "0: Baud Factor 128,1: Baud Factor 64,2: Baud Factor 32,3: Baud Factor 16" newline hexmask.long.word 0x8 0.--11. 1. "IBAUD,Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency)." line.long 0xC "BAUD1,Baud rate register. Decimal Setting." hexmask.long.word 0xC 0.--11. 1. "DBAUD,Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128." line.long 0x10 "FIFO,FIFO Data buffer." hexmask.long.byte 0x10 0.--7. 1. "FIFO,Load/unload location for TX and RX FIFO buffers." line.long 0x14 "DMA,DMA Configuration." hexmask.long.byte 0x14 16.--21. 1. "RXDMA_LEVEL,RX threshold for DMA transmission." newline hexmask.long.byte 0x14 8.--13. 1. "TXDMA_LEVEL,TX threshold for DMA transmission." newline bitfld.long 0x14 1. "RXDMA_EN,RX DMA channel enable." "0: DMA is disabled,1: DMA is enabled" newline bitfld.long 0x14 0. "TDMA_EN,TX DMA channel enable." "0: DMA is disabled,1: DMA is enabled" line.long 0x18 "TX_FIFO,Transmit FIFO Status register." hexmask.long.byte 0x18 0.--6. 1. "DATA,Reading from this field returns the next character available at the output of the TX FIFO (if one is available otherwise 00h is returned)." tree.end tree "UART1" base ad:0x40043000 group.long 0x0++0x7 line.long 0x0 "CTRL,Control Register." hexmask.long.byte 0x0 16.--23. 1. "RX_TO,RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read." newline bitfld.long 0x0 15. "CLKSEL,Baud Rate Clock Source Select. Selects the baud rate clock." "0: System clock.,1: Alternate 7.3727MHz internal clock. Useful in.." newline bitfld.long 0x0 14. "BREAK,Break control bit. It causes a break condition to be transmitted to receiving UART." "0: Break characters are not generated.,1: Break characters are sent(all the bits are at.." newline bitfld.long 0x0 13. "NULL_MODEM,NULL Modem Support (RTS/CTS and TXD/RXD swap)." "0: Direct convention.,1: Null Modem Mode." newline bitfld.long 0x0 12. "FLOW_POL,RTS/CTS polarity." "0: RTS/CTS asserted is logic 0.,1: RTS/CTS asserted is logic 1." newline bitfld.long 0x0 11. "FLOW_CTRL,Enables/disables hardware flow control." "0: HW Flow Control disabled,1: HW Flow Control with RTS/CTS enabled" newline bitfld.long 0x0 10. "STOPBITS,Selects the number of stop bits that will be generated." "0: 1 stop bit.,1: 1.5 stop bits." newline bitfld.long 0x0 8.--9. "CHAR_SIZE,Selects UART character size." "0: 5 bits.,1: 6 bits.,2: 7 bits.,3: 8 bits." newline bitfld.long 0x0 7. "BITACC,If set bit accuracy is selected in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear frame accuracy is selected .." "0: Frame accuracy.,1: Bit accuracy." newline bitfld.long 0x0 6. "RX_FLUSH,Flushes the RX FIFO buffer." "0,1" newline bitfld.long 0x0 5. "TX_FLUSH,Flushes the TX FIFO buffer." "0,1" newline bitfld.long 0x0 4. "PARMD,Selects parity based on 1s or 0s count (when PARITY_EN=1)." "0: Parity calculation is based on number of 1s in..,1: Parity calculation is based on number of 0s in.." newline bitfld.long 0x0 2.--3. "PARITY,When PARITY_EN=1 selects odd even Mark or Space parity. Mark parity = always 1; Space parity = always 0." "0: Even parity selected.,1: Odd parity selected.,2: Mark parity selected.,3: Space parity selected." newline bitfld.long 0x0 1. "PARITY_EN,Enable/disable Parity bit (9th character)." "0: No Parity,1: Parity enabled as 9th bit" newline bitfld.long 0x0 0. "ENABLE,UART enabled to enable UART block it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled." "0: UART disabled. FIFOs are flushed. Clock is gated..,1: UART enabled." line.long 0x4 "THRESH_CTRL,Threshold Control register." hexmask.long.byte 0x4 16.--21. 1. "RTS_FIFO_THRESH,RTS threshold control. When the RX FIFO reaches this many bytes or higher the RTS output signal is deasserted informing the transmitting UART to stop sending data to this UART." newline hexmask.long.byte 0x4 8.--13. 1. "TX_FIFO_THRESH,TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher UARTn_INTFL.tx_fifo_level is set." newline hexmask.long.byte 0x4 0.--5. 1. "RX_FIFO_THRESH,RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher UARTn_INFTL.rx_fifo_level is set." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,Status Register." bitfld.long 0x0 24. "RX_TO,RX Timeout status." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "TX_FIFO_CNT,Indicates the number of bytes currently in the TX FIFO." newline hexmask.long.byte 0x0 8.--13. 1. "RX_FIFO_CNT,Indicates the number of bytes currently in the RX FIFO." newline bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state." "0,1" newline bitfld.long 0x0 6. "TX_EMPTY,Read-only flag indicating the TX FIFO state." "0,1" newline bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state." "0,1" newline bitfld.long 0x0 4. "RX_EMPTY,Read-only flag indicating the RX FIFO state." "0,1" newline bitfld.long 0x0 3. "BREAK,Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is the total time of Start bit + data bits + Parity + Stop bits)." "0,1" newline bitfld.long 0x0 2. "PARITY,9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3." "0,1" newline bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UARTreceiver status." "0,1" newline bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status." "0,1" group.long 0xC++0x1B line.long 0x0 "INT_EN,Interrupt Enable Register." bitfld.long 0x0 9. "LAST_BREAK,Enable for Last break character interrupt." "0,1" newline bitfld.long 0x0 8. "RX_TIMEOUT,Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO)." "0,1" newline bitfld.long 0x0 7. "BREAK,Enable for received BREAK character interrupt." "0,1" newline bitfld.long 0x0 6. "TX_FIFO_THRESH,Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field." "0,1" newline bitfld.long 0x0 5. "TX_FIFO_ALMOST_EMPTY,Enable for interrupt when TX FIFO has only one byte remaining." "0,1" newline bitfld.long 0x0 4. "RX_FIFO_THRESH,Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN,Enable for RX FIFO OVerrun interrupt." "0,1" newline bitfld.long 0x0 2. "CTS_CHANGE,Enable for CTS signal change interrupt." "0,1" newline bitfld.long 0x0 1. "RX_PARITY_ERROR,Enable for RX Parity Error interrupt." "0,1" newline bitfld.long 0x0 0. "RX_FRAME_ERROR,Enable for RX Frame Error Interrupt." "0,1" line.long 0x4 "INT_FL,Interrupt Status Flags." bitfld.long 0x4 9. "LAST_BREAK,FLAG for Last break character interrupt." "0,1" newline bitfld.long 0x4 8. "RX_TIMEOUT,FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO)." "0,1" newline bitfld.long 0x4 7. "BREAK,FLAG for received BREAK character interrupt." "0,1" newline bitfld.long 0x4 6. "TX_FIFO_THRESH,FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field." "0,1" newline bitfld.long 0x4 5. "TX_FIFO_ALMOST_EMPTY,FLAG for interrupt when TX FIFO has only one byte remaining." "0,1" newline bitfld.long 0x4 4. "RX_FIFO_THRESH,FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1" newline bitfld.long 0x4 3. "RX_OVERRUN,FLAG for RX FIFO Overrun interrupt." "0,1" newline bitfld.long 0x4 2. "CTS_CHANGE,FLAG for CTS signal change interrupt." "0,1" newline bitfld.long 0x4 1. "RX_PARITY_ERROR,FLAG for RX Parity Error interrupt." "0,1" newline bitfld.long 0x4 0. "RX_FRAME_ERROR,FLAG for RX Frame Error Interrupt." "0,1" line.long 0x8 "BAUD0,Baud rate register. Integer portion." bitfld.long 0x8 16.--17. "FACTOR,FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR." "0: Baud Factor 128,1: Baud Factor 64,2: Baud Factor 32,3: Baud Factor 16" newline hexmask.long.word 0x8 0.--11. 1. "IBAUD,Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency)." line.long 0xC "BAUD1,Baud rate register. Decimal Setting." hexmask.long.word 0xC 0.--11. 1. "DBAUD,Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128." line.long 0x10 "FIFO,FIFO Data buffer." hexmask.long.byte 0x10 0.--7. 1. "FIFO,Load/unload location for TX and RX FIFO buffers." line.long 0x14 "DMA,DMA Configuration." hexmask.long.byte 0x14 16.--21. 1. "RXDMA_LEVEL,RX threshold for DMA transmission." newline hexmask.long.byte 0x14 8.--13. 1. "TXDMA_LEVEL,TX threshold for DMA transmission." newline bitfld.long 0x14 1. "RXDMA_EN,RX DMA channel enable." "0: DMA is disabled,1: DMA is enabled" newline bitfld.long 0x14 0. "TDMA_EN,TX DMA channel enable." "0: DMA is disabled,1: DMA is enabled" line.long 0x18 "TX_FIFO,Transmit FIFO Status register." hexmask.long.byte 0x18 0.--6. 1. "DATA,Reading from this field returns the next character available at the output of the TX FIFO (if one is available otherwise 00h is returned)." tree.end tree "UART2" base ad:0x40044000 group.long 0x0++0x7 line.long 0x0 "CTRL,Control Register." hexmask.long.byte 0x0 16.--23. 1. "RX_TO,RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read." newline bitfld.long 0x0 15. "CLKSEL,Baud Rate Clock Source Select. Selects the baud rate clock." "0: System clock.,1: Alternate 7.3727MHz internal clock. Useful in.." newline bitfld.long 0x0 14. "BREAK,Break control bit. It causes a break condition to be transmitted to receiving UART." "0: Break characters are not generated.,1: Break characters are sent(all the bits are at.." newline bitfld.long 0x0 13. "NULL_MODEM,NULL Modem Support (RTS/CTS and TXD/RXD swap)." "0: Direct convention.,1: Null Modem Mode." newline bitfld.long 0x0 12. "FLOW_POL,RTS/CTS polarity." "0: RTS/CTS asserted is logic 0.,1: RTS/CTS asserted is logic 1." newline bitfld.long 0x0 11. "FLOW_CTRL,Enables/disables hardware flow control." "0: HW Flow Control disabled,1: HW Flow Control with RTS/CTS enabled" newline bitfld.long 0x0 10. "STOPBITS,Selects the number of stop bits that will be generated." "0: 1 stop bit.,1: 1.5 stop bits." newline bitfld.long 0x0 8.--9. "CHAR_SIZE,Selects UART character size." "0: 5 bits.,1: 6 bits.,2: 7 bits.,3: 8 bits." newline bitfld.long 0x0 7. "BITACC,If set bit accuracy is selected in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear frame accuracy is selected .." "0: Frame accuracy.,1: Bit accuracy." newline bitfld.long 0x0 6. "RX_FLUSH,Flushes the RX FIFO buffer." "0,1" newline bitfld.long 0x0 5. "TX_FLUSH,Flushes the TX FIFO buffer." "0,1" newline bitfld.long 0x0 4. "PARMD,Selects parity based on 1s or 0s count (when PARITY_EN=1)." "0: Parity calculation is based on number of 1s in..,1: Parity calculation is based on number of 0s in.." newline bitfld.long 0x0 2.--3. "PARITY,When PARITY_EN=1 selects odd even Mark or Space parity. Mark parity = always 1; Space parity = always 0." "0: Even parity selected.,1: Odd parity selected.,2: Mark parity selected.,3: Space parity selected." newline bitfld.long 0x0 1. "PARITY_EN,Enable/disable Parity bit (9th character)." "0: No Parity,1: Parity enabled as 9th bit" newline bitfld.long 0x0 0. "ENABLE,UART enabled to enable UART block it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled." "0: UART disabled. FIFOs are flushed. Clock is gated..,1: UART enabled." line.long 0x4 "THRESH_CTRL,Threshold Control register." hexmask.long.byte 0x4 16.--21. 1. "RTS_FIFO_THRESH,RTS threshold control. When the RX FIFO reaches this many bytes or higher the RTS output signal is deasserted informing the transmitting UART to stop sending data to this UART." newline hexmask.long.byte 0x4 8.--13. 1. "TX_FIFO_THRESH,TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher UARTn_INTFL.tx_fifo_level is set." newline hexmask.long.byte 0x4 0.--5. 1. "RX_FIFO_THRESH,RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher UARTn_INFTL.rx_fifo_level is set." rgroup.long 0x8++0x3 line.long 0x0 "STATUS,Status Register." bitfld.long 0x0 24. "RX_TO,RX Timeout status." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "TX_FIFO_CNT,Indicates the number of bytes currently in the TX FIFO." newline hexmask.long.byte 0x0 8.--13. 1. "RX_FIFO_CNT,Indicates the number of bytes currently in the RX FIFO." newline bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state." "0,1" newline bitfld.long 0x0 6. "TX_EMPTY,Read-only flag indicating the TX FIFO state." "0,1" newline bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state." "0,1" newline bitfld.long 0x0 4. "RX_EMPTY,Read-only flag indicating the RX FIFO state." "0,1" newline bitfld.long 0x0 3. "BREAK,Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is the total time of Start bit + data bits + Parity + Stop bits)." "0,1" newline bitfld.long 0x0 2. "PARITY,9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3." "0,1" newline bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UARTreceiver status." "0,1" newline bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status." "0,1" group.long 0xC++0x1B line.long 0x0 "INT_EN,Interrupt Enable Register." bitfld.long 0x0 9. "LAST_BREAK,Enable for Last break character interrupt." "0,1" newline bitfld.long 0x0 8. "RX_TIMEOUT,Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO)." "0,1" newline bitfld.long 0x0 7. "BREAK,Enable for received BREAK character interrupt." "0,1" newline bitfld.long 0x0 6. "TX_FIFO_THRESH,Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field." "0,1" newline bitfld.long 0x0 5. "TX_FIFO_ALMOST_EMPTY,Enable for interrupt when TX FIFO has only one byte remaining." "0,1" newline bitfld.long 0x0 4. "RX_FIFO_THRESH,Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1" newline bitfld.long 0x0 3. "RX_OVERRUN,Enable for RX FIFO OVerrun interrupt." "0,1" newline bitfld.long 0x0 2. "CTS_CHANGE,Enable for CTS signal change interrupt." "0,1" newline bitfld.long 0x0 1. "RX_PARITY_ERROR,Enable for RX Parity Error interrupt." "0,1" newline bitfld.long 0x0 0. "RX_FRAME_ERROR,Enable for RX Frame Error Interrupt." "0,1" line.long 0x4 "INT_FL,Interrupt Status Flags." bitfld.long 0x4 9. "LAST_BREAK,FLAG for Last break character interrupt." "0,1" newline bitfld.long 0x4 8. "RX_TIMEOUT,FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO)." "0,1" newline bitfld.long 0x4 7. "BREAK,FLAG for received BREAK character interrupt." "0,1" newline bitfld.long 0x4 6. "TX_FIFO_THRESH,FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field." "0,1" newline bitfld.long 0x4 5. "TX_FIFO_ALMOST_EMPTY,FLAG for interrupt when TX FIFO has only one byte remaining." "0,1" newline bitfld.long 0x4 4. "RX_FIFO_THRESH,FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1" newline bitfld.long 0x4 3. "RX_OVERRUN,FLAG for RX FIFO Overrun interrupt." "0,1" newline bitfld.long 0x4 2. "CTS_CHANGE,FLAG for CTS signal change interrupt." "0,1" newline bitfld.long 0x4 1. "RX_PARITY_ERROR,FLAG for RX Parity Error interrupt." "0,1" newline bitfld.long 0x4 0. "RX_FRAME_ERROR,FLAG for RX Frame Error Interrupt." "0,1" line.long 0x8 "BAUD0,Baud rate register. Integer portion." bitfld.long 0x8 16.--17. "FACTOR,FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR." "0: Baud Factor 128,1: Baud Factor 64,2: Baud Factor 32,3: Baud Factor 16" newline hexmask.long.word 0x8 0.--11. 1. "IBAUD,Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency)." line.long 0xC "BAUD1,Baud rate register. Decimal Setting." hexmask.long.word 0xC 0.--11. 1. "DBAUD,Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128." line.long 0x10 "FIFO,FIFO Data buffer." hexmask.long.byte 0x10 0.--7. 1. "FIFO,Load/unload location for TX and RX FIFO buffers." line.long 0x14 "DMA,DMA Configuration." hexmask.long.byte 0x14 16.--21. 1. "RXDMA_LEVEL,RX threshold for DMA transmission." newline hexmask.long.byte 0x14 8.--13. 1. "TXDMA_LEVEL,TX threshold for DMA transmission." newline bitfld.long 0x14 1. "RXDMA_EN,RX DMA channel enable." "0: DMA is disabled,1: DMA is enabled" newline bitfld.long 0x14 0. "TDMA_EN,TX DMA channel enable." "0: DMA is disabled,1: DMA is enabled" line.long 0x18 "TX_FIFO,Transmit FIFO Status register." hexmask.long.byte 0x18 0.--6. 1. "DATA,Reading from this field returns the next character available at the output of the TX FIFO (if one is available otherwise 00h is returned)." tree.end tree.end tree "USBHS (USB 2.0 High-speed Controller.)" base ad:0x400B1000 group.byte 0x0++0x1 line.byte 0x0 "FADDR,Function address register." rbitfld.byte 0x0 7. "UPDATE,Set when ADDR is written cleared when new address takes effect." "0,1" hexmask.byte 0x0 0.--6. 1. "ADDR,Function address for this controller." line.byte 0x1 "POWER,Power management register." bitfld.byte 0x1 7. "ISO_UPDATE,Wait for SOF during Isochronous xfers." "0,1" bitfld.byte 0x1 6. "SOFTCONN,Softconn." "0,1" newline bitfld.byte 0x1 5. "HS_ENABLE,High-speed mode enable." "0,1" rbitfld.byte 0x1 4. "HS_MODE,High-speed mode detected." "0,1" newline rbitfld.byte 0x1 3. "RESET,Bus reset detected." "0,1" bitfld.byte 0x1 2. "RESUME,Generate resume signaling." "0,1" newline rbitfld.byte 0x1 1. "SUSPEND,Suspend mode detected." "0,1" bitfld.byte 0x1 0. "EN_SUSPENDM,Enable SUSPENDM signal." "0,1" rgroup.word 0x2++0x3 line.word 0x0 "INTRIN,Interrupt register for EP0 and IN EP1-15." bitfld.word 0x0 15. "EP15_IN_INT,Endpoint 15 interrupt." "0,1" bitfld.word 0x0 14. "EP14_IN_INT,Endpoint 14 interrupt." "0,1" newline bitfld.word 0x0 13. "EP13_IN_INT,Endpoint 13 interrupt." "0,1" bitfld.word 0x0 12. "EP12_IN_INT,Endpoint 12 interrupt." "0,1" newline bitfld.word 0x0 11. "EP11_IN_INT,Endpoint 11 interrupt." "0,1" bitfld.word 0x0 10. "EP10_IN_INT,Endpoint 10 interrupt." "0,1" newline bitfld.word 0x0 9. "EP9_IN_INT,Endpoint 9 interrupt." "0,1" bitfld.word 0x0 8. "EP8_IN_INT,Endpoint 8 interrupt." "0,1" newline bitfld.word 0x0 7. "EP7_IN_INT,Endpoint 7 interrupt." "0,1" bitfld.word 0x0 6. "EP6_IN_INT,Endpoint 6 interrupt." "0,1" newline bitfld.word 0x0 5. "EP5_IN_INT,Endpoint 5 interrupt." "0,1" bitfld.word 0x0 4. "EP4_IN_INT,Endpoint 4 interrupt." "0,1" newline bitfld.word 0x0 3. "EP3_IN_INT,Endpoint 3 interrupt." "0,1" bitfld.word 0x0 2. "EP2_IN_INT,Endpoint 2 interrupt." "0,1" newline bitfld.word 0x0 1. "EP1_IN_INT,Endpoint 1 interrupt." "0,1" bitfld.word 0x0 0. "EP0_IN_INT,Endpoint 0 interrupt." "0,1" line.word 0x2 "INTROUT,Interrupt register for OUT EP 1-15." bitfld.word 0x2 15. "EP15_OUT_INT,Endpoint 15 interrupt." "0,1" bitfld.word 0x2 14. "EP14_OUT_INT,Endpoint 14 interrupt." "0,1" newline bitfld.word 0x2 13. "EP13_OUT_INT,Endpoint 13 interrupt." "0,1" bitfld.word 0x2 12. "EP12_OUT_INT,Endpoint 12 interrupt." "0,1" newline bitfld.word 0x2 11. "EP11_OUT_INT,Endpoint 11 interrupt." "0,1" bitfld.word 0x2 10. "EP10_OUT_INT,Endpoint 10 interrupt." "0,1" newline bitfld.word 0x2 9. "EP9_OUT_INT,Endpoint 9 interrupt." "0,1" bitfld.word 0x2 8. "EP8_OUT_INT,Endpoint 8 interrupt." "0,1" newline bitfld.word 0x2 7. "EP7_OUT_INT,Endpoint 7 interrupt." "0,1" bitfld.word 0x2 6. "EP6_OUT_INT,Endpoint 6 interrupt." "0,1" newline bitfld.word 0x2 5. "EP5_OUT_INT,Endpoint 5 interrupt." "0,1" bitfld.word 0x2 4. "EP4_OUT_INT,Endpoint 4 interrupt." "0,1" newline bitfld.word 0x2 3. "EP3_OUT_INT,Endpoint 3 interrupt." "0,1" bitfld.word 0x2 2. "EP2_OUT_INT,Endpoint 2 interrupt." "0,1" newline bitfld.word 0x2 1. "EP1_OUT_INT,Endpoint 1 interrupt." "0,1" group.word 0x6++0x3 line.word 0x0 "INTRINEN,Interrupt enable for EP 0 and IN EP 1-15." bitfld.word 0x0 15. "EP15_IN_INT_EN,Endpoint 15 interrupt enable." "0,1" bitfld.word 0x0 14. "EP14_IN_INT_EN,Endpoint 14 interrupt enable." "0,1" newline bitfld.word 0x0 13. "EP13_IN_INT_EN,Endpoint 13 interrupt enable." "0,1" bitfld.word 0x0 12. "EP12_IN_INT_EN,Endpoint 12 interrupt enable." "0,1" newline bitfld.word 0x0 11. "EP11_IN_INT_EN,Endpoint 11 interrupt enable." "0,1" bitfld.word 0x0 10. "EP10_IN_INT_EN,Endpoint 10 interrupt enable." "0,1" newline bitfld.word 0x0 9. "EP9_IN_INT_EN,Endpoint 9 interrupt enable." "0,1" bitfld.word 0x0 8. "EP8_IN_INT_EN,Endpoint 8 interrupt enable." "0,1" newline bitfld.word 0x0 7. "EP7_IN_INT_EN,Endpoint 7 interrupt enable." "0,1" bitfld.word 0x0 6. "EP6_IN_INT_EN,Endpoint 6 interrupt enable." "0,1" newline bitfld.word 0x0 5. "EP5_IN_INT_EN,Endpoint 5 interrupt enable." "0,1" bitfld.word 0x0 4. "EP4_IN_INT_EN,Endpoint 4 interrupt enable." "0,1" newline bitfld.word 0x0 3. "EP3_IN_INT_EN,Endpoint 3 interrupt enable." "0,1" bitfld.word 0x0 2. "EP2_IN_INT_EN,Endpoint 2 interrupt enable." "0,1" newline bitfld.word 0x0 1. "EP1_IN_INT_EN,Endpoint 1 interrupt enable." "0,1" bitfld.word 0x0 0. "EP0_INT_EN,Endpoint 0 interrupt enable." "0,1" line.word 0x2 "INTROUTEN,Interrupt enable for OUT EP 1-15." bitfld.word 0x2 15. "EP15_OUT_INT_EN,Endpoint 15 interrupt." "0,1" bitfld.word 0x2 14. "EP14_OUT_INT_EN,Endpoint 14 interrupt." "0,1" newline bitfld.word 0x2 13. "EP13_OUT_INT_EN,Endpoint 13 interrupt." "0,1" bitfld.word 0x2 12. "EP12_OUT_INT_EN,Endpoint 12 interrupt." "0,1" newline bitfld.word 0x2 11. "EP11_OUT_INT_EN,Endpoint 11 interrupt." "0,1" bitfld.word 0x2 10. "EP10_OUT_INT_EN,Endpoint 10 interrupt." "0,1" newline bitfld.word 0x2 9. "EP9_OUT_INT_EN,Endpoint 9 interrupt." "0,1" bitfld.word 0x2 8. "EP8_OUT_INT_EN,Endpoint 8 interrupt." "0,1" newline bitfld.word 0x2 7. "EP7_OUT_INT_EN,Endpoint 7 interrupt." "0,1" bitfld.word 0x2 6. "EP6_OUT_INT_EN,Endpoint 6 interrupt." "0,1" newline bitfld.word 0x2 5. "EP5_OUT_INT_EN,Endpoint 5 interrupt." "0,1" bitfld.word 0x2 4. "EP4_OUT_INT_EN,Endpoint 4 interrupt." "0,1" newline bitfld.word 0x2 3. "EP3_OUT_INT_EN,Endpoint 3 interrupt." "0,1" bitfld.word 0x2 2. "EP2_OUT_INT_EN,Endpoint 2 interrupt." "0,1" newline bitfld.word 0x2 1. "EP1_OUT_INT_EN,Endpoint 1 interrupt." "0,1" rgroup.byte 0xA++0x0 line.byte 0x0 "INTRUSB,Interrupt register for common USB interrupts." bitfld.byte 0x0 3. "SOF_INT,Start of Frame." "0,1" bitfld.byte 0x0 2. "RESET_INT,Bus reset detected." "0,1" newline bitfld.byte 0x0 1. "RESUME_INT,Resume detected." "0,1" bitfld.byte 0x0 0. "SUSPEND_INT,Suspend detected." "0,1" group.byte 0xB++0x0 line.byte 0x0 "INTRUSBEN,Interrupt enable for common USB interrupts." bitfld.byte 0x0 3. "SOF_INT_EN,Start of Frame." "0,1" bitfld.byte 0x0 2. "RESET_INT_EN,Bus reset detected." "0,1" newline bitfld.byte 0x0 1. "RESUME_INT_EN,Resume detected." "0,1" bitfld.byte 0x0 0. "SUSPEND_INT_EN,Suspend detected." "0,1" rgroup.word 0xC++0x1 line.word 0x0 "FRAME,Frame number." hexmask.word 0x0 0.--10. 1. "FRAMENUM,Read the last received frame number that is the 11-bit frame number received in the SOF packet." group.byte 0xE++0x1 line.byte 0x0 "INDEX,Index for banked registers." hexmask.byte 0x0 0.--3. 1. "INDEX,Index Register Access Selector." line.byte 0x1 "TESTMODE,USB 2.0 test mode enable register." bitfld.byte 0x1 5. "FORCE_FS,Force USB to Full-speed after reset." "0,1" bitfld.byte 0x1 4. "FORCE_HS,Force USB to High-speed after reset." "0,1" newline bitfld.byte 0x1 3. "TEST_PKT,Transmit fixed test packet." "0,1" bitfld.byte 0x1 2. "TEST_K,Force USB to continuous K state." "0,1" newline bitfld.byte 0x1 1. "TEST_J,Force USB to continuous J state." "0,1" bitfld.byte 0x1 0. "TEST_SE0_NAK,Respond to any valid IN token with NAK." "0,1" group.word 0x10++0x1 line.word 0x0 "INMAXP,Maximum packet size for INx endpoint (x == INDEX)." hexmask.word.byte 0x0 11.--15. 1. "NUMPACKMINUS1,Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk.." hexmask.word 0x0 0.--10. 1. "MAXPACKETSIZE,Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes that is transmitted for each microframe. The maximum value is 1024 subject to the limitations of the endpoint type set in USB 2.0 Specification Chapter 9" group.byte 0x12++0x0 line.byte 0x0 "CSR0,Control status register for EP 0 (when INDEX == 0)." bitfld.byte 0x0 7. "SERV_SETUP_END,Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set" "0,1" bitfld.byte 0x0 6. "SERV_OUTPKTRDY,Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set." "0,1" newline bitfld.byte 0x0 5. "SEND_STALL,Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set." "0,1" rbitfld.byte 0x0 4. "SETUP_END,Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear." "0,1" newline bitfld.byte 0x0 3. "DATA_END,Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after.." "0,1" bitfld.byte 0x0 2. "SENT_STALL,Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear." "0,1" newline bitfld.byte 0x0 1. "INPKTRDY,EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared." "?,1: Write a 1 after writing a data packet to the IN.." rbitfld.byte 0x0 0. "OUTPKTRDY,EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO." "0,1" group.byte 0x12++0x1 line.byte 0x0 "INCSRL,Control status lower register for INx endpoint (x == INDEX)." bitfld.byte 0x0 7. "INCOMPTX,Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from.." "0,1" bitfld.byte 0x0 6. "CLRDATATOG,Write 1 to clear IN endpoint data-toggle to 0." "0,1" newline bitfld.byte 0x0 5. "SENTSTALL,Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted at which time the IN FIFO is flushed and inpktrdy is cleared. Write 0 to clear." "0,1" rbitfld.byte 0x0 4. "SENDSTALL,Send STALL Handshake." "0: Terminate STALL handhsake,1: Respond to an IN token with a STALL handshake" newline bitfld.byte 0x0 3. "FLUSHFIFO,Flush Next Packet from IN FIFO. Write 1 to clear" "0,1" bitfld.byte 0x0 2. "UNDERRUN,Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear" "0,1" newline bitfld.byte 0x0 1. "FIFONOTEMPTY,Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear." "0,1" rbitfld.byte 0x0 0. "INPKTRDY,IN Packet Ready. Write a 1 to clear" "0,1" line.byte 0x1 "INCSRU,Control status upper register for INx endpoint (x == INDEX)." bitfld.byte 0x1 7. "AUTOSET,Auto Set inpktrdy." "0: USBHS_INCSRL_inpktrdy must be set by firmware.,1: USBHS_INCSRL_inpktrdy is automatically set." bitfld.byte 0x1 6. "ISO,Isochronous Transfer Enable" "0: Enable IN Bulk and IN interrupt transfers.,1: Enable IN Isochronous transfers." newline bitfld.byte 0x1 5. "MODE,Endpoint Direction Mode." "0: Endpoint direction is OUT.,1: Endpoint direction is IN." bitfld.byte 0x1 4. "DMAREQEN,DMA Request Enable" "0: Disable DMA for this IN endpoint.,1: Enable DMA for this IN endpoint." newline bitfld.byte 0x1 3. "FRCDATATOG,Force In Data - Toggle" "0: Toggle data-toglge only when an ACK is received.,1: Toggle data-toggle regardless of ACK." bitfld.byte 0x1 2. "DMAREQMODE,DMA Request Mode Enable" "0: Enable DMA Request Mode 0.,1: Enable DMA Request Mode 1." newline bitfld.byte 0x1 1. "DPKTBUFDIS,Double Packet Buffering Disable" "0: Enable Double packet buffering.,1: Disable Double Packet Buffering." group.word 0x14++0x1 line.word 0x0 "OUTMAXP,Maximum packet size for OUTx endpoint (x == INDEX)." hexmask.word.byte 0x0 11.--15. 1. "NUMPACKMINUS1,Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize." hexmask.word 0x0 0.--10. 1. "MAXPACKETSIZE,Maximum Packet in a Single Transaction. This is the maximum packet size in bytes that is transmitted for each microframe. The maximum value is 1024 subject to the limitations for the endpoint type set in USB2.0 spesification chapter 9." group.byte 0x16++0x1 line.byte 0x0 "OUTCSRL,Control status lower register for OUTx endpoint (x == INDEX)." bitfld.byte 0x0 7. "CLRDATATOG" "0,1" bitfld.byte 0x0 6. "SENTSTALL" "0,1" newline bitfld.byte 0x0 5. "SENDSTALL" "0,1" bitfld.byte 0x0 4. "FLUSHFIFO" "0,1" newline rbitfld.byte 0x0 3. "DATAERROR" "0,1" bitfld.byte 0x0 2. "OVERRUN" "0,1" newline rbitfld.byte 0x0 1. "FIFOFULL" "0,1" bitfld.byte 0x0 0. "OUTPKTRDY" "0,1" line.byte 0x1 "OUTCSRU,Control status upper register for OUTx endpoint (x == INDEX)." bitfld.byte 0x1 7. "AUTOCLEAR" "0,1" bitfld.byte 0x1 6. "ISO" "0,1" newline bitfld.byte 0x1 5. "DMAREQEN" "0,1" bitfld.byte 0x1 4. "DISNYET" "0,1" newline bitfld.byte 0x1 3. "DMAREQMODE" "0,1" bitfld.byte 0x1 1. "DPKTBUFDIS" "0,1" newline rbitfld.byte 0x1 0. "INCOMPRX" "0,1" rgroup.word 0x18++0x1 line.word 0x0 "COUNT0,Number of received bytes in EP 0 FIFO (INDEX == 0)." hexmask.word.byte 0x0 0.--6. 1. "COUNT0,Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1" rgroup.word 0x18++0x1 line.word 0x0 "OUTCOUNT,Number of received bytes in OUT EPx FIFO (x == INDEX)." hexmask.word 0x0 0.--12. 1. "OUTCOUNT,Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO." group.long 0x20++0x3F line.long 0x0 "FIFO0,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x0 0.--31. 1. "USBHS_FIFO0,USBHS Endpoint FIFO Read/Write Register." line.long 0x4 "FIFO1,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x4 0.--31. 1. "USBHS_FIFO1,USBHS Endpoint FIFO Read/Write Register." line.long 0x8 "FIFO2,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x8 0.--31. 1. "USBHS_FIFO2,USBHS Endpoint FIFO Read/Write Register." line.long 0xC "FIFO3,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0xC 0.--31. 1. "USBHS_FIFO3,USBHS Endpoint FIFO Read/Write Register." line.long 0x10 "FIFO4,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x10 0.--31. 1. "USBHS_FIFO4,USBHS Endpoint FIFO Read/Write Register." line.long 0x14 "FIFO5,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x14 0.--31. 1. "USBHS_FIFO5,USBHS Endpoint FIFO Read/Write Register." line.long 0x18 "FIFO6,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x18 0.--31. 1. "USBHS_FIFO6,USBHS Endpoint FIFO Read/Write Register." line.long 0x1C "FIFO7,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x1C 0.--31. 1. "USBHS_FIFO7,USBHS Endpoint FIFO Read/Write Register." line.long 0x20 "FIFO8,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x20 0.--31. 1. "USBHS_FIFO8,USBHS Endpoint FIFO Read/Write Register." line.long 0x24 "FIFO9,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x24 0.--31. 1. "USBHS_FIFO9,USBHS Endpoint FIFO Read/Write Register." line.long 0x28 "FIFO10,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x28 0.--31. 1. "USBHS_FIFO10,USBHS Endpoint FIFO Read/Write Register." line.long 0x2C "FIFO11,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x2C 0.--31. 1. "USBHS_FIFO11,USBHS Endpoint FIFO Read/Write Register." line.long 0x30 "FIFO12,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x30 0.--31. 1. "USBHS_FIFO12,USBHS Endpoint FIFO Read/Write Register." line.long 0x34 "FIFO13,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x34 0.--31. 1. "USBHS_FIFO13,USBHS Endpoint FIFO Read/Write Register." line.long 0x38 "FIFO14,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x38 0.--31. 1. "USBHS_FIFO14,USBHS Endpoint FIFO Read/Write Register." line.long 0x3C "FIFO15,Read for OUT data FIFO. write for IN data FIFO." hexmask.long 0x3C 0.--31. 1. "USBHS_FIFO15,USBHS Endpoint FIFO Read/Write Register." group.word 0x6C++0x1 line.word 0x0 "HWVERS,HWVERS" hexmask.word 0x0 0.--15. 1. "USBHS_HWVERS,USBHS Register." rgroup.byte 0x78++0x1 line.byte 0x0 "EPINFO,Endpoint hardware information." hexmask.byte 0x0 4.--7. 1. "OUTENDPOINTS" hexmask.byte 0x0 0.--3. 1. "INTENDPOINTS" line.byte 0x1 "RAMINFO,RAM width and DMA hardware information." hexmask.byte 0x1 4.--7. 1. "DMACHANS" hexmask.byte 0x1 0.--3. 1. "RAMBITS" group.byte 0x7A++0x1 line.byte 0x0 "SOFTRESET,Software reset register." bitfld.byte 0x0 1. "RSTXS" "0,1" bitfld.byte 0x0 0. "RSTS" "0,1" line.byte 0x1 "EARLYDMA,DMA timing control register." bitfld.byte 0x1 1. "EDMAIN" "0,1" bitfld.byte 0x1 0. "EDMAOUT" "0,1" group.word 0x80++0x3 line.word 0x0 "CTUCH,Chirp timeout timer setting." hexmask.word 0x0 0.--15. 1. "C_T_UCH,HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host." line.word 0x2 "CTHSRTN,Sets delay between HS resume to UTM normal operating mode." hexmask.word 0x2 0.--15. 1. "C_T_HSTRN,High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends the when the USBHS resumes normal operation." group.long 0x410++0xB line.long 0x0 "M31_PHY_PONRST,M31_PHY_PONRST" line.long 0x4 "M31_PHY_NONCRY_RSTB,M31_PHY_NONCRY_RSTB" line.long 0x8 "M31_PHY_NONCRY_EN,M31_PHY_NONCRY_EN" group.long 0x430++0x3 line.long 0x0 "M31_PHY_PLL_EN,M31_PHY_PLL_EN" group.long 0x43C++0x3 line.long 0x0 "M31_PHY_OSCOUTEN,M31_PHY_OSCOUTEN" group.long 0x448++0x7 line.long 0x0 "M31_PHY_CORECLKIN,M31_PHY_CORECLKIN" line.long 0x4 "M31_PHY_XTLSEL,M31_PHY_XTLSEL" group.long 0x45C++0x3 line.long 0x0 "M31_PHY_OUTCLKSEL,M31_PHY_OUTCLKSEL" group.long 0x498++0xF line.long 0x0 "MXM_INT,USB Added Maxim Interrupt Flag Register." bitfld.long 0x0 1. "NOVBUS,NOVBUS" "0,1" bitfld.long 0x0 0. "VBUS,VBUS" "0,1" line.long 0x4 "MXM_INT_EN,USB Added Maxim Interrupt Enable Register." bitfld.long 0x4 1. "NOVBUS,NOVBUS" "0,1" bitfld.long 0x4 0. "VBUS,VBUS" "0,1" line.long 0x8 "MXM_SUSPEND,USB Added Maxim Suspend Register." bitfld.long 0x8 0. "SEL,Suspend register" "0,1" line.long 0xC "MXM_REG_A4,USB Added Maxim Power Status Register" bitfld.long 0xC 1. "DMA_INT,DMA_INT" "0,1" bitfld.long 0xC 0. "VRST_VDDB_N_A,VRST_VDDB_N_A" "0,1" tree.end tree "WDT (Watchdog Timer)" base ad:0x0 tree "WDT0" base ad:0x40003000 group.long 0x0++0x3 line.long 0x0 "CTRL,Watchdog Timer Control Register." bitfld.long 0x0 31. "RST_FLAG,Watchdog Timer Reset Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 11. "RST_EN,Watchdog Timer Reset Enable." "0: Disable.,1: Enable." bitfld.long 0x0 10. "INT_EN,Watchdog Timer Interrupt Enable." "0: Disable.,1: Enable." eventfld.long 0x0 9. "INT_FLAG,Watchdog Timer Interrupt Flag." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 8. "WDT_EN,Watchdog Timer Enable." "0: Disable.,1: Enable." newline hexmask.long.byte 0x0 4.--7. 1. "RST_PERIOD,Watchdog Reset Period. The watchdog timer will assert a reset if enabled if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset." hexmask.long.byte 0x0 0.--3. 1. "INT_PERIOD,Watchdog Interrupt Period. The watchdog timer will assert an interrupt if enabled if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset." wgroup.long 0x4++0x3 line.long 0x0 "RST,Watchdog Timer Reset Register." hexmask.long.byte 0x0 0.--7. 1. "WDT_RST,Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset.." tree.end tree "WDT1" base ad:0x40003400 group.long 0x0++0x3 line.long 0x0 "CTRL,Watchdog Timer Control Register." bitfld.long 0x0 31. "RST_FLAG,Watchdog Timer Reset Flag." "0: The event has not occurred.,1: The event has occurred." bitfld.long 0x0 11. "RST_EN,Watchdog Timer Reset Enable." "0: Disable.,1: Enable." bitfld.long 0x0 10. "INT_EN,Watchdog Timer Interrupt Enable." "0: Disable.,1: Enable." eventfld.long 0x0 9. "INT_FLAG,Watchdog Timer Interrupt Flag." "0: No interrupt is pending.,1: An interrupt is pending." bitfld.long 0x0 8. "WDT_EN,Watchdog Timer Enable." "0: Disable.,1: Enable." newline hexmask.long.byte 0x0 4.--7. 1. "RST_PERIOD,Watchdog Reset Period. The watchdog timer will assert a reset if enabled if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset." hexmask.long.byte 0x0 0.--3. 1. "INT_PERIOD,Watchdog Interrupt Period. The watchdog timer will assert an interrupt if enabled if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset." wgroup.long 0x4++0x3 line.long 0x0 "RST,Watchdog Timer Reset Register." hexmask.long.byte 0x0 0.--7. 1. "WDT_RST,Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset.." tree.end tree.end newline AUTOINDENT.OFF