; -------------------------------------------------------------------------------- ; @Title: CEC17xx On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2025-02-03 KRZ ; @Manufacturer: MICROCHIP - Microchip Technology Inc. ; @Doc: Generated (TRACE32, build: 176288.), based on: ; CEC1702.svd (Ver. 0), CEC1712H.svd (Ver. 0), ; CEC1734_S0_2HW.svd (Ver. 0), CEC1734_S0_2ZW.svd (Ver. 0), ; CEC1736_S0_2HW.svd (Ver. 0), CEC1736_S0_2ZW.svd (Ver. 0) ; @Core: Cortex-M4F ; @Chip: CEC1702, CEC1712, CEC1734-2HW, CEC1734-2ZW, ; CEC1736-2HW, CEC1736-2ZW ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: percec17xx.per 19100 2025-02-24 14:34:34Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "ADC (Analog to Digital Converter)" base ad:0x40007C00 group.long 0x0++0x13 line.long 0x0 "CTRL,The ADC Control Register is used to control the behavior of the Analog to Digital Converter." bitfld.long 0x0 7. "SIN_DONE_STS,0: ADC single-sample conversion is not complete. 1: ADC single-sample conversion is completed. (R/WC)" "0: ADC single-sample conversion is not complete,1: ADC single-sample conversion is completed" bitfld.long 0x0 6. "RPT_DONE_STS,0: ADC repeat-sample conversion is not complete. 1: ADC repeat-sample conversion is completed. (R/WC)" "0: ADC repeat-sample conversion is not complete,1: ADC repeat-sample conversion is completed" newline bitfld.long 0x0 4. "SFT_RST,(SFT_RST) 1: writing one causes a reset of the ADC block hardware (not the registers) 0: writing zero takes the ADC block out of reset" "0: writing zero takes the ADC block out of reset,1: writing one causes a reset of the ADC block.." bitfld.long 0x0 3. "PWR_SAV_DIS,0: Power saving feature is enabled. 1: Power saving feature is disabled." "0: Power saving feature is enabled,1: Power saving feature is disabled" newline bitfld.long 0x0 2. "STRT_RPT,0: The ADC Repeat Mode is disabled. 1: The ADC Repeat Mode is enabled." "0: The ADC Repeat Mode is disabled,1: The ADC Repeat Mode is enabled" bitfld.long 0x0 1. "STRT_SIN,(STRT_SIN) 0: The ADC Single Mode is disabled. 1: The ADC Single Mode is enabled. Note: This bit is self-clearing" "0: The ADC Single Mode is disabled,1: The ADC Single Mode is enabled" newline bitfld.long 0x0 0. "ACT,0: The ADC is disabled and placed in its lowest power state. 1: ADC block is enabled for operation." "0: The ADC is disabled and placed in its lowest..,1: ADC block is enabled for operation" line.long 0x4 "DELAY,The ADC Delay register determines the delay from setting Start_Repeat in the \n ADC Control Register and the start of a conversion cycle. This register also controls the interval between conversion cycles in repeat mode." hexmask.long.word 0x4 16.--31. 1. "RPT_DLY,This field determines the interval between conversion cycles when Start_Repeat is 1." hexmask.long.word 0x4 0.--15. 1. "STRT_DLY,This field determines the starting delay before a conversion cycle is begun when Start_Repeat is written with a 1." line.long 0x8 "CHAN_STS,The ADC Status Register indicates whether the ADC has completed a conversion cycle.\n All bits are cleared by being written with a 1. \n 0: conversion of the corresponding ADC channel is not complete\n 1: conversion of.." hexmask.long.word 0x8 0.--15. 1. "STS,All bits are cleared by being written with a '1'. 1=conversion of the corresponding ADC channel is complete;\n 0=conversion of the corresponding ADC channel is not complete. For enabled single cycles the SINGLE_DONE_STATUS bit in the\n.." line.long 0xC "SNG_EN,The ADC Single Register is used to control which ADC channel \n is captured during a Single-Sample conversion cycle initiated by the Start_Single bit in the ADC Control Register. \n APPLICATION NOTE: Do not change the bits in this.." hexmask.long.word 0xC 0.--15. 1. "S_EN,Each bit in this field enables the corresponding ADC channel when a single cycle of conversions is started when the\n START_SINGLE bit in the ADC Control Register is written with a 1. 1=single cycle conversions for this channel are.." line.long 0x10 "REPT_EN,The ADC Repeat Register is used to control which ADC channels \n are captured during a repeat conversion cycle initiated by the Start_Repeat bit in the ADC Control Register." hexmask.long.word 0x10 0.--15. 1. "R_EN,Each bit in this field enables the corresponding ADC channel for each pass of the Repeated ADC Conversion that is\n controlled by bit START_REPEAT in the ADC Control Register. 1=repeat conversions for this channel are enabled;\n.." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x14)++0x3 line.long 0x0 "CHAN_RD[$1],All 16 ADC channels return their results into \n a 32-bit reading register. In each case the low 10 bits of the reading register\n return the result of the Analog to Digital conversion and the upper 22 bits return 0." repeat.end sif (cpuis("CEC1712*")) group.long 0x7C++0x13 line.long 0x0 "CFG,The ADC Configuration Register is used to configure the ADC clock timing." hexmask.long.byte 0x0 24.--31. 1. "DUMYCYC_GAP,These bits define the number of micro-seconds between consective Starts.\n" hexmask.long.byte 0x0 20.--23. 1. "PWRUP_DLY,These bits define the power up delay in number of micro-seconds.\n Valid Values are from 0x0 to 0xF.\n" newline hexmask.long.byte 0x0 16.--19. 1. "CLKDUMY_TIM,These bits define the dummy cycles of the ADC clock.\n Valid Values are from 0x0 to 0xF.\n" hexmask.long.byte 0x0 8.--15. 1. "CLKHIGH_TIM,These bits define the high time count of the ADC clock.\n 0= not used.\n 1= 1 System Clock.\n 2= 2 System Clock.\n" newline hexmask.long.byte 0x0 0.--7. 1. "CLKLW_TIM,These bits define the low time count of the ADC clock.\n 0= not used.\n 1= 1 System Clock.\n 2= 2 System Clock.\n" line.long 0x4 "VREF_CHAN,The ADC Channel Register is used to configure the reference voltage to the clock timing.\n" bitfld.long 0x4 30.--31. "SEL15,These bits define the reference voltage for Channel 15.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 28.--29. "SEL14,These bits define the reference voltage for Channel 14.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 26.--27. "SEL13,These bits define the reference voltage for Channel 13.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 24.--25. "SEL12,These bits define the reference voltage for Channel 12.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 22.--23. "SEL11,These bits define the reference voltage for Channel 11.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 20.--21. "SEL10,These bits define the reference voltage for Channel 10.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 18.--19. "SEL9,These bits define the reference voltage for Channel 9.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 16.--17. "SEL8,These bits define the reference voltage for Channel 8.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 14.--15. "SEL7,These bits define the reference voltage for Channel 7.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 12.--13. "SEL6,These bits define the reference voltage for Channel 6.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 10.--11. "SEL5,These bits define the reference voltage for Channel 5.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 8.--9. "SEL4,These bits define the reference voltage for Channel 4.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 6.--7. "SEL3,These bits define the reference voltage for Channel 3.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 4.--5. "SEL2,These bits define the reference voltage for Channel 2.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" newline bitfld.long 0x4 2.--3. "SEL1,These bits define the reference voltage for Channel 1.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" bitfld.long 0x4 0.--1. "SEL0,These bits define the reference voltage for Channel 0.\n 0h= VREF0\n 1h= VREF1\n 2h= Reserved\n 3h= Reserved\n" "0,1,2,3" line.long 0x8 "VREF_CTRL,This is the VREF Control Register" bitfld.long 0x8 30.--31. "SELSTAT,This fields gives information about the current VREF selected.\n 0x0= VREF0\n 0x1= VREF1\n 0x2= Reserved\n 0x3= Reserved\n" "0: VREF0\n,1: VREF1\n,2: Reserved\n,3: Reserved\n" bitfld.long 0x8 29. "PADCTRL,This fields give the choice to the application whether to float the unused PAD's or to Drive them to 0.\n 1= Drive unused PAD's Low 0b\n 0= Leave unused PAD's Floating.\n" "0: Leave unused PAD's Floating,1: Drive unused PAD's Low 0b\n" newline hexmask.long.word 0x8 16.--28. 1. "SWITCH_DLY,This field represnts the delay time interval between switching VREF Selects.\n" hexmask.long.word 0x8 0.--15. 1. "CHRG_DLY,This field represnts the delay time to charge up the external VREF capacitor.\n" line.long 0xC "SAR_CTRL,This is the SAR ADC Control Register.\n" hexmask.long.word 0xC 7.--15. 1. "WARM_UP_DLY,This field represents the warmup delay number in microseconds.\n" bitfld.long 0xC 5. "EN_SERIAL,This field enables serial output (dout) from ADC.\n 0= Parallel dout.\n 1= Serial dout.\n" "0: Parallel dout,1: Serial dout" newline bitfld.long 0xC 4. "EN_ASYN_SMPL,This field enables asynchronous sampling.\n 0= Async Sampling Disabled.\n 1= Async Sampling Enabled.\n" "0: Async Sampling Disabled,1: Async Sampling Enabled" bitfld.long 0xC 3. "SHIFT_DAT,This field defined if the ADC output is Right or Left Justified.\n 1= adc_dout is not shifted and lower bits are set to 0.\n 0= adc_dout is shifted right following resolution selected.\n" "0: adc_dout is shifted right following resolution..,1: adc_dout is not shifted and lower bits are set.." newline bitfld.long 0xC 1.--2. "SEL_RES,This field select the ADC Resolution (10/12 bits).\n 0x0= Reserved.\n 0x1= Reserved.\n 0x2= 10 bit ADC resolution.\n 0x3= 12 bit ADC resolution.\n" "0: Reserved,1: Reserved,2: 10 bit ADC resolution,3: 12 bit ADC resolution" bitfld.long 0xC 0. "SEL_DIFF,This field select between Single ended / Differential input.\n 0= ADC core is enabled for single ended input operation.\n 1= ADC core is enabled for differential input operation.\n" "0: ADC core is enabled for single ended input..,1: ADC core is enabled for differential input.." line.long 0x10 "SAR_CFG,This is the SAR ADC Configuration Register.\n" bitfld.long 0x10 31. "EN_EXT_BIAS,EN external bias.\n 1 = Disables internal switched cap bias circuit.\n 0 = Enables internal switched cap bias circuit.\n" "0: Enables internal switched cap bias circuit,1: Disables internal switched cap bias circuit" bitfld.long 0x10 28.--29. "ICMBF,This register controls the bias current for common mode buffer amplifier.\n" "0,1,2,3" newline bitfld.long 0x10 26.--27. "ICMBF_STG2,This register controls the bias current for the 2nd stage of the comparator.\n" "0,1,2,3" bitfld.long 0x10 24.--25. "ICMBF_STG1,This register controls the bias current for the 1st stage of the comparator.\n" "0,1,2,3" newline bitfld.long 0x10 22.--23. "IADC_RANGE1,This register controls the current consumption for the whole ADC.\n" "0,1,2,3" bitfld.long 0x10 20.--21. "IADC_RANGE2,This register controls the current consumption for the whole ADC.\n" "0,1,2,3" newline hexmask.long.byte 0x10 11.--15. 1. "CLK_DIV,This register defines the programmable ADC Clock divider value. Divider ratios of 256 128 64 32 16 are supported.\n" bitfld.long 0x10 9.--10. "REGEN_DLY,This register defines the delay between regen and latch.\n" "0,1,2,3" newline bitfld.long 0x10 6. "EN_RADC,Enable RADC.\n 1 = RDAC remains high during power cycling.\n 0 = Controls RDAC during power cycling.\n" "0: Controls RDAC during power cycling,1: RDAC remains high during power cycling" bitfld.long 0x10 5. "LAZ_AU_ZERO,Enable L_AZ AUTOZEROING.\n 1= Disable L_AZ autozeroing.\n 0= Enable L_AZ autozeroing.\n" "0: Enable L_AZ autozeroing,1: Disable L_AZ autozeroing" newline bitfld.long 0x10 4. "SAZ_AU_ZERO,Enable S_AZ AUTOZEROING.\n 1= Disable S_AZ autozeroing.\n 0= Enable S_AZ autozeroing.\n" "0: Enable S_AZ autozeroing,1: Disable S_AZ autozeroing" bitfld.long 0x10 3. "FAZ_AU_ZERO,Enable F_AZ AUTOZEROING.\n 1= Disable f_az autozeroing.\n 0= Enable f_az autozeroing.\n" "0: Enable f_az autozeroing,1: Disable f_az autozeroing" newline bitfld.long 0x10 2. "EN_DITHER,Enable Dithering.\n 0= Disable Dither.\n 1= Enable Dither.\n" "0: Disable Dither,1: Enable Dither" bitfld.long 0x10 1. "DIS_DOUT,Disable Parallel Output.\n 0= Enable Parallel Output.\n 1= Disable Parallel Output.\n" "0: Enable Parallel Output,1: Disable Parallel Output" newline bitfld.long 0x10 0. "EN_CMBF,Enable Common Mode Buffer Amplifier.\n 0= Common Mode Buffer Amplifier is high all the time.\n 1= Controls Common Mode Buffer Amplifier during power cycling.\n" "0: Common Mode Buffer Amplifier is high all the time,1: Controls Common Mode Buffer Amplifier during.." endif tree.end endif tree "CCT (Capture Compare Timer)" base ad:0x40001000 group.long 0x0++0x2F line.long 0x0 "CTRL,This register controls the capture and compare timer." bitfld.long 0x0 25. "CMP_CLR0,When read returns the current value off the Compare Timer Output 0 state." "0,1" bitfld.long 0x0 24. "CMP_CLR1,When read returns the current value off the Compare Timer Output 1 state." "0,1" newline bitfld.long 0x0 17. "CMP_SET0,When read returns the current value off the Compare Timer Output 0 state." "0,1" bitfld.long 0x0 16. "CMP_SET1,When read returns the current value off the Compare Timer Output 1 state." "0,1" newline bitfld.long 0x0 9. "CMP_EN1,Compare Enable for Compare 1 Register." "0,1" bitfld.long 0x0 8. "CMP_EN0,Compare Enable for Compare 0 Register." "0,1" newline bitfld.long 0x0 4.--6. "TCLK,This 3-bit field sets the clock source for the Free-Running Counter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "FREE_RST,Free Running Timer Reset. This bit stops the timer and resets the internal counter to 0000_0000h." "0,1" newline bitfld.long 0x0 1. "FREE_EN,Free-Running Timer Enable. This bit is used to start and stop the free running timer." "0,1" bitfld.long 0x0 0. "ACT,This bit is used to start the capture and compare timer running and power it down." "0,1" line.long 0x4 "CAP0_CTRL,This register is used to configure capture and compare timers 0-3." sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x4 29.--31. "FCLK_SEL3,This 3-bit field sets the clock source for the input filter for Capture Register 3." "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--25. "CAP_EDGE3,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 3." "0,1,2,3" newline bitfld.long 0x4 21.--23. "FCLK_SEL2,This 3-bit field sets the clock source for the input filter for Capture Register 2." "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--17. "CAP_EDGE2,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 2." "0,1,2,3" newline bitfld.long 0x4 13.--15. "FCLK_SEL1,This 3-bit field sets the clock source for the input filter for Capture Register 1." "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--9. "CAP_EDGE1,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 1." "0,1,2,3" newline bitfld.long 0x4 5.--7. "FCLK_SEL0,This 3-bit field sets the clock source for the input filter for Capture Register 0." "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--1. "CAP_EDGE0,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 0." "0,1,2,3" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 29.--31. "FCLK_SEL3,This 3-bit field sets the clock source for the input filter for Capture Register 3." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 29.--31. "FCLK_SEL3,This 3-bit field sets the clock source for the input filter for Capture Register 3." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 29.--31. "FCLK_SEL3,This 3-bit field sets the clock source for the input filter for Capture Register 3." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 29.--31. "FCLK_SEL3,This 3-bit field sets the clock source for the input filter for Capture Register 3." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif bitfld.long 0x4 26. "FILTER_BYP3,This bit enables bypassing the input noise filter for Capture Register 3 so that the input signal goes directly into the timer." "0,1" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 24.--25. "CAP_EDGE3,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 3." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 21.--23. "FCLK_SEL2,This 3-bit field sets the clock source for the input filter for Capture Register 2." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 24.--25. "CAP_EDGE3,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 3." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 21.--23. "FCLK_SEL2,This 3-bit field sets the clock source for the input filter for Capture Register 2." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 24.--25. "CAP_EDGE3,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 3." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 21.--23. "FCLK_SEL2,This 3-bit field sets the clock source for the input filter for Capture Register 2." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 24.--25. "CAP_EDGE3,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 3." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 21.--23. "FCLK_SEL2,This 3-bit field sets the clock source for the input filter for Capture Register 2." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif bitfld.long 0x4 18. "FILTER_BYP2,This bit enables bypassing the input noise filter for Capture Register 2 so that the input signal goes directly into the timer." "0,1" newline sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 16.--17. "CAP_EDGE2,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 2." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" bitfld.long 0x4 13.--15. "FCLK_SEL1,This 3-bit field sets the clock source for the input filter for Capture Register 1." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 16.--17. "CAP_EDGE2,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 2." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" bitfld.long 0x4 13.--15. "FCLK_SEL1,This 3-bit field sets the clock source for the input filter for Capture Register 1." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 16.--17. "CAP_EDGE2,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 2." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" bitfld.long 0x4 13.--15. "FCLK_SEL1,This 3-bit field sets the clock source for the input filter for Capture Register 1." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 16.--17. "CAP_EDGE2,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 2." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" bitfld.long 0x4 13.--15. "FCLK_SEL1,This 3-bit field sets the clock source for the input filter for Capture Register 1." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif bitfld.long 0x4 10. "FILTER_BYP1,This bit enables bypassing the input noise filter for Capture Register 1 so that the input signal goes directly into the timer." "0,1" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 8.--9. "CAP_EDGE1,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 1." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 5.--7. "FCLK_SEL0,This 3-bit field sets the clock source for the input filter for Capture Register 0." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 8.--9. "CAP_EDGE1,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 1." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 5.--7. "FCLK_SEL0,This 3-bit field sets the clock source for the input filter for Capture Register 0." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 8.--9. "CAP_EDGE1,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 1." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 5.--7. "FCLK_SEL0,This 3-bit field sets the clock source for the input filter for Capture Register 0." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 8.--9. "CAP_EDGE1,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 1." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x4 5.--7. "FCLK_SEL0,This 3-bit field sets the clock source for the input filter for Capture Register 0." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif bitfld.long 0x4 2. "FILTER_BYP0,This bit enables bypassing the input noise filter for Capture Register 0 so that the input signal goes directly into the timer." "0,1" newline sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 0.--1. "CAP_EDGE0,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 0." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 0.--1. "CAP_EDGE0,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 0." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 0.--1. "CAP_EDGE0,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 0." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" endif line.long 0x8 "CAP1_CTRL,This register is used to configure capture and compare timers 4-5." sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x8 13.--15. "FCLK_SEL5,This 3-bit field sets the clock source for the input filter for Capture Register 5." "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--9. "CAP_EDGE5,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 5." "0,1,2,3" newline bitfld.long 0x8 5.--7. "FCLK_SEL4,This 3-bit field sets the clock source for the input filter for Capture Register 4." "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--1. "CAP_EDGE4,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 4." "0,1,2,3" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x8 13.--15. "FCLK_SEL5,This 3-bit field sets the clock source for the input filter for Capture Register 5." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x8 13.--15. "FCLK_SEL5,This 3-bit field sets the clock source for the input filter for Capture Register 5." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x8 13.--15. "FCLK_SEL5,This 3-bit field sets the clock source for the input filter for Capture Register 5." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x8 13.--15. "FCLK_SEL5,This 3-bit field sets the clock source for the input filter for Capture Register 5." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" newline endif bitfld.long 0x8 10. "FILTER_BYP5,This bit enables bypassing the input noise filter for Capture Register 5 so that the input signal goes directly into the timer." "0,1" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x8 8.--9. "CAP_EDGE5,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 5." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x8 5.--7. "FCLK_SEL4,This 3-bit field sets the clock source for the input filter for Capture Register 4." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x8 8.--9. "CAP_EDGE5,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 5." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x8 5.--7. "FCLK_SEL4,This 3-bit field sets the clock source for the input filter for Capture Register 4." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x8 8.--9. "CAP_EDGE5,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 5." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x8 5.--7. "FCLK_SEL4,This 3-bit field sets the clock source for the input filter for Capture Register 4." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x8 8.--9. "CAP_EDGE5,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 5." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline bitfld.long 0x8 5.--7. "FCLK_SEL4,This 3-bit field sets the clock source for the input filter for Capture Register 4." "0: Divide by 1 (48 MHz),1: Divide by 2 (24 MHz),2: Divide by 4 (12 MHz),3: Divide by 8 (6 MHz),4: Divide by 16 (3 MHz),5: Divide by 32 (1.5 MHz),6: Divide by 64 (750 KHz),7: Divide by 128 (375 KHz)" endif bitfld.long 0x8 2. "FILTER_BYP4,This bit enables bypassing the input noise filter for Capture Register 4 so that the input signal goes directly into the timer." "0,1" newline sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x8 0.--1. "CAP_EDGE4,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 4." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x8 0.--1. "CAP_EDGE4,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 4." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x8 0.--1. "CAP_EDGE4,This field selects the edge type that triggers the capture of the Free Running Counter into Capture Register 4." "0: Capture on falling edge,1: Capture on rising edge,2: Capture on both falling and rising edges,3: Capture event disabled" endif line.long 0xC "FREE_RUN,This register contains the current value of the Free Running Timer." hexmask.long 0xC 0.--31. 1. "TMR,This register contains the current value of the Free Running Timer." line.long 0x10 "CAP0,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." hexmask.long 0x10 0.--31. 1. "CAP_0,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." line.long 0x14 "CAP1,This register saves the value copied from the Free Running timer on a programmed edge of ICT1." hexmask.long 0x14 0.--31. 1. "CAP_1,This register saves the value copied from the Free Running timer on a programmed edge of ICT1." line.long 0x18 "CAP2,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." hexmask.long 0x18 0.--31. 1. "CAP_2,This register saves the value copied from the Free Running timer on a programmed edge of ICT2." line.long 0x1C "CAP3,This register saves the value copied from the Free Running timer on a programmed edge of ICT0." hexmask.long 0x1C 0.--31. 1. "CAP_3,This register saves the value copied from the Free Running timer on a programmed edge of ICT3." line.long 0x20 "CAP4,This register saves the value copied from the Free Running timer on a programmed edge of ICT4." hexmask.long 0x20 0.--31. 1. "CAP_4,This register saves the value copied from the Free Running timer on a programmed edge of ICT4." line.long 0x24 "CAP5,This register saves the value copied from the Free Running timer on a programmed edge of ICT5." hexmask.long 0x24 0.--31. 1. "CAP_5,This register saves the value copied from the Free Running timer on a programmed edge of ICT5." line.long 0x28 "COMP0,A COMPARE 0 interrupt is generated when this register matches the value in the Free Running Timer." hexmask.long 0x28 0.--31. 1. "COMP_0,A COMPARE 0 interrupt is generated when this register matches the value in the Free Running Timer." line.long 0x2C "COMP1,A COMPARE 1 interrupt is generated when this register matches the value in the Free Running Timer." hexmask.long 0x2C 0.--31. 1. "COMP_1,A COMPARE 1 interrupt is generated when this register matches the value in the Free Running Timer." sif (cpuis("CEC1712*")) group.long 0x30++0x3 line.long 0x0 "MUX_SEL,This register selects the pin mapping to the capture register." hexmask.long.byte 0x0 20.--23. 1. "CAP5,Mux Select for Capture 5 register." hexmask.long.byte 0x0 16.--19. 1. "CAP4,Mux Select for Capture 4 register." newline hexmask.long.byte 0x0 12.--15. 1. "CAP3,Mux Select for Capture 3 register." hexmask.long.byte 0x0 8.--11. 1. "CAP2,Mux Select for Capture 2 register." newline hexmask.long.byte 0x0 4.--7. 1. "CAP1,Mux Select for Capture 1 register." hexmask.long.byte 0x0 0.--3. 1. "CAP0,Mux Select for Capture 0 register." endif sif (cpuis("CEC1734?2HW*")) group.long 0x30++0x3 line.long 0x0 "MUX_SEL,This register selects the pin mapping to the capture register." hexmask.long.byte 0x0 20.--23. 1. "CAP5,Mux Select for Capture 5 register." hexmask.long.byte 0x0 16.--19. 1. "CAP4,Mux Select for Capture 4 register." newline hexmask.long.byte 0x0 12.--15. 1. "CAP3,Mux Select for Capture 3 register." hexmask.long.byte 0x0 8.--11. 1. "CAP2,Mux Select for Capture 2 register." newline hexmask.long.byte 0x0 4.--7. 1. "CAP1,Mux Select for Capture 1 register." hexmask.long.byte 0x0 0.--3. 1. "CAP0,Mux Select for Capture 0 register." endif sif (cpuis("CEC1734?2ZW*")) group.long 0x30++0x3 line.long 0x0 "MUX_SEL,This register selects the pin mapping to the capture register." hexmask.long.byte 0x0 20.--23. 1. "CAP5,Mux Select for Capture 5 register." hexmask.long.byte 0x0 16.--19. 1. "CAP4,Mux Select for Capture 4 register." newline hexmask.long.byte 0x0 12.--15. 1. "CAP3,Mux Select for Capture 3 register." hexmask.long.byte 0x0 8.--11. 1. "CAP2,Mux Select for Capture 2 register." newline hexmask.long.byte 0x0 4.--7. 1. "CAP1,Mux Select for Capture 1 register." hexmask.long.byte 0x0 0.--3. 1. "CAP0,Mux Select for Capture 0 register." endif sif (cpuis("CEC1736?2HW*")) group.long 0x30++0x3 line.long 0x0 "MUX_SEL,This register selects the pin mapping to the capture register." hexmask.long.byte 0x0 20.--23. 1. "CAP5,Mux Select for Capture 5 register." hexmask.long.byte 0x0 16.--19. 1. "CAP4,Mux Select for Capture 4 register." newline hexmask.long.byte 0x0 12.--15. 1. "CAP3,Mux Select for Capture 3 register." hexmask.long.byte 0x0 8.--11. 1. "CAP2,Mux Select for Capture 2 register." newline hexmask.long.byte 0x0 4.--7. 1. "CAP1,Mux Select for Capture 1 register." hexmask.long.byte 0x0 0.--3. 1. "CAP0,Mux Select for Capture 0 register." endif sif (cpuis("CEC1736?2ZW*")) group.long 0x30++0x3 line.long 0x0 "MUX_SEL,This register selects the pin mapping to the capture register." hexmask.long.byte 0x0 20.--23. 1. "CAP5,Mux Select for Capture 5 register." hexmask.long.byte 0x0 16.--19. 1. "CAP4,Mux Select for Capture 4 register." newline hexmask.long.byte 0x0 12.--15. 1. "CAP3,Mux Select for Capture 3 register." hexmask.long.byte 0x0 8.--11. 1. "CAP2,Mux Select for Capture 2 register." newline hexmask.long.byte 0x0 4.--7. 1. "CAP1,Mux Select for Capture 1 register." hexmask.long.byte 0x0 0.--3. 1. "CAP0,Mux Select for Capture 0 register." endif tree.end sif (cpuis("CEC1702*")) tree "CNT_TMR (16-bit Counter-Timer Interface)" base ad:0x0 tree "CNT_TMR0" base ad:0x40000D00 group.long 0x0++0xF line.long 0x0 "TIMERX_CTRL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TMRX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block;\n 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLP_EN,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POL,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal \n this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode\n.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FIL_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled.\n The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes.\n It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;\n.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin.\n Event Mode: 1=The timer counts up; 0=The timer counts down.\n Timer Mode:; 1=TINx pin pauses the timer.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RST,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit\n also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the\n.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "EN,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer\n pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted automatically; this will become the new value of the counter upon restart." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies\n are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode.\n 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode.\n Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RLD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TMR_RLD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer.\n In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the\n timer.." line.long 0xC "TIMERX_CNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TMR_CNT,This is the current value of the timer in all modes." tree.end tree "CNT_TMR1" base ad:0x40000D20 group.long 0x0++0xF line.long 0x0 "TIMERX_CTRL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TMRX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block;\n 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLP_EN,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POL,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal \n this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode\n.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FIL_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled.\n The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes.\n It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;\n.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin.\n Event Mode: 1=The timer counts up; 0=The timer counts down.\n Timer Mode:; 1=TINx pin pauses the timer.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RST,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit\n also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the\n.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "EN,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer\n pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted automatically; this will become the new value of the counter upon restart." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies\n are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode.\n 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode.\n Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RLD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TMR_RLD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer.\n In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the\n timer.." line.long 0xC "TIMERX_CNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TMR_CNT,This is the current value of the timer in all modes." tree.end tree "CNT_TMR2" base ad:0x40000D40 group.long 0x0++0xF line.long 0x0 "TIMERX_CTRL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TMRX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block;\n 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLP_EN,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POL,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal \n this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode\n.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FIL_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled.\n The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes.\n It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;\n.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin.\n Event Mode: 1=The timer counts up; 0=The timer counts down.\n Timer Mode:; 1=TINx pin pauses the timer.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RST,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit\n also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the\n.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "EN,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer\n pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted automatically; this will become the new value of the counter upon restart." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies\n are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode.\n 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode.\n Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RLD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TMR_RLD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer.\n In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the\n timer.." line.long 0xC "TIMERX_CNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TMR_CNT,This is the current value of the timer in all modes." tree.end tree "CNT_TMR3" base ad:0x40000D60 group.long 0x0++0xF line.long 0x0 "TIMERX_CTRL,This bit reflects the current state of the timer's Clock_Required output signal." bitfld.long 0x0 12. "TMRX_CLK_REQ,This bit reflects the current state of the timer's Clock_Required output signal. 1=The main clock is required by this block;\n 0=The main clock is not required by this block." "0: The main clock is not required by this block,1: The main clock is required by this block" bitfld.long 0x0 11. "SLP_EN,This bit reflects the current state of the timer's Sleep_Enable input signal. 1=Normal operation; 0=Sleep Mode is requested." "0: Sleep Mode is requested,1: Normal operation" newline bitfld.long 0x0 10. "TOUT_POL,This bit determines the polarity of the TOUTx output signal. In timer modes that toggle the TOUTx signal \n this polarity bit will not have a perceivable difference except to determine the inactive state. In One-Shot mode\n.." "0: Active high,1: Active low" bitfld.long 0x0 9. "PD,Power Down. 1=The timer is powered down and all clocks are gated; 0=The timer is in a running state." "0: The timer is in a running state,1: The timer is powered down and all clocks are gated" newline bitfld.long 0x0 8. "FIL_BYPASS,This bit is used to enable or disable the noise filter on the TINx input signal. 1=Bypass Mode: input filter disabled.\n The TINx input directly affects the timer; 0=Filter Mode: input filter enabled. The TINx input is.." "0: Filter Mode: input filter enabled,1: Bypass Mode: input filter disabled" bitfld.long 0x0 7. "RLOAD,Reload Control. This bit controls how the timer is reloaded on overflow or underflow in Event and Timer modes.\n It has no effect in One shot mode. 1=Reload timer from Timer Reload Register and continue counting;\n.." "0: Roll timer over to FFFFh and continue counting..,1: Reload timer from Timer Reload Register and.." newline bitfld.long 0x0 6. "TOUT_EN,This bit enables the TOUTx pin. 1=TOUTx pin function is enabled; 0=TOUTx pin is inactive." "0: TOUTx pin is inactive,1: TOUTx pin function is enabled" bitfld.long 0x0 5. "UPDN,In Event Mode this bit selects the timer count direction. In Timer Mode enables timer control by the TINx input pin.\n Event Mode: 1=The timer counts up; 0=The timer counts down.\n Timer Mode:; 1=TINx pin pauses the timer.." "0: TINx pin has no effect on the timer,1: TINx pin pauses the timer when de-asserted" newline bitfld.long 0x0 4. "INPOL,This bit selects the polarity of the TINx input. 1=TINx is active low; 0=TINx is active high." "0: TINx is active high,1: TINx is active low" bitfld.long 0x0 2.--3. "MODE,Timer Mode. 3=Measurement Mode; 2=One Shot Mode; 1=Event Mode; 0=Timer Mode." "0: Timer Mode,1: Event Mode,2: One Shot Mode,3: Measurement Mode" newline bitfld.long 0x0 1. "RST,This bit stops the timer and resets the internal counter to the value in the Timer Reload Register. This bit\n also clears the ENABLE bit if it is set. This bit is self-clearing after the timer is reset. Firmware must poll the\n.." "0: Normal timer operation,1: Timer reset" bitfld.long 0x0 0. "EN,This bit is used to start and stop the timer. This bit does not reset the timer count but does reset the timer\n pulse output. This bit will be cleared when the timer stops counting in One-Shot mode. The ENABLE bit is cleared.." "0: Timer is disabled,1: Timer is enabled" line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted automatically; this will become the new value of the counter upon restart." hexmask.long.byte 0x4 8.--11. 1. "FCLK,Timer Clock Select. This field determines the clock source for the TINx noise filter. The available frequencies\n are the same as for TCLK." bitfld.long 0x4 7. "EVENT,Event Select. This bit is used to select the count source when the timer is operating in Event Mode.\n 1=TINx is count source; 0=Timer x-1 overflow is count source." "0: Timer x-1 overflow is count source,1: TINx is count source" newline bitfld.long 0x4 5.--6. "EDGE,This field selects which edge of the TINx input signal affects the timer in Event Mode One-Shot Mode and Measurement Mode.\n Event Mode: 11b=No event selected; 10b=Counts rising and falling edges; 01b=Counts rising edges; 00b=Counts.." "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "TCLK,Timer Clock Select. This field determines the clock source for the 16-bit counter in the timer." line.long 0x8 "TIMERX_RLD,This register is used in Timer and One-Shot modes to set the lower limit of the timer." hexmask.long.word 0x8 0.--15. 1. "TMR_RLD,The Timer Reload register is used in Timer and One-Shot modes to set the lower limit of the timer.\n In Event mode the Timer Reload register sets either the upper or lower limit of the timer depending on if the\n timer.." line.long 0xC "TIMERX_CNT,This register returns the current value of the timer in all modes." hexmask.long.word 0xC 0.--15. 1. "TMR_CNT,This is the current value of the timer in all modes." tree.end tree.end endif tree "DMA_CHAN (DMA Channel)" base ad:0x0 tree "DMA_CHAN00" base ad:0x40002440 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable.." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to Memory.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the transfer over the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" group.long 0x20++0xB line.long 0x0 "CRC_EN,DMA CHANNEL N CRC ENABLE" bitfld.long 0x0 1. "POST_TRANS,The bit enables the transfer of the calculated CRC-32 after the completion of the DMA transaction.\n If the DMA transaction is aborted by either firmware or an internal bus error the transfer will not occur.\n If the target.." "0: Disable the automatic transfer of the CRC,1: Enable the transfer of CRC-32 for DMA Channel N.." bitfld.long 0x0 0. "MODE,1=Enable the calculation of CRC-32 for DMA Channel N\n 0=Disable the calculation of CRC-32 for DMA Channel N" "0: Disable the calculation of CRC-32 for DMA..,1: Enable the calculation of CRC-32 for DMA Channel.." line.long 0x4 "CRC_DATA,DMA CHANNEL N CRC DATA" hexmask.long 0x4 0.--31. 1. "CRC,Writes to this register initialize the CRC generator. Reads from this register return the output of the\n CRC that is calculated from the data transferred by DMA Channel N. The output of the CRC generator is bit-reversed\n and.." line.long 0x8 "CRC_POST_STS,DMA CHANNEL N CRC POST STATUS" bitfld.long 0x8 3. "CRC_DATA_READY,This bit is set to '1b' when the DMA controller is processing the post-transfer of the CRC data.\n This bit is cleared to '0b' when the post-transfer completes." "0,1" bitfld.long 0x8 2. "CRC_DATA_DONE,This bit is set to '1b' when the DMA controller has completed the post-transfer of the CRC data.\n This bit is cleared to '0b' when the a new DMA transfer starts." "0,1" newline bitfld.long 0x8 1. "CRC_RUNNING,This bit is set to '1b' when the DMA controller starts the post-transfer transmission of the CRC.\n It is only set when the post-transfer is enabled by the CRC_POST_TRANSFER_ENABLE field. This bit is cleared\n to '0b' when.." "0,1" bitfld.long 0x8 0. "CRC_DONE,This bit is set to '1b' when the CRC calculation has completed from either normal or forced termination.\n It is cleared to '0b' when the DMA controller starts a new transfer on the channel." "0,1" tree.end tree "DMA_CHAN01" base ad:0x40002480 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the transfer over.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA.\n.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERROR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" group.long 0x20++0xB line.long 0x0 "FILL_EN,DMA CHANNEL N FILL ENABLE" bitfld.long 0x0 0. "MODE,1=Enable the calculation of CRC-32 for DMA Channel N\n 0=Disable the calculation of CRC-32 for DMA Channel N" "0: Disable the calculation of CRC-32 for DMA..,1: Enable the calculation of CRC-32 for DMA Channel.." line.long 0x4 "FILL_DATA,DMA CHANNEL N FILL DATA" hexmask.long 0x4 0.--31. 1. "DATA,This is the data pattern used to fill memory." line.long 0x8 "FILL_STS,DMA CHANNEL N FILL STATUS" bitfld.long 0x8 1. "RUNNING,This bit is set to '1b' when the DMA controller starts the post-transfer transmission of the CRC.\n It is only set when the post-transfer is enabled by the CRC_POST_TRANSFER_ENABLE field. This bit is cleared\n to '0b' when.." "0,1" bitfld.long 0x8 0. "DONE,This bit is set to '1b' when the CRC calculation has completed from either normal or forced termination.\n It is cleared to '0b' when the DMA controller starts a new transfer on the channel." "0,1" tree.end tree "DMA_CHAN02" base ad:0x400024C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN03" base ad:0x40002500 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN04" base ad:0x40002540 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN05" base ad:0x40002580 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN06" base ad:0x400025C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN07" base ad:0x40002600 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN08" base ad:0x40002640 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end tree "DMA_CHAN09" base ad:0x40002680 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "DMA_CHAN10" base ad:0x400026C0 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "DMA_CHAN11" base ad:0x40002700 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end endif sif (cpuis("CEC1702*")) tree "DMA_CHAN12" base ad:0x40002740 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end endif sif (cpuis("CEC1702*")) tree "DMA_CHAN13" base ad:0x40002780 group.byte 0x0++0x0 line.byte 0x0 "ACTIVATE,Enable this channel for operation. The DMA Main Control: Activate must also be enabled for this channel to be operational." bitfld.byte 0x0 0. "CHN,Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this channel to be operational.\n 1=Enable channel(block). Each individual channel must be enabled separately.\n 0=Disable channel(block)." "0: Disable channel,1: Enable channel" group.long 0x4++0xF line.long 0x0 "MSTART,This is the starting address for the Memory device." line.long 0x4 "MEND,This is the ending address for the Memory device." line.long 0x8 "DSTART,This is the Master Device address." line.long 0xC "CTRL,DMA Channel N Control" bitfld.long 0xC 25. "TRANS_ABORT,This is used to abort the current transfer on this DMA Channel. The aborted transfer will be forced to terminate immediately." "0,1" bitfld.long 0xC 24. "TRANS_GO,This is used for the Firmware Flow Control DMA transfer." "0,1" newline bitfld.long 0xC 20.--22. "TRANS_SIZE,This is the transfer size in Bytes of each Data Packet transfer.\n Note: The transfer size must be a legal AMBA transfer size. Valid sizes are 1 2 and 4 Bytes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19. "DIS_HW_FLOW_CTRL,This will Disable the Hardware Flow Control. When disabled any DMA Master device attempting to communicate to the DMA over the DMA Flow Control Interface (Ports: dma_req dma_term and dma_done) will be ignored. This should be set.." "0,1" newline bitfld.long 0xC 18. "LOCK,This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted Transfer Done or Transfer.." "0,1" bitfld.long 0xC 17. "INC_DEV_ADDR,This will enable an auto-increment to the DMA Channel Device Address.\n 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0: Do nothing" "0: Do nothing,1: Increment the DMA Channel Device Address by DMA.." newline bitfld.long 0xC 16. "INC_MEM_ADDR,This will enable an auto-increment to the DMA Channel Memory Address.\n 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer\n 0=Do nothing" "0: Do nothing,1: Increment the DMA Channel Memory Address by DMA.." hexmask.long.byte 0xC 9.--15. 1. "HW_FLOW_CTRL_DEV,This is the device that is connected to this channel as its Hardware Flow Control master.\n The Flow Control Interface is a bus with each master concatenated onto it.\n This selects which bus index of the.." newline bitfld.long 0xC 8. "TX_DIR,This determines the direction of the DMA Transfer.\n 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address\n 0=Data Packet Read from Device Address followed by Data Packet Write to.." "0: Data Packet Read from Device Address followed by..,1: Data Packet Read from Memory Start Address.." bitfld.long 0xC 5. "BUSY,This is a status signal.\n 1=The DMA Channel is busy (FSM is not IDLE)\n 0=The DMA Channel is not busy (FSM is IDLE)" "0: The DMA Channel is not busy,1: The DMA Channel is busy" newline bitfld.long 0xC 3.--4. "STS,This is a status signal. The status decode is listed in priority order with the highest priority first.\n 3: Error detected by the DMA\n 2: The DMA Channel is externally done in that the Device has terminated the.." "0: DMA Channel Control:Run is Disabled,1: The DMA Channel is locally done,2: The DMA Channel is externally done,3: Error detected by the DMA\n" bitfld.long 0xC 2. "DONE,This is a status signal. It is only valid while DMA Channel Control: Run is Enabled. \n This is the inverse of the DMA Channel Control: Busy field except this is qualified with the DMA Channel Control:Run field.\n 1=Channel is.." "0: Channel is not done or it is OFF,1: Channel is done\n" newline bitfld.long 0xC 1. "REQ,This is a status field.\n 1= There is a transfer request from the Master Device\n 0= There is no transfer request from the Master Device" "0: There is no transfer request from the Master..,1: There is a transfer request from the Master.." bitfld.long 0xC 0. "RUN,This is a control field. Note: This bit only applies to Hardware Flow Control mode.\n 1= This channel is enabled and will service transfer requests\n 0=This channel is disabled. All transfer requests are ignored." "0: This channel is disabled,1: This channel is enabled and will service.." group.byte 0x14++0x0 line.byte 0x0 "ISTS,DMA Channel N Interrupt Status" bitfld.byte 0x0 2. "DONE,This is an interrupt source register. This flags when the DMA Channel has completed a transfer successfully on its side.\n A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End.." "0: Memory Start Address does not equal Memory End..,1: Memory Start Address equals Memory End Address\n" bitfld.byte 0x0 1. "FLOW_CTRL,This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request\n after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the.." "0: No Hardware Flow Control event,1: Hardware Flow Control is requesting after the.." newline bitfld.byte 0x0 0. "BUS_ERR,This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus.\n 1: Error detected. (R/WC)" "?,1: Error detected" group.byte 0x18++0x0 line.byte 0x0 "IEN,DMA CHANNEL N INTERRUPT ENABLE" bitfld.byte 0x0 2. "STS_EN_DONE,This is an interrupt enable for DMA Channel Interrupt:Status Done.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" bitfld.byte 0x0 1. "STS_EN_FLOW_CTRL,This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" newline bitfld.byte 0x0 0. "STS_EN_BUS_ERR,This is an interrupt enable for DMA Channel Interrupt:Status Bus Error.\n 1=Enable Interrupt\n 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt\n" tree.end endif tree.end tree "DMA_MAIN (DMA Main Registers)" base ad:0x40002400 group.byte 0x0++0x0 line.byte 0x0 "ACTRST,Soft reset the entire module. Enable the blocks operation." bitfld.byte 0x0 1. "SOFT_RST,Soft reset the entire module. This bit is self-clearing." "0,1" bitfld.byte 0x0 0. "ACT,Enable the blocks operation. (R/WS)\n 1=Enable block. Each individual channel must be enabled separately.\n 0=Disable all channels." "0: Disable all channels,1: Enable block" rgroup.long 0x4++0x3 line.long 0x0 "DATA_PKT,Debug register that has the data that is stored in the Data Packet. This data is read data from the currently active transfer source." tree.end sif (cpuis("CEC1702*")) base ad:0x4000FC04 elif (cpuis("CEC1712*")||cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) base ad:0x4000FC00 endif tree "EC_REG_BANK" sif (cpuis("CEC1734?2HW*")) group.byte 0x0++0x0 line.byte 0x0 "SRAM_CNFG,SRAM Configuration Register" bitfld.byte 0x0 0.--1. "SRAM_SIZE,SRAM Configuration Register: 0: 384KB (352k Code 32k Data) 1: 320kB (288k Code 32k Data) 2: 256kB (224k Code 32k Data) 3: Illegal 256kB (224k Code 32k Data)" "0: 384KB,1: 320kB,2: 256kB,3: Illegal 256kB" group.long 0x70++0x3 line.long 0x0 "SRAM_BNK_SWP,Security Monitor SRAM Bank Swap Register" bitfld.long 0x0 0. "BNK_SWP,SRAM bank Swap Register" "0,1" group.long 0x90++0x3 line.long 0x0 "VW_SRC_CNGF,Virtual Wire Source Configuration Register" bitfld.long 0x0 0.--2. "VW_SRC,VWIRE_SOURCE [2] VWIRE_SOURCE [1] VWIRE_SOURCE [0]" "0,1,2,3,4,5,6,7" group.long 0xC4++0x3 line.long 0x0 "SPIMON_IB_CNGF,SPI Monitor's Inter-Bus Configuration Register" bitfld.long 0x0 27. "IDE,Inter-Bus Intervention Enable" "0,1" bitfld.long 0x0 25.--26. "IDU,Delay Units" "0,1,2,3" newline hexmask.long.byte 0x0 20.--24. 1. "IDV,Delay Value" bitfld.long 0x0 12. "IDL,Lock bit for IDE" "0,1" newline bitfld.long 0x0 9. "MON1,QSPI1 Monitor 1. 1 = Route QMSPI1 Traffic to Monitor. 0 = Route Host AP1 Traffic to Monitor" "0: Route Host AP1 Traffic to Monitor,1: Route QMSPI1 Traffic to Monitor" bitfld.long 0x0 8. "MON0,QSPI0 Monitor 0. 1 = Route QMSPI0 Traffic to Monitor. 0 = Route Host AP0 Traffic to Monitor" "0: Route Host AP0 Traffic to Monitor,1: Route QMSPI0 Traffic to Monitor" endif sif (cpuis("CEC1734?2ZW*")) group.byte 0x0++0x0 line.byte 0x0 "SRAM_CNFG,SRAM Configuration Register" bitfld.byte 0x0 0.--1. "SRAM_SIZE,SRAM Configuration Register: 0: 384KB (352k Code 32k Data) 1: 320kB (288k Code 32k Data) 2: 256kB (224k Code 32k Data) 3: Illegal 256kB (224k Code 32k Data)" "0: 384KB,1: 320kB,2: 256kB,3: Illegal 256kB" group.long 0x70++0x3 line.long 0x0 "SRAM_BNK_SWP,Security Monitor SRAM Bank Swap Register" bitfld.long 0x0 0. "BNK_SWP,SRAM bank Swap Register" "0,1" group.long 0x90++0x3 line.long 0x0 "VW_SRC_CNGF,Virtual Wire Source Configuration Register" bitfld.long 0x0 0.--2. "VW_SRC,VWIRE_SOURCE [2] VWIRE_SOURCE [1] VWIRE_SOURCE [0]" "0,1,2,3,4,5,6,7" group.long 0xC4++0x3 line.long 0x0 "SPIMON_IB_CNGF,SPI Monitor's Inter-Bus Configuration Register" bitfld.long 0x0 27. "IDE,Inter-Bus Intervention Enable" "0,1" bitfld.long 0x0 25.--26. "IDU,Delay Units" "0,1,2,3" newline hexmask.long.byte 0x0 20.--24. 1. "IDV,Delay Value" bitfld.long 0x0 12. "IDL,Lock bit for IDE" "0,1" newline bitfld.long 0x0 9. "MON1,QSPI1 Monitor 1. 1 = Route QMSPI1 Traffic to Monitor. 0 = Route Host AP1 Traffic to Monitor" "0: Route Host AP1 Traffic to Monitor,1: Route QMSPI1 Traffic to Monitor" bitfld.long 0x0 8. "MON0,QSPI0 Monitor 0. 1 = Route QMSPI0 Traffic to Monitor. 0 = Route Host AP0 Traffic to Monitor" "0: Route Host AP0 Traffic to Monitor,1: Route QMSPI0 Traffic to Monitor" group.long 0x240++0x7 line.long 0x0 "PD_MON_CTRL,PAD Monitor Control Register" bitfld.long 0x0 14. "VTR2_PROTECN,PAD Monitor Override Protect N VTR2." "0,1" bitfld.long 0x0 13. "VTR2_INPT_DIS,PAD Monitor Override Input Disable VTR2. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 12. "OVRD_VTR2,PAD Monitor Override VTR2 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 8.--9. "CTRL_VTR2,Pad Monitor Control VTR2. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" newline bitfld.long 0x0 6. "VTR1_PROTECN,PAD Monitor Override Protect N VTR1." "0,1" bitfld.long 0x0 5. "VTR1_INPT_DIS,PAD Monitor Override Input Disable VTR1. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 4. "OVRD_VTR1,PAD Monitor Override VTR1 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 0.--1. "CTRL_VTR1,Pad Monitor Control VTR1. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" line.long 0x4 "PD_MON_INT_EN,PAD Monitor Interrupt Enable Register" bitfld.long 0x4 9. "VTR2_PU_INTEN,Pad Monitor VTR2 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 8. "VTR2_PD_INTEN,Pad Monitor VTR2 Power Down Interrupt Enable." "0,1" newline bitfld.long 0x4 1. "VTR1_PU_INTEN,Pad Monitor VTR1 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 0. "VTR1_PD_INTEN,Pad Monitor VTR1 Power Down Interrupt Enable." "0,1" endif sif (cpuis("CEC1736?2HW*")) group.byte 0x0++0x0 line.byte 0x0 "SRAM_CNFG,SRAM Configuration Register" bitfld.byte 0x0 0.--1. "SRAM_SIZE,SRAM Configuration Register: 0: 384KB (352k Code 32k Data) 1: 320kB (288k Code 32k Data) 2: 256kB (224k Code 32k Data) 3: Illegal 256kB (224k Code 32k Data)" "0: 384KB,1: 320kB,2: 256kB,3: Illegal 256kB" group.long 0x70++0x3 line.long 0x0 "SRAM_BNK_SWP,Security Monitor SRAM Bank Swap Register" bitfld.long 0x0 0. "BNK_SWP,SRAM bank Swap Register" "0,1" group.long 0x90++0x3 line.long 0x0 "VW_SRC_CNGF,Virtual Wire Source Configuration Register" bitfld.long 0x0 0.--2. "VW_SRC,VWIRE_SOURCE [2] VWIRE_SOURCE [1] VWIRE_SOURCE [0]" "0,1,2,3,4,5,6,7" group.long 0xC4++0x3 line.long 0x0 "SPIMON_IB_CNGF,SPI Monitor's Inter-Bus Configuration Register" bitfld.long 0x0 27. "IDE,Inter-Bus Intervention Enable" "0,1" bitfld.long 0x0 25.--26. "IDU,Delay Units" "0,1,2,3" newline hexmask.long.byte 0x0 20.--24. 1. "IDV,Delay Value" bitfld.long 0x0 12. "IDL,Lock bit for IDE" "0,1" newline bitfld.long 0x0 9. "MON1,QSPI1 Monitor 1. 1 = Route QMSPI1 Traffic to Monitor. 0 = Route Host AP1 Traffic to Monitor" "0: Route Host AP1 Traffic to Monitor,1: Route QMSPI1 Traffic to Monitor" bitfld.long 0x0 8. "MON0,QSPI0 Monitor 0. 1 = Route QMSPI0 Traffic to Monitor. 0 = Route Host AP0 Traffic to Monitor" "0: Route Host AP0 Traffic to Monitor,1: Route QMSPI0 Traffic to Monitor" group.long 0x240++0x7 line.long 0x0 "PD_MON_CTRL,PAD Monitor Control Register" bitfld.long 0x0 14. "VTR2_PROTECN,PAD Monitor Override Protect N VTR2." "0,1" bitfld.long 0x0 13. "VTR2_INPT_DIS,PAD Monitor Override Input Disable VTR2. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 12. "OVRD_VTR2,PAD Monitor Override VTR2 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 8.--9. "CTRL_VTR2,Pad Monitor Control VTR2. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" newline bitfld.long 0x0 6. "VTR1_PROTECN,PAD Monitor Override Protect N VTR1." "0,1" bitfld.long 0x0 5. "VTR1_INPT_DIS,PAD Monitor Override Input Disable VTR1. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 4. "OVRD_VTR1,PAD Monitor Override VTR1 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 0.--1. "CTRL_VTR1,Pad Monitor Control VTR1. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" line.long 0x4 "PD_MON_INT_EN,PAD Monitor Interrupt Enable Register" bitfld.long 0x4 9. "VTR2_PU_INTEN,Pad Monitor VTR2 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 8. "VTR2_PD_INTEN,Pad Monitor VTR2 Power Down Interrupt Enable." "0,1" newline bitfld.long 0x4 1. "VTR1_PU_INTEN,Pad Monitor VTR1 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 0. "VTR1_PD_INTEN,Pad Monitor VTR1 Power Down Interrupt Enable." "0,1" endif sif (cpuis("CEC1736?2ZW*")) group.byte 0x0++0x0 line.byte 0x0 "SRAM_CNFG,SRAM Configuration Register" bitfld.byte 0x0 0.--1. "SRAM_SIZE,SRAM Configuration Register: 0: 384KB (352k Code 32k Data) 1: 320kB (288k Code 32k Data) 2: 256kB (224k Code 32k Data) 3: Illegal 256kB (224k Code 32k Data)" "0: 384KB,1: 320kB,2: 256kB,3: Illegal 256kB" group.long 0x70++0x3 line.long 0x0 "SRAM_BNK_SWP,Security Monitor SRAM Bank Swap Register" bitfld.long 0x0 0. "BNK_SWP,SRAM bank Swap Register" "0,1" group.long 0x90++0x3 line.long 0x0 "VW_SRC_CNGF,Virtual Wire Source Configuration Register" bitfld.long 0x0 0.--2. "VW_SRC,VWIRE_SOURCE [2] VWIRE_SOURCE [1] VWIRE_SOURCE [0]" "0,1,2,3,4,5,6,7" group.long 0xC4++0x3 line.long 0x0 "SPIMON_IB_CNGF,SPI Monitor's Inter-Bus Configuration Register" bitfld.long 0x0 27. "IDE,Inter-Bus Intervention Enable" "0,1" bitfld.long 0x0 25.--26. "IDU,Delay Units" "0,1,2,3" newline hexmask.long.byte 0x0 20.--24. 1. "IDV,Delay Value" bitfld.long 0x0 12. "IDL,Lock bit for IDE" "0,1" newline bitfld.long 0x0 9. "MON1,QSPI1 Monitor 1. 1 = Route QMSPI1 Traffic to Monitor. 0 = Route Host AP1 Traffic to Monitor" "0: Route Host AP1 Traffic to Monitor,1: Route QMSPI1 Traffic to Monitor" bitfld.long 0x0 8. "MON0,QSPI0 Monitor 0. 1 = Route QMSPI0 Traffic to Monitor. 0 = Route Host AP0 Traffic to Monitor" "0: Route Host AP0 Traffic to Monitor,1: Route QMSPI0 Traffic to Monitor" group.long 0x240++0x7 line.long 0x0 "PD_MON_CTRL,PAD Monitor Control Register" bitfld.long 0x0 14. "VTR2_PROTECN,PAD Monitor Override Protect N VTR2." "0,1" bitfld.long 0x0 13. "VTR2_INPT_DIS,PAD Monitor Override Input Disable VTR2. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 12. "OVRD_VTR2,PAD Monitor Override VTR2 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 8.--9. "CTRL_VTR2,Pad Monitor Control VTR2. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" newline bitfld.long 0x0 6. "VTR1_PROTECN,PAD Monitor Override Protect N VTR1." "0,1" bitfld.long 0x0 5. "VTR1_INPT_DIS,PAD Monitor Override Input Disable VTR1. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 4. "OVRD_VTR1,PAD Monitor Override VTR1 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 0.--1. "CTRL_VTR1,Pad Monitor Control VTR1. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" line.long 0x4 "PD_MON_INT_EN,PAD Monitor Interrupt Enable Register" bitfld.long 0x4 9. "VTR2_PU_INTEN,Pad Monitor VTR2 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 8. "VTR2_PD_INTEN,Pad Monitor VTR2 Power Down Interrupt Enable." "0,1" newline bitfld.long 0x4 1. "VTR1_PU_INTEN,Pad Monitor VTR1 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 0. "VTR1_PD_INTEN,Pad Monitor VTR1 Power Down Interrupt Enable." "0,1" endif group.long 0x4++0x3 line.long 0x0 "AHB_ERR_ADDR,AHB Error Address [0:0] AHB_ERR_ADDR. In priority order:\n 1. AHB address is registered when an AHB error occurs on the processor's AHB master port and the register value was\n already 0. This way only the first address to.." group.byte 0x14++0x0 line.byte 0x0 "AHB_ERR_CTRL,AHB Error Control [0:0] AHB_ERROR_DISABLE.\n 0: EC memory exceptions are enabled. 1: EC memory exceptions are disabled." group.long 0x18++0x17 line.long 0x0 "INTR_CTRL,Interrupt Control [0:0] NVIC_EN (NVIC_EN) \n This bit enables Alternate NVIC IRQ's Vectors. The Alternate NVIC Vectors provides each interrupt event with a dedicated (direct) NVIC vector.\n 0 = Alternate NVIC vectors disabled. 1=.." line.long 0x4 "ETM_CTRL,ETM TRACE Enable [0:0] TRACE_EN (TRACE_EN) \n This bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug Interface pins are forced to the TRACE functions.\n 0 = ARM TRACE port disabled. 1= ARM TRACE port enabled" line.long 0x8 "DEBUG_CTRL,Debug Enable Register" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x8 4. "BS_EN,This bit sets the boundary scan tap controller accessibility from JTAG port. 1= Boundary scan tap controller accessibile through JTAG Port. 0= Boundary scan tap controller not accessibile through JTAG Port." "0: Boundary scan tap controller not accessibile..,1: Boundary scan tap controller accessibile through.." newline bitfld.long 0x8 3. "JTAG_PU_EN,If this bit is set to '1b' internal pull-up resistors are automatically enabled on the appropriate debugging port wires whenever the debug port is enabled (the DEBUG_EN bit in this register is '1b' and the JTAG_RST# pin is high). The.." "0,1" newline bitfld.long 0x8 1.--2. "DBG_PIN_CFG,This field determines which pins are affected by the TRST# debug enable pin. 3=Reserved 2=The pins associated with the JTAG TCK and TMS switch to the debug interface when TRST# is de-asserted high. The pins associated with TDI.." "0: All four pins associated with JTAG,1: The pins associated with the JTAG TCK,2: The pins associated with the JTAG TCK and TMS..,3: Reserved" newline bitfld.long 0x8 0. "JTAG_EN,DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug port. 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e. the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state) 1= JTAG/SWD port.." "0: JTAG/SWD port disabled,1: JTAG/SWD port enabled" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x8 4. "BS_EN,This bit sets the boundary scan tap controller accessibility from JTAG port. 1= Boundary scan tap controller accessibile through JTAG Port. 0= Boundary scan tap controller not accessibile through JTAG Port." "0: Boundary scan tap controller not accessibile..,1: Boundary scan tap controller accessibile through.." newline bitfld.long 0x8 3. "JTAG_PU_EN,If this bit is set to '1b' internal pull-up resistors are automatically enabled on the appropriate debugging port wires whenever the debug port is enabled (the DEBUG_EN bit in this register is '1b' and the JTAG_RST# pin is high). The.." "0,1" newline bitfld.long 0x8 1.--2. "DBG_PIN_CFG,This field determines which pins are affected by the TRST# debug enable pin. 3=Reserved 2=The pins associated with the JTAG TCK and TMS switch to the debug interface when TRST# is de-asserted high. The pins associated with TDI.." "0: All four pins associated with JTAG,1: The pins associated with the JTAG TCK,2: The pins associated with the JTAG TCK and TMS..,3: Reserved" newline bitfld.long 0x8 0. "JTAG_EN,DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug port. 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e. the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state) 1= JTAG/SWD port.." "0: JTAG/SWD port disabled,1: JTAG/SWD port enabled" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x8 4. "BS_EN,This bit sets the boundary scan tap controller accessibility from JTAG port. 1= Boundary scan tap controller accessibile through JTAG Port. 0= Boundary scan tap controller not accessibile through JTAG Port." "0: Boundary scan tap controller not accessibile..,1: Boundary scan tap controller accessibile through.." newline bitfld.long 0x8 3. "JTAG_PU_EN,If this bit is set to '1b' internal pull-up resistors are automatically enabled on the appropriate debugging port wires whenever the debug port is enabled (the DEBUG_EN bit in this register is '1b' and the JTAG_RST# pin is high). The.." "0,1" newline bitfld.long 0x8 1.--2. "DBG_PIN_CFG,This field determines which pins are affected by the TRST# debug enable pin. 3=Reserved 2=The pins associated with the JTAG TCK and TMS switch to the debug interface when TRST# is de-asserted high. The pins associated with TDI.." "0: All four pins associated with JTAG,1: The pins associated with the JTAG TCK,2: The pins associated with the JTAG TCK and TMS..,3: Reserved" newline bitfld.long 0x8 0. "JTAG_EN,DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug port. 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e. the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state) 1= JTAG/SWD port.." "0: JTAG/SWD port disabled,1: JTAG/SWD port enabled" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x8 4. "BS_EN,This bit sets the boundary scan tap controller accessibility from JTAG port. 1= Boundary scan tap controller accessibile through JTAG Port. 0= Boundary scan tap controller not accessibile through JTAG Port." "0: Boundary scan tap controller not accessibile..,1: Boundary scan tap controller accessibile through.." newline bitfld.long 0x8 3. "JTAG_PU_EN,If this bit is set to '1b' internal pull-up resistors are automatically enabled on the appropriate debugging port wires whenever the debug port is enabled (the DEBUG_EN bit in this register is '1b' and the JTAG_RST# pin is high). The.." "0,1" newline bitfld.long 0x8 1.--2. "DBG_PIN_CFG,This field determines which pins are affected by the TRST# debug enable pin. 3=Reserved 2=The pins associated with the JTAG TCK and TMS switch to the debug interface when TRST# is de-asserted high. The pins associated with TDI.." "0: All four pins associated with JTAG,1: The pins associated with the JTAG TCK,2: The pins associated with the JTAG TCK and TMS..,3: Reserved" newline bitfld.long 0x8 0. "JTAG_EN,DEBUG_EN (JTAG_EN) This bit enables the JTAG/SWD debug port. 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e. the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state) 1= JTAG/SWD port.." "0: JTAG/SWD port disabled,1: JTAG/SWD port enabled" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x8 4. "BSP_EN,This bit sets the boundary scan tap controller accessibility from JTAG port.\n 1= Boundary scan tap controller accessibile through JTAG Port.\n 0= Boundary scan tap controller not accessibile through JTAG Port.\n" "0: Boundary scan tap controller not accessibile..,1: Boundary scan tap controller accessibile through.." newline endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x8 3. "PU_EN,If this bit is set to '1b' internal pull-up resistors are automatically enabled on the appropriate debugging port\n wires whenever the debug port is enabled (the DEBUG_EN bit in this register is '1b' and the JTAG_RST# pin is high). The.." "0,1" newline bitfld.long 0x8 1.--2. "PIN_CFG,This field determines which pins are affected by the TRST# debug enable pin.3=Reserved\n 2=The pins associated with the JTAG TCK and TMS switch to the debug interface when TRST# is de-asserted high. The pins\n associated with.." "0: All four pins associated with JTAG,1: The pins associated with the JTAG TCK,2: The pins associated with the JTAG TCK and TMS..,3: Reserved\n" newline bitfld.long 0x8 0. "EN,EN (JTAG_EN) This bit enables the JTAG/SWD debug port.\n 0= JTAG/SWD port disabled. JTAG/SWD cannot be enabled (i.e. the TRST# pin is ignored and the JTAG signals remain in their non-JTAG state)\n 1= JTAG/SWD port enabled. A high on.." "0: JTAG/SWD port disabled,1: JTAG/SWD port enabled" endif line.long 0xC "OTP_LOCK,OTP Lock" sif (cpuis("CEC1734?2HW*")) bitfld.long 0xC 8. "SCUR_MBX_LOCK,Secure Mailbox LOCK. 0 = Not Locked. 1 = Write Locked." "0: Not Locked,1: Write Locked" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0xC 8. "SCUR_MBX_LOCK,Secure Mailbox LOCK. 0 = Not Locked. 1 = Write Locked." "0: Not Locked,1: Write Locked" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0xC 8. "SCUR_MBX_LOCK,Secure Mailbox LOCK. 0 = Not Locked. 1 = Write Locked." "0: Not Locked,1: Write Locked" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0xC 8. "SCUR_MBX_LOCK,Secure Mailbox LOCK. 0 = Not Locked. 1 = Write Locked." "0: Not Locked,1: Write Locked" newline endif sif (cpuis("CEC1702*")) bitfld.long 0xC 4. "PUB_KEY_LOCK,This bit controls access to the Public Key region of the eFuse memory bytes 128 to 191. Once written this bit becomes Read Only.\n If the JTAG_EN bit is 1 (enabled) the Public Key is inaccessible independent of the state of this.." "0: The Public Key is accessible,1: The Public Key is inaccessible" newline bitfld.long 0xC 3. "USER_OTP_LOCK,This bit controls access to the User region of the eFuse memory bytes 192 to 511. Once written this bit becomes Read Only.\n If the JTAG_EN bit is 1 (enabled) the User region is inaccessible independent of the state of this.." "0: The User region is accessible,1: The User region is inaccessible" newline bitfld.long 0xC 2. "PRIV_KEY_LOCK,This bit controls access to Private Key region of the eFuse memory bytes 0 to 31. Once written this bit becomes Read Only.\n If the JTAG_EN bit is 1 (enabled) the Private Key is inaccessible independent of the state of this.." "0: The Private Key is accessible,1: The Private Key is inaccessible" newline bitfld.long 0xC 1. "MCHIP_LOCK,This bit controls access to Microchip region of the eFuse memory bytes 32 to 127. Once written this bit becomes Read Only.\n If the JTAG_EN bit is 1 (enabled) the Private Key is inaccessible independent of the state of this bit.\n.." "0: The Microchip region is accessible,1: The Microchip region is inaccessible" newline endif sif (cpuis("CEC1712*")) bitfld.long 0xC 2. "VBAT_REG_LOCK,VBAT REG LOCK.\n 0 = Not Locked.\n 1 = Locked.\n" "0: Not Locked,1: Locked" newline bitfld.long 0xC 1. "VBAT_RAM_LOCK,VBAT RAM LOCK bit.\n 0 = Not Locked.\n 1 = Locked.\n" "0: Not Locked,1: Locked" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0xC 2. "VBAT_REG_LOCK,VBAT REG LOCK. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline bitfld.long 0xC 1. "VBAT_RAM_LOCK,VBAT RAM LOCK bit. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0xC 2. "VBAT_REG_LOCK,VBAT REG LOCK. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline bitfld.long 0xC 1. "VBAT_RAM_LOCK,VBAT RAM LOCK bit. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0xC 2. "VBAT_REG_LOCK,VBAT REG LOCK. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline bitfld.long 0xC 1. "VBAT_RAM_LOCK,VBAT RAM LOCK bit. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0xC 2. "VBAT_REG_LOCK,VBAT REG LOCK. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline bitfld.long 0xC 1. "VBAT_RAM_LOCK,VBAT RAM LOCK bit. 0 = Not Locked. 1 = Locked." "0: Not Locked,1: Locked" newline endif bitfld.long 0xC 0. "TEST,Test" "0,1" line.long 0x10 "WDT_CNT,WDT Event Count [3:0] WDT_COUNT (WDT_COUNT) These EC R/W bits are cleared to 0 on VCC1 POR.\n but not on a WDT Note: This field is written by Boot ROM firmware to indicate the number of times a WDT fired before loading a good EC code image." line.long 0x14 "AESH_BSWAP_CTRL,AES HASH Byte Swap Control Register." bitfld.long 0x14 5.--7. "OP_BLK_SWAP_EN,Used to enable word swap on a DWORD during AHB write from AES / HASH block\n 4=Swap 32-bit doublewords in 128-byte blocks\n 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus references issued in the.." "0: Disable,1: Swap doublewords in 8-byte blocks,2: Swap doublewords in 16-byte blocks,3: Swap doublewords in 64-byte blocks,4: Swap 32-bit doublewords in 128-byte blocks\n,?,?,?" newline bitfld.long 0x14 2.--4. "IP_BLK_SWAP_EN,Used to enable word swap on a DWORD during AHB read from AES / HASH block\n 4=Swap 32-bit doublewords in 128-byte blocks\n 3=Swap doublewords in 64-byte blocks. Useful for SHA-256. Bus references issued in the order.." "0: Disable,1: Swap doublewords in 8-byte blocks,2: Swap doublewords in 16-byte blocks,3: Swap doublewords in 64-byte blocks,4: Swap 32-bit doublewords in 128-byte blocks\n,?,?,?" newline bitfld.long 0x14 1. "OP_BYTE_SWAP_EN,Used to enable byte swap on a DWORD during AHB write from AES / HASH block: 1=Enable; 0=Disable." "0: Disable,1: Enable" newline bitfld.long 0x14 0. "IP_BYTE_SWAP_EN,Used to enable byte swap on a DWORD during AHB read from AES / HASH block: 1=Enable; 0=Disable." "0: Disable,1: Enable" sif (cpuis("CEC1702*")) group.long 0x38++0x3 line.long 0x0 "SYS_SHUTDWN_RST,AES HASH Byte Swap Control Register." bitfld.long 0x0 0. "SYS_SHDN_RST,When this bit is asserted 1 the SYS_SHDN# output is deasserted" "0,1" endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) group.long 0x40++0x3 line.long 0x0 "PECI_DIS,PECI Disable" sif (cpuis("CEC1702*")) bitfld.long 0x0 0. "PECI_DISABLE,When this bit is asserted 1 it disables the PECI pads to reduce leakage." "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0x0 0. "P_DIS,When this bit is asserted ('1') it disables the PECI pads to reduce leakage." "0,1" endif group.long 0x5C++0x3 line.long 0x0 "CRYPTO_SRST,System Shutdown Reset" sif (cpuis("CEC1702*")) bitfld.long 0x0 2. "AES_HASH_SFT_RST,When this bit is asserted 1 the AES and Hash blocks are reset." "0,1" bitfld.long 0x0 1. "PUB_KEY_SFT_RST,When this bit is asserted 1 the Public Key block is reset." "0,1" newline bitfld.long 0x0 0. "RNG_SFT_RST,When this bit is asserted 1 the Random Number Generator block is reset." "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0x0 2. "AES_HASH,When this bit is asserted ('1') the AES and Hash blocks are reset." "0,1" newline bitfld.long 0x0 1. "PUB_KEY,When this bit is asserted ('1') the Public Key block is reset." "0,1" bitfld.long 0x0 0. "RNG,When this bit is asserted ('1') the Random Number Generator block is reset." "0,1" endif group.long 0x70++0x3 line.long 0x0 "JTAG_MCFG,JTAG Master Configuration Register" bitfld.long 0x0 3. "MAS_SLV,This bit controls the direction of the JTAG port. 1=The JTAG Port is configured as a Master\n 0=The JTAG Port is configures as a Slave." "0: The JTAG Port is configures as a Slave,1: The JTAG Port is configured as a Master\n" bitfld.long 0x0 0.--2. "JTM_CLK,This field determines the JTAG Master clock rate derived from the 48MHz master clock.\n 7=375KHz; 6=750KHz; 5=1.5Mhz; 4=3Mhz; 3=6Mhz; 2=12Mhz; 1=24MHz; 0=Reserved." "0: Reserved,1: 24MHz,2: 12Mhz,3: 6Mhz,4: 3Mhz,5: 1,6: 750KHz,7: 375KHz" rgroup.long 0x74++0x3 line.long 0x0 "JTAG_MSTS,JTAG Master Status Register" bitfld.long 0x0 0. "JTM_DONE,This bit is set to '1b' when the JTAG Master Command Register is written. It becomes '0b' when shifting has completed.\n Software can poll this bit to determine when a command has completed and it is therefore safe to remove the data in.." "0,1" group.long 0x78++0xF line.long 0x0 "JTAG_MTDO,JTAG Master TDO Register" hexmask.long 0x0 0.--31. 1. "JTM_TDO,When the JTAG Master Command Register is written from 1 to 32 bits are shifted into this register starting with bit 0 \n from the JTAG_TDO pin. Shifting is at the rate determined by the JTM_CLK field in the JTAG Master Configuration.." line.long 0x4 "JTAG_MTDI,JTAG Master TDI Register" hexmask.long 0x4 0.--31. 1. "JTM_TDI,When the JTAG Master Command Register is written from 1 to 32 bits are shifted out of this register starting with bit 0 \n onto the JTAG_TDI pin. Shifting is at the rate determined by the JTM_CLK field in the JTAG Master Configuration.." line.long 0x8 "JTAG_MTMS,JTAG Master TMS Register" hexmask.long 0x8 0.--31. 1. "JTM_TMS,When the JTAG Master Command Register is written from 1 to 32 bits are shifted out of this register starting with bit 0 \n onto the JTAG_TMS pin. Shifting is at the rate determined by the JTM_CLK field in the JTAG Master Configuration.." line.long 0xC "JTAG_MCMD,JTAG Master Command Register" hexmask.long.byte 0xC 0.--4. 1. "JTM_COUNT,If the JTAG Port is configured as a Master writing this register starts clocking and shifting on the JTAG port. The JTAG\n Master port will shift JTM_COUNT+1 times so writing a '0h' will shift 1 bit and writing '31h' will shift 32.." endif sif (cpuis("CEC1712*")) rgroup.long 0x4C++0x3 line.long 0x0 "STAP_TMIR,This register is a mirror of the Boot Control Register.\n" bitfld.long 0x0 3. "INT_SPI_RECOV,This register bit tells BOOT ROM that SPI FLASH Recovery Mode is entered.\n" "0,1" bitfld.long 0x0 2. "BS_STATUS,This register bit tells BOOT ROM about the Boundary Scan Status.\n" "0,1" newline bitfld.long 0x0 1. "VLD_MODE,This is the mirror of the Validation MODE (bit 1) of Boot Control Register.\n This register bit tells BOOT ROM to enter the Validation mode.\n" "0,1" bitfld.long 0x0 0. "QA_MODE,This is the mirror of the QA_MODE (bit 0) of Boot Control Register.\n This register bit tells BOOT ROM to enter the QA mode.\n" "0,1" group.byte 0x54++0x0 line.byte 0x0 "BROM_STS,This register contains the VTR Reset Status for BOOT ROM.\n" bitfld.byte 0x0 1. "WDT_EVT,This bit contains the WDT Event Status for BOOT ROM usage.\n 1= WDT event occured.\n 0= WDT event did not occured.\n This registe is R/W1C (read / write 1 to clear)." "0: WDT event did not occured,1: WDT event occured" bitfld.byte 0x0 0. "VTR_RST_STS,This bit contains the RESET_SYS Status for BOOT ROM usage.\n 1= RESET_SYS event occured.\n 0= RESET_SYS event did not occured.\n This registe is R/W1C (read / write 1 to clear)." "0: RESET_SYS event did not occured,1: RESET_SYS event occured" endif group.long 0x64++0x3 line.long 0x0 "GPIO_BANK_PWR,GPIO Bank Power Register" bitfld.long 0x0 7. "GPIO_BANK_PWR_LOCK,GPIO Bank Power Lock. 0: VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit are R/W\n 1 = VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit are Read Only." "0: VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit..,1: VTR_LEVEL bits[2:0] and GPIO Bank Power Lock bit.." newline sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x0 2. "VTR_LVL3,Voltage value on VTR3. This bit is set by hardware after a VTR Power On Reset but may be overridden by software.\n It must be set by software if the VTR power rail is not active when RESET_SYS is de-asserted. Write access is.." "0: VTR3 is powered by 1,1: VTR3 is powered by 3" newline endif bitfld.long 0x0 1. "VTR_LVL2,Voltage value on VTR2. This bit is set by hardware after a VTR Power On Reset but may be overridden by software.\n It must be set by software if the VTR power rail is not active when RESET_SYS is de-asserted. Write access is determined.." "0: VTR2 is powered by 1,1: VTR2 is powered by 3" newline sif (cpuis("CEC1702*")) bitfld.long 0x0 0. "VTR_LVL1,Voltage value on VTR1. This bit is set by hardware after a VTR Power On Reset but may be overridden by software.\n It must be set by software if the VTR power rail is not active when RESET_SYS is de-asserted. Write access is.." "0: VTR1 is powered by 1,1: VTR1 is powered by 3" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 0. "TEST,This bit must be programmed to 0h for proper operation of the device.\n" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 0. "TEST,This bit must be programmed to 0h for proper operation of the device." "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 0. "TEST,This bit must be programmed to 0h for proper operation of the device." "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 0. "TEST,This bit must be programmed to 0h for proper operation of the device." "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 0. "TEST,This bit must be programmed to 0h for proper operation of the device." "0,1" endif sif (cpuis("CEC1712*")) group.long 0x180++0xF line.long 0x0 "FW_SCR0,BOOT ROM Scratch 0 Register" hexmask.long 0x0 0.--31. 1. "SCR0,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x4 "FW_SCR1,BOOT ROM Scratch 1 Register" hexmask.long 0x4 0.--31. 1. "SCR1,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0x8 "FW_SCR2,BOOT ROM Scratch 2 Register" hexmask.long 0x8 0.--31. 1. "SCR2,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." line.long 0xC "FW_SCR3,BOOT ROM Scratch 3 Register" hexmask.long 0xC 0.--31. 1. "SCR3,This field has no functionality other than storage. This register is aliased to ESPI Config Scratch Register." endif sif (cpuis("CEC1734?2HW*")) group.long 0x240++0xB line.long 0x0 "PD_MON_CTRL,PAD Monitor Control Register" bitfld.long 0x0 14. "VTR2_PROTECN,PAD Monitor Override Protect N VTR2." "0,1" bitfld.long 0x0 13. "VTR2_INPT_DIS,PAD Monitor Override Input Disable VTR2. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 12. "OVRD_VTR2,PAD Monitor Override VTR2 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 8.--9. "CTRL_VTR2,Pad Monitor Control VTR2. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" newline bitfld.long 0x0 6. "VTR1_PROTECN,PAD Monitor Override Protect N VTR1." "0,1" bitfld.long 0x0 5. "VTR1_INPT_DIS,PAD Monitor Override Input Disable VTR1. 0=Normal Operation 1=input_disable" "0: Normal Operation,1: input_disable" newline bitfld.long 0x0 4. "OVRD_VTR1,PAD Monitor Override VTR1 0=Normal Operation 1=Override input_disable and pad_protect_n" "0: Normal Operation,1: Override input_disable and pad_protect_n" bitfld.long 0x0 0.--1. "CTRL_VTR1,Pad Monitor Control VTR1. 0=OFF 1=1ms delay 2=10ms delay 3=100ms delay" "0: OFF,1: 1ms delay,2: 10ms delay,3: 100ms delay" line.long 0x4 "PD_MON_INT_EN,PAD Monitor Interrupt Enable Register" bitfld.long 0x4 9. "VTR2_PU_INTEN,Pad Monitor VTR2 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 8. "VTR2_PD_INTEN,Pad Monitor VTR2 Power Down Interrupt Enable." "0,1" newline bitfld.long 0x4 1. "VTR1_PU_INTEN,Pad Monitor VTR1 Power Up Interrupt Enable" "0,1" bitfld.long 0x4 0. "VTR1_PD_INTEN,Pad Monitor VTR1 Power Down Interrupt Enable." "0,1" line.long 0x8 "PD_MON_STS,PAD Monitor Status Register" bitfld.long 0x8 15. "VTR2_CS_STS,Pad Monitor Current state VTR2" "0,1" bitfld.long 0x8 9. "VTR2_PU_STS,Pad Monitor VTR2 Power Up Status" "0,1" newline bitfld.long 0x8 8. "VTR2_PD_STS,Pad Monitor VTR2 Power Down Status" "0,1" bitfld.long 0x8 7. "VTR1_CS_STS,Pad Monitor Current state VTR1" "0,1" newline bitfld.long 0x8 1. "VTR1_PU_STS,Pad Monitor VTR1 Power Up Status" "0,1" bitfld.long 0x8 0. "VTR1_PD_STS,Pad Monitor VTR1 Power Down Status" "0,1" endif sif (cpuis("CEC1734?2ZW*")) group.long 0x248++0x3 line.long 0x0 "PD_MON_STS,PAD Monitor Status Register" bitfld.long 0x0 15. "VTR2_CS_STS,Pad Monitor Current state VTR2" "0,1" bitfld.long 0x0 9. "VTR2_PU_STS,Pad Monitor VTR2 Power Up Status" "0,1" newline bitfld.long 0x0 8. "VTR2_PD_STS,Pad Monitor VTR2 Power Down Status" "0,1" bitfld.long 0x0 7. "VTR1_CS_STS,Pad Monitor Current state VTR1" "0,1" newline bitfld.long 0x0 1. "VTR1_PU_STS,Pad Monitor VTR1 Power Up Status" "0,1" bitfld.long 0x0 0. "VTR1_PD_STS,Pad Monitor VTR1 Power Down Status" "0,1" endif sif (cpuis("CEC1736?2HW*")) group.long 0x248++0x3 line.long 0x0 "PD_MON_STS,PAD Monitor Status Register" bitfld.long 0x0 15. "VTR2_CS_STS,Pad Monitor Current state VTR2" "0,1" bitfld.long 0x0 9. "VTR2_PU_STS,Pad Monitor VTR2 Power Up Status" "0,1" newline bitfld.long 0x0 8. "VTR2_PD_STS,Pad Monitor VTR2 Power Down Status" "0,1" bitfld.long 0x0 7. "VTR1_CS_STS,Pad Monitor Current state VTR1" "0,1" newline bitfld.long 0x0 1. "VTR1_PU_STS,Pad Monitor VTR1 Power Up Status" "0,1" bitfld.long 0x0 0. "VTR1_PD_STS,Pad Monitor VTR1 Power Down Status" "0,1" endif sif (cpuis("CEC1736?2ZW*")) group.long 0x248++0x3 line.long 0x0 "PD_MON_STS,PAD Monitor Status Register" bitfld.long 0x0 15. "VTR2_CS_STS,Pad Monitor Current state VTR2" "0,1" bitfld.long 0x0 9. "VTR2_PU_STS,Pad Monitor VTR2 Power Up Status" "0,1" newline bitfld.long 0x0 8. "VTR2_PD_STS,Pad Monitor VTR2 Power Down Status" "0,1" bitfld.long 0x0 7. "VTR1_CS_STS,Pad Monitor Current state VTR1" "0,1" newline bitfld.long 0x0 1. "VTR1_PU_STS,Pad Monitor VTR1 Power Up Status" "0,1" bitfld.long 0x0 0. "VTR1_PD_STS,Pad Monitor VTR1 Power Down Status" "0,1" endif tree.end tree "ECIA (EC Interrupt Aggregator)" base ad:0x4000E000 sif (cpuis("CEC1702*")) repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x4000E000 ad:0x4000E014 ad:0x4000E028 ad:0x4000E03C ad:0x4000E050 ad:0x4000E064 ad:0x4000E078 ad:0x4000E08C ad:0x4000E0A0 ad:0x4000E0B4 ad:0x4000E0C8 ad:0x4000E0DC ad:0x4000E0F0 ad:0x4000E104 ad:0x4000E118 ad:0x4000E12C) tree "GIRQ[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "SRC,Status R/W1C" line.long 0x4 "EN_SET,Write to set source enables" rgroup.long ($2+0x8)++0x3 line.long 0x0 "RESULT,Read-only bitwise OR of Source and Enable" group.long ($2+0xC)++0x3 line.long 0x0 "EN_CLR,Write to clear source enables" tree.end repeat.end repeat 3. (list 0x10 0x11 0x12)(list ad:0x4000E140 ad:0x4000E154 ad:0x4000E168) tree "GIRQ[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "SRC,Status R/W1C" line.long 0x4 "EN_SET,Write to set source enables" rgroup.long ($2+0x8)++0x3 line.long 0x0 "RESULT,Read-only bitwise OR of Source and Enable" group.long ($2+0xC)++0x3 line.long 0x0 "EN_CLR,Write to clear source enables" tree.end repeat.end base ad:0x4000E000 endif sif (cpuis("CEC1712*")) group.long 0x0++0x7 line.long 0x0 "SRC8,GIRQ8 Source Register" line.long 0x4 "EN_SET8,GIRQ8 Enable Set Register" rgroup.long 0x8++0x3 line.long 0x0 "RESULT8,GIRQ8 Result Register" group.long 0xC++0x3 line.long 0x0 "EN_CLR8,GIRQ8 Enable Clear Register" group.long 0x14++0x7 line.long 0x0 "SRC9,GIRQ9 Source Register" line.long 0x4 "EN_SET9,GIRQ9 Enable Set Register" rgroup.long 0x1C++0x3 line.long 0x0 "RESULT9,GIRQ9 Result Register" group.long 0x20++0x3 line.long 0x0 "EN_CLR9,GIRQ9 Enable Clear Register" group.long 0x28++0x7 line.long 0x0 "SRC10,GIRQ10 Source Register" line.long 0x4 "EN_SET10,GIRQ10 Enable Set Register" rgroup.long 0x30++0x3 line.long 0x0 "RESULT10,GIRQ10 Result Register" group.long 0x34++0x3 line.long 0x0 "EN_CLR10,GIRQ10 Enable Clear Register" group.long 0x3C++0x7 line.long 0x0 "SRC11,GIRQ11 Source Register" line.long 0x4 "EN_SET11,GIRQ11 Enable Set Register" rgroup.long 0x44++0x3 line.long 0x0 "RESULT11,GIRQ11 Result Register" group.long 0x48++0x3 line.long 0x0 "EN_CLR11,GIRQ11 Enable Clear Register" group.long 0x50++0x7 line.long 0x0 "SRC12,GIRQ12 Source Register" line.long 0x4 "EN_SET12,GIRQ12 Enable Set Register" rgroup.long 0x58++0x3 line.long 0x0 "RESULT12,GIRQ12 Result Register" group.long 0x5C++0x3 line.long 0x0 "EN_CLR12,GIRQ12 Enable Clear Register" group.long 0x64++0x7 line.long 0x0 "SRC13,GIRQ13 Source Register" line.long 0x4 "EN_SET13,GIRQ13 Enable Set Register" rgroup.long 0x6C++0x3 line.long 0x0 "RESULT13,GIRQ13 Result Register" group.long 0x70++0x3 line.long 0x0 "EN_CLR13,GIRQ13 Enable Clear Register" group.long 0x78++0x7 line.long 0x0 "SRC14,GIRQ14 Source Register" line.long 0x4 "EN_SET14,GIRQ14 Enable Set Register" rgroup.long 0x80++0x3 line.long 0x0 "RESULT14,GIRQ14 Result Register" group.long 0x84++0x3 line.long 0x0 "EN_CLR14,GIRQ14 Enable Clear Register" group.long 0x8C++0x7 line.long 0x0 "SRC15,GIRQ15 Source Register" line.long 0x4 "EN_SET15,GIRQ15 Enable Set Register" rgroup.long 0x94++0x3 line.long 0x0 "RESULT15,GIRQ15 Result Register" group.long 0x98++0x3 line.long 0x0 "EN_CLR15,GIRQ15 Enable Clear Register" group.long 0xA0++0x7 line.long 0x0 "SRC16,GIRQ16 Source Register" line.long 0x4 "EN_SET16,GIRQ16 Enable Set Register" rgroup.long 0xA8++0x3 line.long 0x0 "RESULT16,GIRQ16 Result Register" group.long 0xAC++0x3 line.long 0x0 "EN_CLR16,GIRQ16 Enable Clear Register" group.long 0xB4++0x7 line.long 0x0 "SRC17,GIRQ17 Source Register" line.long 0x4 "EN_SET17,GIRQ17 Enable Set Register" rgroup.long 0xBC++0x3 line.long 0x0 "RESULT17,GIRQ17 Result Register" group.long 0xC0++0x3 line.long 0x0 "EN_CLR17,GIRQ17 Enable Clear Register" group.long 0xC8++0x7 line.long 0x0 "SRC18,GIRQ18 Source Register" line.long 0x4 "EN_SET18,GIRQ18 Enable Set Register" rgroup.long 0xD0++0x3 line.long 0x0 "RESULT18,GIRQ18 Result Register" group.long 0xD4++0x3 line.long 0x0 "EN_CLR18,GIRQ18 Enable Clear Register" group.long 0xDC++0x7 line.long 0x0 "SRC19,GIRQ19 Source Register" line.long 0x4 "EN_SET19,GIRQ19 Enable Set Register" rgroup.long 0xE4++0x3 line.long 0x0 "RESULT19,GIRQ19 Result Register" group.long 0xE8++0x3 line.long 0x0 "EN_CLR19,GIRQ19 Enable Clear Register" group.long 0xF0++0x7 line.long 0x0 "SRC20,GIRQ20 Source Register" line.long 0x4 "EN_SET20,GIRQ20 Enable Set Register" rgroup.long 0xF8++0x3 line.long 0x0 "RESULT20,GIRQ20 Result Register" group.long 0xFC++0x3 line.long 0x0 "EN_CLR20,GIRQ20 Enable Clear Register" group.long 0x104++0x7 line.long 0x0 "SRC21,GIRQ21 Source Register" line.long 0x4 "EN_SET21,GIRQ21 Enable Set Register" rgroup.long 0x10C++0x3 line.long 0x0 "RESULT21,GIRQ21 Result Register" group.long 0x110++0x3 line.long 0x0 "EN_CLR21,GIRQ21 Enable Clear Register" group.long 0x118++0x7 line.long 0x0 "SRC22,GIRQ22 Source Register" line.long 0x4 "EN_SET22,GIRQ22 Enable Set Register" rgroup.long 0x120++0x3 line.long 0x0 "RESULT22,GIRQ22 Result Register" group.long 0x124++0x3 line.long 0x0 "EN_CLR22,GIRQ22 Enable Clear Register" group.long 0x12C++0x7 line.long 0x0 "SRC23,GIRQ23 Source Register" line.long 0x4 "EN_SET23,GIRQ23 Enable Set Register" rgroup.long 0x134++0x3 line.long 0x0 "RESULT23,GIRQ23 Result Register" group.long 0x138++0x3 line.long 0x0 "EN_CLR23,GIRQ23 Enable Clear Register" group.long 0x140++0x7 line.long 0x0 "SRC24,GIRQ24 Source Register" line.long 0x4 "EN_SET24,GIRQ24 Enable Set Register" rgroup.long 0x148++0x3 line.long 0x0 "RESULT24,GIRQ24 Result Register" group.long 0x14C++0x3 line.long 0x0 "EN_CLR24,GIRQ24 Enable Clear Register" group.long 0x154++0x7 line.long 0x0 "SRC25,GIRQ25 Source Register" line.long 0x4 "EN_SET25,GIRQ25 Enable Set Register" rgroup.long 0x15C++0x3 line.long 0x0 "RESULT25,GIRQ25 Result Register" group.long 0x160++0x3 line.long 0x0 "EN_CLR25,GIRQ25 Enable Clear Register" group.long 0x168++0x7 line.long 0x0 "SRC26,GIRQ26 Source Register" line.long 0x4 "EN_SET26,GIRQ26 Enable Set Register" rgroup.long 0x170++0x3 line.long 0x0 "RESULT26,GIRQ26 Result Register" group.long 0x174++0x3 line.long 0x0 "EN_CLR26,GIRQ26 Enable Clear Register" endif sif (cpuis("CEC1734?2HW*")) group.long 0x0++0x7 line.long 0x0 "SRC8,GIRQ8 SOURCE" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" line.long 0x4 "EN_SET8,GIRQ8 ENABLE SET" bitfld.long 0x4 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x4 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x4 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x4 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x4 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x4 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x4 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x4 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x4 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x4 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x4 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x4 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x4 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x4 0. "GPIO140,GPIO 140" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RESULT8,GIRQ8 RESULT" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0xC++0x3 line.long 0x0 "EN_CLR8,GIRQ8 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0x14++0x7 line.long 0x0 "SRC9,GIRQ9 SOURCE" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" line.long 0x4 "EN_SET9,GIRQ9 ENABLE SET" bitfld.long 0x4 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x4 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x4 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x4 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x4 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x4 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x4 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x4 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x4 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x4 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x4 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x4 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x4 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x4 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x4 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x4 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x4 4. "GPIO104,GPIO 104" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "RESULT9,GIRQ9 RESULT" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x20++0x3 line.long 0x0 "EN_CLR9,GIRQ9 ENABLE CLEAR" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x28++0x7 line.long 0x0 "SRC10,GIRQ10 SOURCE" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" line.long 0x4 "EN_SET10,GIRQ10 ENABLE SET" bitfld.long 0x4 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x4 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x4 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x4 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x4 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x4 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x4 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x4 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x4 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x4 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x4 5. "GPIO045,GPIO 045" "0,1" rgroup.long 0x30++0x3 line.long 0x0 "RESULT10,GIRQ10 RESULT" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x34++0x3 line.long 0x0 "EN_CLR10,GIRQ10 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x3C++0x7 line.long 0x0 "SRC11,GIRQ11 SOURCE" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" line.long 0x4 "EN_SET11,GIRQ11 ENABLE SET" bitfld.long 0x4 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x4 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x4 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x4 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x4 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x4 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x4 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x4 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x4 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x4 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x4 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x4 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x4 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x4 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x4 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x4 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x4 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x4 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x4 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x4 0. "GPIO000,GPIO 000" "0,1" rgroup.long 0x44++0x3 line.long 0x0 "RESULT11,GIRQ11 RESULT" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x48++0x3 line.long 0x0 "EN_CLR11,GIRQ11 ENABLE CLEAR" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x50++0x7 line.long 0x0 "SRC12,GIRQ12 SOURCE" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" line.long 0x4 "EN_SET12,GIRQ12 ENABLE SET" bitfld.long 0x4 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x4 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x4 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x4 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x4 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x4 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x4 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x4 0. "GPIO200,GPIO 200" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "RESULT12,GIRQ12 RESULT" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x5C++0x3 line.long 0x0 "EN_CLR12,GIRQ12 ENABLE CLEAR" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x64++0x7 line.long 0x0 "SRC13,GIRQ13 SOURCE" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" line.long 0x4 "EN_SET13,GIRQ13 ENABLE SET" bitfld.long 0x4 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x4 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x4 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x4 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x4 0. "I2CSMB0,I2CSMB0" "0,1" rgroup.long 0x6C++0x3 line.long 0x0 "RESULT13,GIRQ13 RESULT" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x70++0x3 line.long 0x0 "EN_CLR13,GIRQ13 ENABLE CLEAR" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x78++0x7 line.long 0x0 "SRC14,GIRQ14 SOURCE" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" line.long 0x4 "EN_SET14,GIRQ14 ENABLE SET" bitfld.long 0x4 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x4 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x4 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x4 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x4 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x4 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x4 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x4 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x4 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x4 0. "DMA_CH00,DMA CH00" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "RESULT14,GIRQ14 RESULT" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x84++0x3 line.long 0x0 "EN_CLR14,GIRQ14 ENABLE CLEAR" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x8C++0x7 line.long 0x0 "SRC15,GIRQ15 SOURCE" bitfld.long 0x0 0. "UART0,UART0" "0,1" line.long 0x4 "EN_SET15,GIRQ15 ENABLE SET" bitfld.long 0x4 0. "UART0,UART0" "0,1" rgroup.long 0x94++0x3 line.long 0x0 "RESULT15,GIRQ15 RESULT" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0x98++0x3 line.long 0x0 "EN_CLR15,GIRQ15 ENABLE CLEAR" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0xA0++0x7 line.long 0x0 "SRC16,GIRQ16 SOURCE" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" line.long 0x4 "EN_SET16,GIRQ16 ENABLE SET" bitfld.long 0x4 4. "HASH,HASH" "0,1" bitfld.long 0x4 3. "AES,AES" "0,1" newline bitfld.long 0x4 2. "RNG,RNG" "0,1" bitfld.long 0x4 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x4 0. "PKE_ERR,PKE ERR" "0,1" rgroup.long 0xA8++0x3 line.long 0x0 "RESULT16,GIRQ16 RESULT" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xAC++0x3 line.long 0x0 "EN_CLR16,GIRQ16 ENABLE CLEAR" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xB4++0x7 line.long 0x0 "SRC17,GIRQ17 SOURCE" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" line.long 0x4 "EN_SET17,GIRQ17 ENABLE SET" bitfld.long 0x4 14. "LED1,Breating LED1" "0,1" bitfld.long 0x4 13. "LED0,Breating LED0" "0,1" rgroup.long 0xBC++0x3 line.long 0x0 "RESULT17,GIRQ17 RESULT" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC0++0x3 line.long 0x0 "EN_CLR17,GIRQ17 ENABLE CLEAR" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC8++0x7 line.long 0x0 "SRC18,GIRQ18 SOURCE" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" line.long 0x4 "EN_SET18,GIRQ18 ENABLE SET" bitfld.long 0x4 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x4 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x4 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x4 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x4 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x4 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x4 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x4 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x4 20. "CCT,CCT" "0,1" bitfld.long 0x4 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x4 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x4 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x4 0. "SPT0,SPT0" "0,1" rgroup.long 0xD0++0x3 line.long 0x0 "RESULT18,GIRQ18 RESULT" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xD4++0x3 line.long 0x0 "EN_CLR18,GIRQ18 ENABLE CLEAR" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xDC++0x7 line.long 0x0 "SRC19,GIRQ19 SOURCE" line.long 0x4 "EN_SET19,GIRQ19 ENABLE SET" rgroup.long 0xE4++0x3 line.long 0x0 "RESULT19,GIRQ19 RESULT" group.long 0xE8++0x3 line.long 0x0 "EN_CLR19,GIRQ19 ENABLE CLEAR" group.long 0xF0++0x7 line.long 0x0 "SRC20,GIRQ20 SOURCE" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" line.long 0x4 "EN_SET20,GIRQ20 ENABLE SET" bitfld.long 0x4 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x4 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x4 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x4 8. "IMSPI,IMSPI" "0,1" rgroup.long 0xF8++0x3 line.long 0x0 "RESULT20,GIRQ20 RESULT" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0xFC++0x3 line.long 0x0 "EN_CLR20,GIRQ20 ENABLE CLEAR" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0x104++0x7 line.long 0x0 "SRC21,GIRQ21 SOURCE" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" line.long 0x4 "EN_SET21,GIRQ21 ENABLE SET" bitfld.long 0x4 24. "EMC,EMC" "0,1" bitfld.long 0x4 2. "WDT,WDT" "0,1" rgroup.long 0x10C++0x3 line.long 0x0 "RESULT21,GIRQ21 RESULT" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x110++0x3 line.long 0x0 "EN_CLR21,GIRQ21 ENABLE CLEAR" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x118++0x7 line.long 0x0 "SRC22,GIRQ22 SOURCE" line.long 0x4 "EN_SET22,GIRQ22 ENABLE SET" rgroup.long 0x120++0x3 line.long 0x0 "RESULT22,GIRQ22 RESULT" group.long 0x124++0x3 line.long 0x0 "EN_CLR22,GIRQ22 ENABLE CLEAR" group.long 0x12C++0x7 line.long 0x0 "SRC23,GIRQ23 SOURCE" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" line.long 0x4 "EN_SET23,GIRQ23 ENABLE SET" bitfld.long 0x4 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x4 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x4 14. "SWI3,SWI3" "0,1" bitfld.long 0x4 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x4 12. "SWI1,SWI1" "0,1" bitfld.long 0x4 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x4 10. "RTMR,RTMR" "0,1" bitfld.long 0x4 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x4 4. "TIMER32_0,TIMER32_0" "0,1" rgroup.long 0x134++0x3 line.long 0x0 "RESULT23,GIRQ23 RESULT" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x138++0x3 line.long 0x0 "EN_CLR23,GIRQ23 ENABLE CLEAR" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x140++0x7 line.long 0x0 "SRC24,GIRQ24 SOURCE" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" line.long 0x4 "EN_SET24,GIRQ24 ENABLE SET" bitfld.long 0x4 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x4 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x4 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x4 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x4 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x4 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "RESULT24,GIRQ24 RESULT" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x14C++0x3 line.long 0x0 "EN_CLR24,GIRQ24 ENABLE CLEAR" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x154++0x7 line.long 0x0 "SRC25,GIRQ25 SOURCE" line.long 0x4 "EN_SET25,GIRQ25 ENABLE SET" rgroup.long 0x15C++0x3 line.long 0x0 "RESULT25,GIRQ25 RESULT" group.long 0x160++0x3 line.long 0x0 "EN_CLR25,GIRQ25 ENABLE CLEAR" group.long 0x168++0x7 line.long 0x0 "SRC26,GIRQ26 SOURCE" bitfld.long 0x0 11. "GPIO253,GPIO253" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" line.long 0x4 "EN_SET26,GIRQ26 ENABLE SET" bitfld.long 0x4 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x4 8. "GPIO250,GPIO250" "0,1" rgroup.long 0x170++0x3 line.long 0x0 "RESULT26,GIRQ26 RESULT" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" group.long 0x174++0x3 line.long 0x0 "EN_CLR26,GIRQ26 ENABLE CLEAR" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" endif sif (cpuis("CEC1734?2ZW*")) group.long 0x0++0x7 line.long 0x0 "SRC8,GIRQ8 SOURCE" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" line.long 0x4 "EN_SET8,GIRQ8 ENABLE SET" bitfld.long 0x4 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x4 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x4 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x4 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x4 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x4 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x4 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x4 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x4 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x4 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x4 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x4 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x4 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x4 0. "GPIO140,GPIO 140" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RESULT8,GIRQ8 RESULT" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0xC++0x3 line.long 0x0 "EN_CLR8,GIRQ8 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0x14++0x7 line.long 0x0 "SRC9,GIRQ9 SOURCE" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" line.long 0x4 "EN_SET9,GIRQ9 ENABLE SET" bitfld.long 0x4 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x4 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x4 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x4 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x4 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x4 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x4 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x4 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x4 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x4 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x4 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x4 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x4 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x4 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x4 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x4 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x4 4. "GPIO104,GPIO 104" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "RESULT9,GIRQ9 RESULT" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x20++0x3 line.long 0x0 "EN_CLR9,GIRQ9 ENABLE CLEAR" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x28++0x7 line.long 0x0 "SRC10,GIRQ10 SOURCE" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" line.long 0x4 "EN_SET10,GIRQ10 ENABLE SET" bitfld.long 0x4 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x4 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x4 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x4 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x4 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x4 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x4 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x4 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x4 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x4 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x4 5. "GPIO045,GPIO 045" "0,1" rgroup.long 0x30++0x3 line.long 0x0 "RESULT10,GIRQ10 RESULT" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x34++0x3 line.long 0x0 "EN_CLR10,GIRQ10 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x3C++0x7 line.long 0x0 "SRC11,GIRQ11 SOURCE" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" line.long 0x4 "EN_SET11,GIRQ11 ENABLE SET" bitfld.long 0x4 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x4 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x4 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x4 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x4 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x4 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x4 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x4 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x4 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x4 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x4 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x4 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x4 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x4 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x4 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x4 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x4 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x4 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x4 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x4 0. "GPIO000,GPIO 000" "0,1" rgroup.long 0x44++0x3 line.long 0x0 "RESULT11,GIRQ11 RESULT" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x48++0x3 line.long 0x0 "EN_CLR11,GIRQ11 ENABLE CLEAR" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x50++0x7 line.long 0x0 "SRC12,GIRQ12 SOURCE" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" line.long 0x4 "EN_SET12,GIRQ12 ENABLE SET" bitfld.long 0x4 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x4 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x4 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x4 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x4 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x4 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x4 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x4 0. "GPIO200,GPIO 200" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "RESULT12,GIRQ12 RESULT" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x5C++0x3 line.long 0x0 "EN_CLR12,GIRQ12 ENABLE CLEAR" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x64++0x7 line.long 0x0 "SRC13,GIRQ13 SOURCE" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" line.long 0x4 "EN_SET13,GIRQ13 ENABLE SET" bitfld.long 0x4 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x4 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x4 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x4 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x4 0. "I2CSMB0,I2CSMB0" "0,1" rgroup.long 0x6C++0x3 line.long 0x0 "RESULT13,GIRQ13 RESULT" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x70++0x3 line.long 0x0 "EN_CLR13,GIRQ13 ENABLE CLEAR" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x78++0x7 line.long 0x0 "SRC14,GIRQ14 SOURCE" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" line.long 0x4 "EN_SET14,GIRQ14 ENABLE SET" bitfld.long 0x4 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x4 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x4 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x4 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x4 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x4 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x4 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x4 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x4 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x4 0. "DMA_CH00,DMA CH00" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "RESULT14,GIRQ14 RESULT" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x84++0x3 line.long 0x0 "EN_CLR14,GIRQ14 ENABLE CLEAR" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x8C++0x7 line.long 0x0 "SRC15,GIRQ15 SOURCE" bitfld.long 0x0 0. "UART0,UART0" "0,1" line.long 0x4 "EN_SET15,GIRQ15 ENABLE SET" bitfld.long 0x4 0. "UART0,UART0" "0,1" rgroup.long 0x94++0x3 line.long 0x0 "RESULT15,GIRQ15 RESULT" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0x98++0x3 line.long 0x0 "EN_CLR15,GIRQ15 ENABLE CLEAR" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0xA0++0x7 line.long 0x0 "SRC16,GIRQ16 SOURCE" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" line.long 0x4 "EN_SET16,GIRQ16 ENABLE SET" bitfld.long 0x4 4. "HASH,HASH" "0,1" bitfld.long 0x4 3. "AES,AES" "0,1" newline bitfld.long 0x4 2. "RNG,RNG" "0,1" bitfld.long 0x4 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x4 0. "PKE_ERR,PKE ERR" "0,1" rgroup.long 0xA8++0x3 line.long 0x0 "RESULT16,GIRQ16 RESULT" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xAC++0x3 line.long 0x0 "EN_CLR16,GIRQ16 ENABLE CLEAR" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xB4++0x7 line.long 0x0 "SRC17,GIRQ17 SOURCE" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" line.long 0x4 "EN_SET17,GIRQ17 ENABLE SET" bitfld.long 0x4 14. "LED1,Breating LED1" "0,1" bitfld.long 0x4 13. "LED0,Breating LED0" "0,1" rgroup.long 0xBC++0x3 line.long 0x0 "RESULT17,GIRQ17 RESULT" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC0++0x3 line.long 0x0 "EN_CLR17,GIRQ17 ENABLE CLEAR" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC8++0x7 line.long 0x0 "SRC18,GIRQ18 SOURCE" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" line.long 0x4 "EN_SET18,GIRQ18 ENABLE SET" bitfld.long 0x4 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x4 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x4 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x4 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x4 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x4 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x4 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x4 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x4 20. "CCT,CCT" "0,1" bitfld.long 0x4 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x4 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x4 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x4 0. "SPT0,SPT0" "0,1" rgroup.long 0xD0++0x3 line.long 0x0 "RESULT18,GIRQ18 RESULT" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xD4++0x3 line.long 0x0 "EN_CLR18,GIRQ18 ENABLE CLEAR" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xDC++0x7 line.long 0x0 "SRC19,GIRQ19 SOURCE" line.long 0x4 "EN_SET19,GIRQ19 ENABLE SET" rgroup.long 0xE4++0x3 line.long 0x0 "RESULT19,GIRQ19 RESULT" group.long 0xE8++0x3 line.long 0x0 "EN_CLR19,GIRQ19 ENABLE CLEAR" group.long 0xF0++0x7 line.long 0x0 "SRC20,GIRQ20 SOURCE" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" line.long 0x4 "EN_SET20,GIRQ20 ENABLE SET" bitfld.long 0x4 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x4 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x4 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x4 8. "IMSPI,IMSPI" "0,1" rgroup.long 0xF8++0x3 line.long 0x0 "RESULT20,GIRQ20 RESULT" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0xFC++0x3 line.long 0x0 "EN_CLR20,GIRQ20 ENABLE CLEAR" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0x104++0x7 line.long 0x0 "SRC21,GIRQ21 SOURCE" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" line.long 0x4 "EN_SET21,GIRQ21 ENABLE SET" bitfld.long 0x4 24. "EMC,EMC" "0,1" bitfld.long 0x4 2. "WDT,WDT" "0,1" rgroup.long 0x10C++0x3 line.long 0x0 "RESULT21,GIRQ21 RESULT" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x110++0x3 line.long 0x0 "EN_CLR21,GIRQ21 ENABLE CLEAR" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x118++0x7 line.long 0x0 "SRC22,GIRQ22 SOURCE" line.long 0x4 "EN_SET22,GIRQ22 ENABLE SET" rgroup.long 0x120++0x3 line.long 0x0 "RESULT22,GIRQ22 RESULT" group.long 0x124++0x3 line.long 0x0 "EN_CLR22,GIRQ22 ENABLE CLEAR" group.long 0x12C++0x7 line.long 0x0 "SRC23,GIRQ23 SOURCE" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" line.long 0x4 "EN_SET23,GIRQ23 ENABLE SET" bitfld.long 0x4 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x4 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x4 14. "SWI3,SWI3" "0,1" bitfld.long 0x4 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x4 12. "SWI1,SWI1" "0,1" bitfld.long 0x4 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x4 10. "RTMR,RTMR" "0,1" bitfld.long 0x4 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x4 4. "TIMER32_0,TIMER32_0" "0,1" rgroup.long 0x134++0x3 line.long 0x0 "RESULT23,GIRQ23 RESULT" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x138++0x3 line.long 0x0 "EN_CLR23,GIRQ23 ENABLE CLEAR" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x140++0x7 line.long 0x0 "SRC24,GIRQ24 SOURCE" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" line.long 0x4 "EN_SET24,GIRQ24 ENABLE SET" bitfld.long 0x4 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x4 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x4 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x4 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x4 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x4 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "RESULT24,GIRQ24 RESULT" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x14C++0x3 line.long 0x0 "EN_CLR24,GIRQ24 ENABLE CLEAR" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x154++0x7 line.long 0x0 "SRC25,GIRQ25 SOURCE" line.long 0x4 "EN_SET25,GIRQ25 ENABLE SET" rgroup.long 0x15C++0x3 line.long 0x0 "RESULT25,GIRQ25 RESULT" group.long 0x160++0x3 line.long 0x0 "EN_CLR25,GIRQ25 ENABLE CLEAR" group.long 0x168++0x7 line.long 0x0 "SRC26,GIRQ26 SOURCE" bitfld.long 0x0 11. "GPIO253,GPIO253" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" line.long 0x4 "EN_SET26,GIRQ26 ENABLE SET" bitfld.long 0x4 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x4 8. "GPIO250,GPIO250" "0,1" rgroup.long 0x170++0x3 line.long 0x0 "RESULT26,GIRQ26 RESULT" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" group.long 0x174++0x3 line.long 0x0 "EN_CLR26,GIRQ26 ENABLE CLEAR" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" endif sif (cpuis("CEC1736?2HW*")) group.long 0x0++0x7 line.long 0x0 "SRC8,GIRQ8 SOURCE" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" line.long 0x4 "EN_SET8,GIRQ8 ENABLE SET" bitfld.long 0x4 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x4 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x4 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x4 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x4 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x4 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x4 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x4 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x4 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x4 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x4 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x4 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x4 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x4 0. "GPIO140,GPIO 140" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RESULT8,GIRQ8 RESULT" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0xC++0x3 line.long 0x0 "EN_CLR8,GIRQ8 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0x14++0x7 line.long 0x0 "SRC9,GIRQ9 SOURCE" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" line.long 0x4 "EN_SET9,GIRQ9 ENABLE SET" bitfld.long 0x4 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x4 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x4 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x4 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x4 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x4 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x4 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x4 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x4 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x4 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x4 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x4 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x4 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x4 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x4 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x4 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x4 4. "GPIO104,GPIO 104" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "RESULT9,GIRQ9 RESULT" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x20++0x3 line.long 0x0 "EN_CLR9,GIRQ9 ENABLE CLEAR" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x28++0x7 line.long 0x0 "SRC10,GIRQ10 SOURCE" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" line.long 0x4 "EN_SET10,GIRQ10 ENABLE SET" bitfld.long 0x4 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x4 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x4 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x4 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x4 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x4 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x4 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x4 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x4 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x4 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x4 5. "GPIO045,GPIO 045" "0,1" rgroup.long 0x30++0x3 line.long 0x0 "RESULT10,GIRQ10 RESULT" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x34++0x3 line.long 0x0 "EN_CLR10,GIRQ10 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x3C++0x7 line.long 0x0 "SRC11,GIRQ11 SOURCE" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" line.long 0x4 "EN_SET11,GIRQ11 ENABLE SET" bitfld.long 0x4 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x4 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x4 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x4 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x4 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x4 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x4 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x4 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x4 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x4 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x4 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x4 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x4 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x4 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x4 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x4 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x4 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x4 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x4 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x4 0. "GPIO000,GPIO 000" "0,1" rgroup.long 0x44++0x3 line.long 0x0 "RESULT11,GIRQ11 RESULT" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x48++0x3 line.long 0x0 "EN_CLR11,GIRQ11 ENABLE CLEAR" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x50++0x7 line.long 0x0 "SRC12,GIRQ12 SOURCE" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" line.long 0x4 "EN_SET12,GIRQ12 ENABLE SET" bitfld.long 0x4 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x4 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x4 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x4 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x4 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x4 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x4 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x4 0. "GPIO200,GPIO 200" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "RESULT12,GIRQ12 RESULT" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x5C++0x3 line.long 0x0 "EN_CLR12,GIRQ12 ENABLE CLEAR" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x64++0x7 line.long 0x0 "SRC13,GIRQ13 SOURCE" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" line.long 0x4 "EN_SET13,GIRQ13 ENABLE SET" bitfld.long 0x4 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x4 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x4 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x4 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x4 0. "I2CSMB0,I2CSMB0" "0,1" rgroup.long 0x6C++0x3 line.long 0x0 "RESULT13,GIRQ13 RESULT" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x70++0x3 line.long 0x0 "EN_CLR13,GIRQ13 ENABLE CLEAR" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x78++0x7 line.long 0x0 "SRC14,GIRQ14 SOURCE" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" line.long 0x4 "EN_SET14,GIRQ14 ENABLE SET" bitfld.long 0x4 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x4 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x4 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x4 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x4 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x4 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x4 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x4 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x4 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x4 0. "DMA_CH00,DMA CH00" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "RESULT14,GIRQ14 RESULT" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x84++0x3 line.long 0x0 "EN_CLR14,GIRQ14 ENABLE CLEAR" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x8C++0x7 line.long 0x0 "SRC15,GIRQ15 SOURCE" bitfld.long 0x0 0. "UART0,UART0" "0,1" line.long 0x4 "EN_SET15,GIRQ15 ENABLE SET" bitfld.long 0x4 0. "UART0,UART0" "0,1" rgroup.long 0x94++0x3 line.long 0x0 "RESULT15,GIRQ15 RESULT" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0x98++0x3 line.long 0x0 "EN_CLR15,GIRQ15 ENABLE CLEAR" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0xA0++0x7 line.long 0x0 "SRC16,GIRQ16 SOURCE" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" line.long 0x4 "EN_SET16,GIRQ16 ENABLE SET" bitfld.long 0x4 4. "HASH,HASH" "0,1" bitfld.long 0x4 3. "AES,AES" "0,1" newline bitfld.long 0x4 2. "RNG,RNG" "0,1" bitfld.long 0x4 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x4 0. "PKE_ERR,PKE ERR" "0,1" rgroup.long 0xA8++0x3 line.long 0x0 "RESULT16,GIRQ16 RESULT" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xAC++0x3 line.long 0x0 "EN_CLR16,GIRQ16 ENABLE CLEAR" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xB4++0x7 line.long 0x0 "SRC17,GIRQ17 SOURCE" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" line.long 0x4 "EN_SET17,GIRQ17 ENABLE SET" bitfld.long 0x4 14. "LED1,Breating LED1" "0,1" bitfld.long 0x4 13. "LED0,Breating LED0" "0,1" rgroup.long 0xBC++0x3 line.long 0x0 "RESULT17,GIRQ17 RESULT" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC0++0x3 line.long 0x0 "EN_CLR17,GIRQ17 ENABLE CLEAR" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC8++0x7 line.long 0x0 "SRC18,GIRQ18 SOURCE" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" line.long 0x4 "EN_SET18,GIRQ18 ENABLE SET" bitfld.long 0x4 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x4 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x4 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x4 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x4 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x4 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x4 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x4 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x4 20. "CCT,CCT" "0,1" bitfld.long 0x4 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x4 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x4 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x4 0. "SPT0,SPT0" "0,1" rgroup.long 0xD0++0x3 line.long 0x0 "RESULT18,GIRQ18 RESULT" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xD4++0x3 line.long 0x0 "EN_CLR18,GIRQ18 ENABLE CLEAR" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xDC++0x7 line.long 0x0 "SRC19,GIRQ19 SOURCE" line.long 0x4 "EN_SET19,GIRQ19 ENABLE SET" rgroup.long 0xE4++0x3 line.long 0x0 "RESULT19,GIRQ19 RESULT" group.long 0xE8++0x3 line.long 0x0 "EN_CLR19,GIRQ19 ENABLE CLEAR" group.long 0xF0++0x7 line.long 0x0 "SRC20,GIRQ20 SOURCE" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" line.long 0x4 "EN_SET20,GIRQ20 ENABLE SET" bitfld.long 0x4 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x4 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x4 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x4 8. "IMSPI,IMSPI" "0,1" rgroup.long 0xF8++0x3 line.long 0x0 "RESULT20,GIRQ20 RESULT" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0xFC++0x3 line.long 0x0 "EN_CLR20,GIRQ20 ENABLE CLEAR" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0x104++0x7 line.long 0x0 "SRC21,GIRQ21 SOURCE" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" line.long 0x4 "EN_SET21,GIRQ21 ENABLE SET" bitfld.long 0x4 24. "EMC,EMC" "0,1" bitfld.long 0x4 2. "WDT,WDT" "0,1" rgroup.long 0x10C++0x3 line.long 0x0 "RESULT21,GIRQ21 RESULT" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x110++0x3 line.long 0x0 "EN_CLR21,GIRQ21 ENABLE CLEAR" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x118++0x7 line.long 0x0 "SRC22,GIRQ22 SOURCE" line.long 0x4 "EN_SET22,GIRQ22 ENABLE SET" rgroup.long 0x120++0x3 line.long 0x0 "RESULT22,GIRQ22 RESULT" group.long 0x124++0x3 line.long 0x0 "EN_CLR22,GIRQ22 ENABLE CLEAR" group.long 0x12C++0x7 line.long 0x0 "SRC23,GIRQ23 SOURCE" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" line.long 0x4 "EN_SET23,GIRQ23 ENABLE SET" bitfld.long 0x4 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x4 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x4 14. "SWI3,SWI3" "0,1" bitfld.long 0x4 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x4 12. "SWI1,SWI1" "0,1" bitfld.long 0x4 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x4 10. "RTMR,RTMR" "0,1" bitfld.long 0x4 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x4 4. "TIMER32_0,TIMER32_0" "0,1" rgroup.long 0x134++0x3 line.long 0x0 "RESULT23,GIRQ23 RESULT" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x138++0x3 line.long 0x0 "EN_CLR23,GIRQ23 ENABLE CLEAR" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x140++0x7 line.long 0x0 "SRC24,GIRQ24 SOURCE" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" line.long 0x4 "EN_SET24,GIRQ24 ENABLE SET" bitfld.long 0x4 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x4 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x4 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x4 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x4 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x4 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "RESULT24,GIRQ24 RESULT" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x14C++0x3 line.long 0x0 "EN_CLR24,GIRQ24 ENABLE CLEAR" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x154++0x7 line.long 0x0 "SRC25,GIRQ25 SOURCE" line.long 0x4 "EN_SET25,GIRQ25 ENABLE SET" rgroup.long 0x15C++0x3 line.long 0x0 "RESULT25,GIRQ25 RESULT" group.long 0x160++0x3 line.long 0x0 "EN_CLR25,GIRQ25 ENABLE CLEAR" group.long 0x168++0x7 line.long 0x0 "SRC26,GIRQ26 SOURCE" bitfld.long 0x0 11. "GPIO253,GPIO253" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" line.long 0x4 "EN_SET26,GIRQ26 ENABLE SET" bitfld.long 0x4 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x4 8. "GPIO250,GPIO250" "0,1" rgroup.long 0x170++0x3 line.long 0x0 "RESULT26,GIRQ26 RESULT" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" group.long 0x174++0x3 line.long 0x0 "EN_CLR26,GIRQ26 ENABLE CLEAR" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" endif sif (cpuis("CEC1736?2ZW*")) group.long 0x0++0x7 line.long 0x0 "SRC8,GIRQ8 SOURCE" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" line.long 0x4 "EN_SET8,GIRQ8 ENABLE SET" bitfld.long 0x4 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x4 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x4 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x4 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x4 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x4 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x4 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x4 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x4 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x4 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x4 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x4 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x4 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x4 0. "GPIO140,GPIO 140" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RESULT8,GIRQ8 RESULT" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0xC++0x3 line.long 0x0 "EN_CLR8,GIRQ8 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO171,GPIO 171" "0,1" bitfld.long 0x0 24. "GPIO170,GPIO 170" "0,1" newline bitfld.long 0x0 22. "GPIO166,GPIO 166" "0,1" bitfld.long 0x0 21. "GPIO165,GPIO 165" "0,1" newline bitfld.long 0x0 19. "GPIO163,GPIO 163" "0,1" bitfld.long 0x0 15. "GPIO157,GPIO 157" "0,1" newline bitfld.long 0x0 14. "GPIO156,GPIO 156" "0,1" bitfld.long 0x0 8. "GPIO150,GPIO 150" "0,1" newline bitfld.long 0x0 7. "GPIO147,GPIO 147" "0,1" bitfld.long 0x0 6. "GPIO146,GPIO 146" "0,1" newline bitfld.long 0x0 5. "GPIO145,GPIO 145" "0,1" bitfld.long 0x0 4. "GPIO144,GPIO 144" "0,1" newline bitfld.long 0x0 3. "GPIO143,GPIO 143" "0,1" bitfld.long 0x0 0. "GPIO140,GPIO 140" "0,1" group.long 0x14++0x7 line.long 0x0 "SRC9,GIRQ9 SOURCE" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" line.long 0x4 "EN_SET9,GIRQ9 ENABLE SET" bitfld.long 0x4 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x4 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x4 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x4 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x4 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x4 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x4 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x4 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x4 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x4 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x4 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x4 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x4 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x4 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x4 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x4 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x4 4. "GPIO104,GPIO 104" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "RESULT9,GIRQ9 RESULT" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x20++0x3 line.long 0x0 "EN_CLR9,GIRQ9 ENABLE CLEAR" bitfld.long 0x0 26. "GPIO132,GPIO 132" "0,1" bitfld.long 0x0 25. "GPIO131,GPIO 131" "0,1" newline bitfld.long 0x0 24. "GPIO130,GPIO 130" "0,1" bitfld.long 0x0 23. "GPIO127,GPIO 127" "0,1" newline bitfld.long 0x0 22. "GPIO126,GPIO 126" "0,1" bitfld.long 0x0 21. "GPIO125,GPIO 125" "0,1" newline bitfld.long 0x0 20. "GPIO124,GPIO 124" "0,1" bitfld.long 0x0 19. "GPIO123,GPIO 123" "0,1" newline bitfld.long 0x0 18. "GPIO122,GPIO 122" "0,1" bitfld.long 0x0 17. "GPIO121,GPIO 121" "0,1" newline bitfld.long 0x0 16. "GPIO120,GPIO 120" "0,1" bitfld.long 0x0 11. "GPIO113,GPIO 113" "0,1" newline bitfld.long 0x0 10. "GPIO112,GPIO 112" "0,1" bitfld.long 0x0 7. "GPIO107,GPIO 107" "0,1" newline bitfld.long 0x0 6. "GPIO106,GPIO 106" "0,1" bitfld.long 0x0 5. "GPIO105,GPIO 105" "0,1" newline bitfld.long 0x0 4. "GPIO104,GPIO 104" "0,1" group.long 0x28++0x7 line.long 0x0 "SRC10,GIRQ10 SOURCE" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" line.long 0x4 "EN_SET10,GIRQ10 ENABLE SET" bitfld.long 0x4 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x4 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x4 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x4 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x4 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x4 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x4 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x4 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x4 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x4 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x4 5. "GPIO045,GPIO 045" "0,1" rgroup.long 0x30++0x3 line.long 0x0 "RESULT10,GIRQ10 RESULT" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x34++0x3 line.long 0x0 "EN_CLR10,GIRQ10 ENABLE CLEAR" bitfld.long 0x0 25. "GPIO071,GPIO 071" "0,1" bitfld.long 0x0 24. "GPIO070,GPIO 070" "0,1" newline bitfld.long 0x0 19. "GPIO063,GPIO 060" "0,1" bitfld.long 0x0 15. "GPIO057,GPIO 057" "0,1" newline bitfld.long 0x0 14. "GPIO056,GPIO 056" "0,1" bitfld.long 0x0 13. "GPIO055,GPIO 055" "0,1" newline bitfld.long 0x0 11. "GPIO053,GPIO 053" "0,1" bitfld.long 0x0 8. "GPIO050,GPIO 050" "0,1" newline bitfld.long 0x0 7. "GPIO047,GPIO 047" "0,1" bitfld.long 0x0 6. "GPIO046,GPIO 046" "0,1" newline bitfld.long 0x0 5. "GPIO045,GPIO 045" "0,1" group.long 0x3C++0x7 line.long 0x0 "SRC11,GIRQ11 SOURCE" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" line.long 0x4 "EN_SET11,GIRQ11 ENABLE SET" bitfld.long 0x4 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x4 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x4 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x4 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x4 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x4 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x4 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x4 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x4 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x4 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x4 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x4 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x4 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x4 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x4 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x4 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x4 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x4 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x4 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x4 0. "GPIO000,GPIO 000" "0,1" rgroup.long 0x44++0x3 line.long 0x0 "RESULT11,GIRQ11 RESULT" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x48++0x3 line.long 0x0 "EN_CLR11,GIRQ11 ENABLE CLEAR" bitfld.long 0x0 28. "GPIO034,GPIO 034" "0,1" bitfld.long 0x0 27. "GPIO033,GPIO 033" "0,1" newline bitfld.long 0x0 26. "GPIO032,GPIO 032" "0,1" bitfld.long 0x0 25. "GPIO031,GPIO 031" "0,1" newline bitfld.long 0x0 24. "GPIO030,GPIO 030" "0,1" bitfld.long 0x0 23. "GPIO027,GPIO 027" "0,1" newline bitfld.long 0x0 22. "GPIO026,GPIO 026" "0,1" bitfld.long 0x0 20. "GPIO024,GPIO 024" "0,1" newline bitfld.long 0x0 19. "GPIO023,GPIO 023" "0,1" bitfld.long 0x0 18. "GPIO022,GPIO 022" "0,1" newline bitfld.long 0x0 17. "GPIO021,GPIO 021" "0,1" bitfld.long 0x0 16. "GPIO020,GPIO 020" "0,1" newline bitfld.long 0x0 14. "GPIO016,GPIO 016" "0,1" bitfld.long 0x0 13. "GPIO015,GPIO 015" "0,1" newline bitfld.long 0x0 11. "GPIO013,GPIO 013" "0,1" bitfld.long 0x0 10. "GPIO012,GPIO 012" "0,1" newline bitfld.long 0x0 4. "GPIO004,GPIO 004" "0,1" bitfld.long 0x0 3. "GPIO003,GPIO 003" "0,1" newline bitfld.long 0x0 2. "GPIO002,GPIO 002" "0,1" bitfld.long 0x0 0. "GPIO000,GPIO 000" "0,1" group.long 0x50++0x7 line.long 0x0 "SRC12,GIRQ12 SOURCE" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" line.long 0x4 "EN_SET12,GIRQ12 ENABLE SET" bitfld.long 0x4 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x4 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x4 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x4 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x4 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x4 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x4 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x4 0. "GPIO200,GPIO 200" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "RESULT12,GIRQ12 RESULT" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x5C++0x3 line.long 0x0 "EN_CLR12,GIRQ12 ENABLE CLEAR" bitfld.long 0x0 23. "GPIO227,GPIO 227" "0,1" bitfld.long 0x0 20. "GPIO224,GPIO 224" "0,1" newline bitfld.long 0x0 19. "GPIO223,GPIO 223" "0,1" bitfld.long 0x0 4. "GPIO204,GPIO 204" "0,1" newline bitfld.long 0x0 3. "GPIO203,GPIO 203" "0,1" bitfld.long 0x0 2. "GPIO202,GPIO 202" "0,1" newline bitfld.long 0x0 1. "GPIO201,GPIO 201" "0,1" bitfld.long 0x0 0. "GPIO200,GPIO 200" "0,1" group.long 0x64++0x7 line.long 0x0 "SRC13,GIRQ13 SOURCE" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" line.long 0x4 "EN_SET13,GIRQ13 ENABLE SET" bitfld.long 0x4 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x4 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x4 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x4 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x4 0. "I2CSMB0,I2CSMB0" "0,1" rgroup.long 0x6C++0x3 line.long 0x0 "RESULT13,GIRQ13 RESULT" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x70++0x3 line.long 0x0 "EN_CLR13,GIRQ13 ENABLE CLEAR" bitfld.long 0x0 4. "I2CSMB4,I2CSMB4" "0,1" bitfld.long 0x0 3. "I2CSMB3,I2CSMB3" "0,1" newline bitfld.long 0x0 2. "I2CSMB2,I2CSMB2" "0,1" bitfld.long 0x0 1. "I2CSMB1,I2CSMB1" "0,1" newline bitfld.long 0x0 0. "I2CSMB0,I2CSMB0" "0,1" group.long 0x78++0x7 line.long 0x0 "SRC14,GIRQ14 SOURCE" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" line.long 0x4 "EN_SET14,GIRQ14 ENABLE SET" bitfld.long 0x4 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x4 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x4 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x4 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x4 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x4 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x4 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x4 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x4 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x4 0. "DMA_CH00,DMA CH00" "0,1" rgroup.long 0x80++0x3 line.long 0x0 "RESULT14,GIRQ14 RESULT" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x84++0x3 line.long 0x0 "EN_CLR14,GIRQ14 ENABLE CLEAR" bitfld.long 0x0 9. "DMA_CH09,DMA CH09" "0,1" bitfld.long 0x0 8. "DMA_CH08,DMA CH08" "0,1" newline bitfld.long 0x0 7. "DMA_CH07,DMA CH07" "0,1" bitfld.long 0x0 6. "DMA_CH06,DMA CH06" "0,1" newline bitfld.long 0x0 5. "DMA_CH05,DMA CH05" "0,1" bitfld.long 0x0 4. "DMA_CH04,DMA CH04" "0,1" newline bitfld.long 0x0 3. "DMA_CH03,DMA CH03" "0,1" bitfld.long 0x0 2. "DMA_CH02,DMA CH02" "0,1" newline bitfld.long 0x0 1. "DMA_CH01,DMA CH01" "0,1" bitfld.long 0x0 0. "DMA_CH00,DMA CH00" "0,1" group.long 0x8C++0x7 line.long 0x0 "SRC15,GIRQ15 SOURCE" bitfld.long 0x0 0. "UART0,UART0" "0,1" line.long 0x4 "EN_SET15,GIRQ15 ENABLE SET" bitfld.long 0x4 0. "UART0,UART0" "0,1" rgroup.long 0x94++0x3 line.long 0x0 "RESULT15,GIRQ15 RESULT" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0x98++0x3 line.long 0x0 "EN_CLR15,GIRQ15 ENABLE CLEAR" bitfld.long 0x0 0. "UART0,UART0" "0,1" group.long 0xA0++0x7 line.long 0x0 "SRC16,GIRQ16 SOURCE" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" line.long 0x4 "EN_SET16,GIRQ16 ENABLE SET" bitfld.long 0x4 4. "HASH,HASH" "0,1" bitfld.long 0x4 3. "AES,AES" "0,1" newline bitfld.long 0x4 2. "RNG,RNG" "0,1" bitfld.long 0x4 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x4 0. "PKE_ERR,PKE ERR" "0,1" rgroup.long 0xA8++0x3 line.long 0x0 "RESULT16,GIRQ16 RESULT" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xAC++0x3 line.long 0x0 "EN_CLR16,GIRQ16 ENABLE CLEAR" bitfld.long 0x0 4. "HASH,HASH" "0,1" bitfld.long 0x0 3. "AES,AES" "0,1" newline bitfld.long 0x0 2. "RNG,RNG" "0,1" bitfld.long 0x0 1. "PKE_END,PKE END" "0,1" newline bitfld.long 0x0 0. "PKE_ERR,PKE ERR" "0,1" group.long 0xB4++0x7 line.long 0x0 "SRC17,GIRQ17 SOURCE" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" line.long 0x4 "EN_SET17,GIRQ17 ENABLE SET" bitfld.long 0x4 14. "LED1,Breating LED1" "0,1" bitfld.long 0x4 13. "LED0,Breating LED0" "0,1" rgroup.long 0xBC++0x3 line.long 0x0 "RESULT17,GIRQ17 RESULT" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC0++0x3 line.long 0x0 "EN_CLR17,GIRQ17 ENABLE CLEAR" bitfld.long 0x0 14. "LED1,Breating LED1" "0,1" bitfld.long 0x0 13. "LED0,Breating LED0" "0,1" group.long 0xC8++0x7 line.long 0x0 "SRC18,GIRQ18 SOURCE" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" line.long 0x4 "EN_SET18,GIRQ18 ENABLE SET" bitfld.long 0x4 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x4 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x4 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x4 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x4 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x4 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x4 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x4 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x4 20. "CCT,CCT" "0,1" bitfld.long 0x4 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x4 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x4 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x4 0. "SPT0,SPT0" "0,1" rgroup.long 0xD0++0x3 line.long 0x0 "RESULT18,GIRQ18 RESULT" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xD4++0x3 line.long 0x0 "EN_CLR18,GIRQ18 ENABLE CLEAR" bitfld.long 0x0 28. "CCT_CMP1,CCT_CMP1" "0,1" bitfld.long 0x0 27. "CCT_CMP0,CCT_CMP0" "0,1" newline bitfld.long 0x0 26. "CCT_CAP5,CCT_CAP5" "0,1" bitfld.long 0x0 25. "CCT_CAP4,CCT_CAP4" "0,1" newline bitfld.long 0x0 24. "CCT_CAP3,CCT_CAP3" "0,1" bitfld.long 0x0 23. "CCT_CAP2,CCT_CAP2" "0,1" newline bitfld.long 0x0 22. "CCT_CAP1,CCT_CAP1" "0,1" bitfld.long 0x0 21. "CCT_CAP0,CCT_CAP0" "0,1" newline bitfld.long 0x0 20. "CCT,CCT" "0,1" bitfld.long 0x0 18. "SPT1,SPT1" "0,1" newline bitfld.long 0x0 2. "QMSPI1,QMSPI1" "0,1" bitfld.long 0x0 1. "QMSPI0,QMSPI0" "0,1" newline bitfld.long 0x0 0. "SPT0,SPT0" "0,1" group.long 0xDC++0x7 line.long 0x0 "SRC19,GIRQ19 SOURCE" line.long 0x4 "EN_SET19,GIRQ19 ENABLE SET" rgroup.long 0xE4++0x3 line.long 0x0 "RESULT19,GIRQ19 RESULT" group.long 0xE8++0x3 line.long 0x0 "EN_CLR19,GIRQ19 ENABLE CLEAR" group.long 0xF0++0x7 line.long 0x0 "SRC20,GIRQ20 SOURCE" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" line.long 0x4 "EN_SET20,GIRQ20 ENABLE SET" bitfld.long 0x4 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x4 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x4 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x4 8. "IMSPI,IMSPI" "0,1" rgroup.long 0xF8++0x3 line.long 0x0 "RESULT20,GIRQ20 RESULT" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0xFC++0x3 line.long 0x0 "EN_CLR20,GIRQ20 ENABLE CLEAR" bitfld.long 0x0 11. "VTR2_PAD_MON,VTR2_PAD_MON" "0,1" bitfld.long 0x0 10. "VTR1_PAD_MON,VTR1_PAD_MON" "0,1" newline bitfld.long 0x0 9. "CLK_MON,CLK_MON" "0,1" bitfld.long 0x0 8. "IMSPI,IMSPI" "0,1" group.long 0x104++0x7 line.long 0x0 "SRC21,GIRQ21 SOURCE" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" line.long 0x4 "EN_SET21,GIRQ21 ENABLE SET" bitfld.long 0x4 24. "EMC,EMC" "0,1" bitfld.long 0x4 2. "WDT,WDT" "0,1" rgroup.long 0x10C++0x3 line.long 0x0 "RESULT21,GIRQ21 RESULT" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x110++0x3 line.long 0x0 "EN_CLR21,GIRQ21 ENABLE CLEAR" bitfld.long 0x0 24. "EMC,EMC" "0,1" bitfld.long 0x0 2. "WDT,WDT" "0,1" group.long 0x118++0x7 line.long 0x0 "SRC22,GIRQ22 SOURCE" line.long 0x4 "EN_SET22,GIRQ22 ENABLE SET" rgroup.long 0x120++0x3 line.long 0x0 "RESULT22,GIRQ22 RESULT" group.long 0x124++0x3 line.long 0x0 "EN_CLR22,GIRQ22 ENABLE CLEAR" group.long 0x12C++0x7 line.long 0x0 "SRC23,GIRQ23 SOURCE" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" line.long 0x4 "EN_SET23,GIRQ23 ENABLE SET" bitfld.long 0x4 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x4 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x4 14. "SWI3,SWI3" "0,1" bitfld.long 0x4 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x4 12. "SWI1,SWI1" "0,1" bitfld.long 0x4 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x4 10. "RTMR,RTMR" "0,1" bitfld.long 0x4 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x4 4. "TIMER32_0,TIMER32_0" "0,1" rgroup.long 0x134++0x3 line.long 0x0 "RESULT23,GIRQ23 RESULT" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x138++0x3 line.long 0x0 "EN_CLR23,GIRQ23 ENABLE CLEAR" bitfld.long 0x0 17. "HTMR1,HTMR1" "0,1" bitfld.long 0x0 16. "HTMR0,HTMR0" "0,1" newline bitfld.long 0x0 14. "SWI3,SWI3" "0,1" bitfld.long 0x0 13. "SWI2,SWI2" "0,1" newline bitfld.long 0x0 12. "SWI1,SWI1" "0,1" bitfld.long 0x0 11. "SWI0,SWI0" "0,1" newline bitfld.long 0x0 10. "RTMR,RTMR" "0,1" bitfld.long 0x0 5. "TIMER32_1,TIMER32_1" "0,1" newline bitfld.long 0x0 4. "TIMER32_0,TIMER32_0" "0,1" group.long 0x140++0x7 line.long 0x0 "SRC24,GIRQ24 SOURCE" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" line.long 0x4 "EN_SET24,GIRQ24 ENABLE SET" bitfld.long 0x4 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x4 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x4 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x4 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x4 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x4 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "RESULT24,GIRQ24 RESULT" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x14C++0x3 line.long 0x0 "EN_CLR24,GIRQ24 ENABLE CLEAR" bitfld.long 0x0 6. "SPIMON1_LTMON,SPIMON1_LTMON" "0,1" bitfld.long 0x0 5. "SPIMON1_MTMON,SPIMON1_MTMON" "0,1" newline bitfld.long 0x0 4. "SPIMON1_VLTN,SPIMON1_VLTN" "0,1" bitfld.long 0x0 2. "SPIMON0_LTMON,SPIMON0_LTMON" "0,1" newline bitfld.long 0x0 1. "SPIMON0_MTMON,SPIMON0_MTMON" "0,1" bitfld.long 0x0 0. "SPIMON0_VLTN,SPIMON0_VLTN" "0,1" group.long 0x154++0x7 line.long 0x0 "SRC25,GIRQ25 SOURCE" line.long 0x4 "EN_SET25,GIRQ25 ENABLE SET" rgroup.long 0x15C++0x3 line.long 0x0 "RESULT25,GIRQ25 RESULT" group.long 0x160++0x3 line.long 0x0 "EN_CLR25,GIRQ25 ENABLE CLEAR" group.long 0x168++0x7 line.long 0x0 "SRC26,GIRQ26 SOURCE" bitfld.long 0x0 11. "GPIO253,GPIO253" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" line.long 0x4 "EN_SET26,GIRQ26 ENABLE SET" bitfld.long 0x4 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x4 8. "GPIO250,GPIO250" "0,1" rgroup.long 0x170++0x3 line.long 0x0 "RESULT26,GIRQ26 RESULT" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" group.long 0x174++0x3 line.long 0x0 "EN_CLR26,GIRQ26 ENABLE CLEAR" bitfld.long 0x0 11. "GPIO260,GPIO260" "0,1" bitfld.long 0x0 8. "GPIO250,GPIO250" "0,1" endif group.long 0x200++0x7 line.long 0x0 "BLK_EN_SET,Block Enable Set Register" hexmask.long 0x0 0.--30. 1. "VTOR_EN_SET,Each GIRQx bit can be individually enabled to assert an interrupt event.\n Reads always return the current value of the internal GIRQX_ENABLE bit. The state of the GIRQX_ENABLE bit is determined by\n the corresponding.." line.long 0x4 "BLK_EN_CLR,Block Enable Clear Register." hexmask.long 0x4 0.--30. 1. "VTOR_EN_CLR,Each GIRQx bit can be individually disabled to inhibit an interrupt event.\n Reads always return the current value of the internal GIRQX_ENABLE bit. The state of the GIRQX_ENABLE bit is determined by\n the corresponding.." rgroup.long 0x208++0x3 line.long 0x0 "BLK_IRQ_VTOR,Block IRQ Vector Register" hexmask.long 0x0 0.--24. 1. "VTOR,Each bit in this field reports the status of the group GIRQ interrupt assertion to the NVIC. If the GIRQx interrupt\n is disabled as a group by the Block Enable Clear Register then the corresponding bit will be '0'b and no interrupt will be.." tree.end sif (cpuis("CEC1702*")) tree "EFUSE" base ad:0x40082000 group.word 0x0++0x1 line.word 0x0 "CTRL,eFUSE CTRL Register" bitfld.word 0x0 4. "FSOURCE_EN_READ,FSOURCE pin enable for reading: 1=FSOURCE switch logic connects eFUSE FSOURCE pin to a power pad for read mode.\n Only set this bit when FSOURCE_EN_PRGM bit is already 0 to avoid shorting the power pad to ground;\n.." "0: FSOURCE switch logic isolates eFUSE FSOURCE pin..,1: FSOURCE switch logic connects eFUSE FSOURCE pin.." bitfld.word 0x0 3. "FSOURCE_EN_PRGM,FSOURCE pin enable for programming: 1=FSOURCE switch logic connects eFUSE FSOURCE pin to a power pad for PROGRAM mode.\n Only set this bit when FSOURCE_EN_READ bit is already 0 to avoid shorting the power pad to ground;\n.." "0: FSOURCE switch logic isolates eFUSE FSOURCE pin..,1: FSOURCE switch logic connects eFUSE FSOURCE pin.." newline bitfld.word 0x0 2. "EXT_PGM,External programming enable: 1=eFUSE programming is done via external pin interface 0=Manual/Normal mode.\n eFUSE programming is done via this block's register set." "0: Manual/Normal mode,1: eFUSE programming is done via external pin.." bitfld.word 0x0 1. "RST,Block reset: 1=Block is reset; 0=Normal operation. This bit self-clears and always reads back 0." "0: Normal operation,1: Block is reset" newline bitfld.word 0x0 0. "EN,Block enable: 1=block is enabled for operation; 0=block is disabled and in lowest power state." "0: block is disabled and in lowest power state,1: block is enabled for operation" group.word 0x4++0x3 line.word 0x0 "MAN_CTRL,Manual Control Register" bitfld.word 0x0 5. "IP_OE,eFUSE output enable. The IP might tri-state at various times so this bit isolates the outputs to avoid potential crowbar.\n 1=eFUSE outputs enabled for read; 0=eFUSE outputs isolated" "0: eFUSE outputs isolated,1: eFUSE outputs enabled for read" bitfld.word 0x0 4. "IP_SENSE_PULSE,eFUSE sense outputs are valid on falling edge of this bit." "0,1" newline bitfld.word 0x0 3. "IP_PRCHG,eFUSE precharge: 1=outputs are being precharged; 0=outputs are not precharged." "0: outputs are not precharged,1: outputs are being precharged" bitfld.word 0x0 2. "IP_PRGM_EN,eFUSE program enable. Can also be considered the write signal: 1=eFUSE is programming; 0=eFUSE is in read mode." "0: eFUSE is in read mode,1: eFUSE is programming" newline bitfld.word 0x0 1. "IP_CS,eFUSE chip select (CS) pin: 1=eFUSE is enabled for PROGRAM/READ modes; 0=eFUSE is disabled and in low power state." "0: eFUSE is disabled and in low power state,1: eFUSE is enabled for PROGRAM/READ modes" bitfld.word 0x0 0. "MAN_ENABLE,Manual mode enable bit: 1=Manual mode is enabled and this register interfaces to the eFUSE;\n 0=Normal mode internal controller interfaces to eFUSE IP. This bit only takes affect when REG_CTRL.EXT_PRGM bit is 0." "0: Normal mode,1: Manual mode is enabled and this register.." line.word 0x2 "MAN_MOD_ADDR,MANUAL MODE ADDRESS REGISTER" bitfld.word 0x2 10.--11. "IP_ADDR_HI,Manual mode address selecting a 1K bit block of eFuse data" "0,1,2,3" hexmask.word 0x2 0.--9. 1. "IP_ADDR_LO,Manual mode address selecting the bit address within a 1K bit block." group.long 0xC++0x3 line.long 0x0 "MAN_MOD_DATA,MANUAL MODE DATA REGISTER" hexmask.long.word 0x0 0.--15. 1. "IP_DATA,Manual mode data: This field connects to the eFUSE data output pins." repeat 128. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x10)++0x3 line.long 0x0 "MEM_DW[$1],512 Bytes of EFUSE Memory (IP_MEM) Represented in 128 DW chunks:\n eFUSE memory read-back data. Access to this region depends on the operating mode: NORMAL MODE: Reading any of the bytes\n starting at this base will automatically.." repeat.end tree.end endif sif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) tree "ENV_MON (Environmental Monitor Block)" base ad:0x40200600 rgroup.word 0x0++0x9 line.word 0x0 "EXT1_TEMP,External Diode 1 Temp Register" hexmask.word 0x0 0.--15. 1. "DIODE1_TEMP,External Diode 1 Temp Byte Register" line.word 0x2 "INT_TEMP,Internal Temp Register" hexmask.word 0x2 0.--15. 1. "INT_TEMP,Internal Temp Byte Register" line.word 0x4 "EXT2_TEMP,External Diode 2 Temp Register" hexmask.word 0x4 0.--15. 1. "DIODE2_TEMP,External Diode 2 Temp Byte Register" line.word 0x6 "EXT3_TEMP,External Diode 3 Temp Register" hexmask.word 0x6 0.--15. 1. "DIODE3_TEMP,External Diode 3 Temp Byte Register" line.word 0x8 "EXT4_TEMP,External Diode 4 Temp Register" hexmask.word 0x8 0.--15. 1. "DIODE4_TEMP,External Diode 4 Temp Byte Register" rgroup.byte 0xE++0x0 line.byte 0x0 "VIN_VOLT,Stores the voltage Measured on VIN channel" hexmask.byte 0x0 0.--7. 1. "VIN_VOLT,Stores the voltage Measured on VIN channel" rgroup.word 0x12++0x7 line.word 0x0 "EXT1A_TEMP,Stores the fractional and integer data for External Diode 1A Register" hexmask.word 0x0 0.--15. 1. "DIODE1A_TEMP,Stores the fractional and integer data for External Diode 1A Register" line.word 0x2 "EXT2A_TEMP,Stores the fractional and integer data for External Diode 2A Register" hexmask.word 0x2 0.--15. 1. "DIODE2A_TEMP,Stores the fractional and integer data for External Diode 2A Register" line.word 0x4 "EXT3A_TEMP,Stores the fractional and integer data for External Diode 3A Register" hexmask.word 0x4 0.--15. 1. "DIODE3A_TEMP,Stores the fractional and integer data for External Diode 3A Register" line.word 0x6 "EXT4A_TEMP,Stores the fractional and integer data for External Diode 4A Register" hexmask.word 0x6 0.--15. 1. "DIODE4A_TEMP,Stores the fractional and integerdata for External Diode 4A Register" rgroup.byte 0x21++0x0 line.byte 0x0 "VCP_VOLT,Stores the VCP Voltage Monitor data" hexmask.byte 0x0 0.--7. 1. "VCP_VOLT,Stores the VCP Voltage Monitor data" rgroup.byte 0x23++0x0 line.byte 0x0 "VTT_VOLT,Stores the VTT Voltage Monitor data" hexmask.byte 0x0 0.--7. 1. "VTT_VOLT,Stores the VTT Voltage Monitor data" group.byte 0x2B++0x5 line.byte 0x0 "TEMP_CFG1,Controls temp sensing for external diodes" hexmask.byte 0x0 0.--7. 1. "TEMP_CFG1,Controls temp sensing for external diodes" line.byte 0x1 "TEMP_CFG2,Controls temp sensing for external diodes" hexmask.byte 0x1 0.--7. 1. "TEMP_CFG2,Controls temp sensing for external diodes" line.byte 0x2 "VOLT_CFG,Controls Voltage sensing for external voltages" hexmask.byte 0x2 0.--7. 1. "VOLT_CFG,Controls Voltage sensing for external voltages" line.byte 0x3 "THEM_CFG,Controls Thermistor or diodes Configuration" hexmask.byte 0x3 0.--7. 1. "THEM_CFG,Controls Thermistor or diodes Configuration" line.byte 0x4 "CNVR_CFG,Controls Temperature Conversion for the temperature channels" hexmask.byte 0x4 0.--7. 1. "CNVR_CFG,Controls Temperature Conversion for the temperature channels" line.byte 0x5 "AVG_EN,Software Averaging Enable" hexmask.byte 0x5 0.--7. 1. "AVG_EN,Software Averaging Enable" group.byte 0x38++0x1 line.byte 0x0 "BCOMP1_EN,Configure Beta compensation settings for External Diode1" hexmask.byte 0x0 0.--7. 1. "BCOMP1_EN,Beta compensation settings for External Diode1 Enable" line.byte 0x1 "BCOMP2_EN,Configure Beta compensation settings for External Diode2" hexmask.byte 0x1 0.--7. 1. "BCOMP2_EN,Beta compensation settings for External Diode2 Enable" group.byte 0x40++0x2 line.byte 0x0 "LCK_STRT,Lock Start Register" hexmask.byte 0x0 0.--7. 1. "BCOMP2_EN,Enables the software lock and monitoring functionality" line.byte 0x1 "FLT_INTSTS,Fault Interrupt Status Register" hexmask.byte 0x1 0.--7. 1. "FLT_INTSTS,Stores the status of the External Diode Faults" line.byte 0x2 "FLT_TEMPSTS,Fault temperature Status Register" hexmask.byte 0x2 0.--7. 1. "FLT_TEMPSTS,Stores the status of the External Diode Faults" rgroup.byte 0x43++0x0 line.byte 0x0 "THRMTRP_STS,ThermTrip Pin Status Register" hexmask.byte 0x0 0.--7. 1. "THRMTRP_STS,Stores the pin state of the signals that affect the SYS_SHDN_n signal" group.byte 0x44++0x1 line.byte 0x0 "INT_TEMP_STS,Temperature of Internal Diode Register" hexmask.byte 0x0 0.--7. 1. "TEMP_STS,Stores the status bits for the Internal Diode" line.byte 0x1 "VLT_INTSTS,Volt Interrupt Status Register" hexmask.byte 0x1 0.--7. 1. "VLTINTSTS,Stores the status bits for voltage inputs" group.word 0x46++0x7 line.word 0x0 "VCP_LIMIT,VCP Limit Register" hexmask.word 0x0 0.--15. 1. "VCP_LIMIT,Limit for VCP Voltage Monitor" line.word 0x2 "VTR_LIMIT,VTR Limit Register" hexmask.word 0x2 0.--15. 1. "VTR_LIMIT,Limit for VTR Voltage Monitor" line.word 0x4 "VTT_LIMIT,VTT Limit Register" hexmask.word 0x4 0.--15. 1. "VTT_LIMIT,Limit for VTT Voltage Monitor" line.word 0x6 "VIN_LIMIT,VIN Limit Register" hexmask.word 0x6 0.--15. 1. "VTT_LIMIT,Limit for VIN Voltage Monitor" group.byte 0x4E++0x11 line.byte 0x0 "EXT1_TMPLO_LMT,Low limit for External Diode 1 Register" hexmask.byte 0x0 0.--7. 1. "TMPLO1_LIMIT,Low limit for External Diode 1 Register" line.byte 0x1 "EXT1_TMPHI_LMT,High limit for External Diode 1 Register" hexmask.byte 0x1 0.--7. 1. "TMPHI1_LIMIT,High limit for External Diode 1 Register" line.byte 0x2 "INT_TMPLO_LMT,Low limit for Internal Diode Register" hexmask.byte 0x2 0.--7. 1. "TMPLO_LIMIT,Low limit for Internal Diode Register" line.byte 0x3 "INT_TMPHI_LMT,High limit for Internal Diode Register" hexmask.byte 0x3 0.--7. 1. "TMPHI_LIMIT,High limit for internal Diode Register" line.byte 0x4 "EXT2_TMPLO_LMT,Low limit for External Diode 2 Register" hexmask.byte 0x4 0.--7. 1. "TMPLO2_LIMIT,Low limit for External Diode 2 Register" line.byte 0x5 "EXT2_TMPHI_LMT,High limit for External Diode 2 Register" hexmask.byte 0x5 0.--7. 1. "TMPHI2_LIMIT,High limit for External Diode 2 Register" line.byte 0x6 "EXT3_TMPLO_LMT,Low limit for External Diode 3 Register" hexmask.byte 0x6 0.--7. 1. "TMPLO3_LIMIT,Low limit for External Diode 3 Register" line.byte 0x7 "EXT3_TMPHI_LMT,High limit for External Diode 3 Register" hexmask.byte 0x7 0.--7. 1. "TMPHI3_LIMIT,High limit for External Diode 3 Register" line.byte 0x8 "EXT4_TMPLO_LMT,Low limit for External Diode 4 Register" hexmask.byte 0x8 0.--7. 1. "TMPLO4_LIMIT,Low limit for External Diode 4 Register" line.byte 0x9 "EXT4_TMPHI_LMT,High limit for External Diode 4 Register" hexmask.byte 0x9 0.--7. 1. "TMPHI4_LIMIT,High limit for External Diode 4 Register" line.byte 0xA "EXT1A_TMPLO_LMT,Low limit for External Diode 1A Register" hexmask.byte 0xA 0.--7. 1. "TMPLO1A_LIMIT,Low limit for External Diode 1A Register" line.byte 0xB "EXT1A_TMPHI_LMT,High limit for External Diode 1A Register" hexmask.byte 0xB 0.--7. 1. "TMPHI1A_LIMIT,High limit for External Diode 1A Register" line.byte 0xC "EXT2A_TMPLO_LMT,Low limit for External Diode 2A Register" hexmask.byte 0xC 0.--7. 1. "TMPLO2A_LIMIT,Low limit for External Diode 2A Register" line.byte 0xD "EXT2A_TMPHI_LMT,High limit for External Diode 2A Register" hexmask.byte 0xD 0.--7. 1. "TMPHI2A_LIMIT,High limit for External Diode 2A Register" line.byte 0xE "EXT3A_TMPLO_LMT,Low limit for External Diode 3A Register" hexmask.byte 0xE 0.--7. 1. "TMPLO3A_LIMIT,Low limit for External Diode 3A Register" line.byte 0xF "EXT3A_TMPHI_LMT,High limit for External Diode 3A Register" hexmask.byte 0xF 0.--7. 1. "TMPHI3A_LIMIT,High limit for External Diode 3A Register" line.byte 0x10 "EXT4A_TMPLO_LMT,Low limit for External Diode 4A Register" hexmask.byte 0x10 0.--7. 1. "TMPLO4A_LIMIT,Low limit for External Diode 4A Register" line.byte 0x11 "EXT4A_TMPHI_LMT,High limit for External Diode 4A Register" hexmask.byte 0x11 0.--7. 1. "TMPHI4A_LIMIT,High limit for External Diode 4A Register" group.byte 0x64++0x1 line.byte 0x0 "BCOMP3_EN,External Diode3 Beta compensation Register" hexmask.byte 0x0 0.--7. 1. "BCOMP3_EN,Beta compensation settings for External Diode3 Enable" line.byte 0x1 "BCOMP4_EN,External Diode4 Beta compensation Register" hexmask.byte 0x1 0.--7. 1. "BCOMP4_EN,Beta compensation settings for External Diode4 Enable" group.byte 0x67++0x0 line.byte 0x0 "BCOMP_INTD_EN,Internal Diode Beta compensation Register" hexmask.byte 0x0 0.--7. 1. "BCOMP4_EN,Beta compensation settings for internal Diode1 Enable" group.byte 0x6C++0x0 line.byte 0x0 "CONV_SRATE,Conversion Seconds Rate Register" hexmask.byte 0x0 0.--7. 1. "CONV_SRATE,Conversion Seconds Rate Register" group.byte 0x6E++0x0 line.byte 0x0 "CONV_MOD,Conversion Mode Register" hexmask.byte 0x0 0.--7. 1. "CONV_MOD,Conversion Mode Register" group.byte 0x70++0x0 line.byte 0x0 "REC_EN,REC Enable Register" hexmask.byte 0x0 0.--7. 1. "REC_EN,Enables REC for all external diode channels" rgroup.byte 0x71++0x0 line.byte 0x0 "VSET_VLT,VSET Voltage Reading Register" hexmask.byte 0x0 0.--7. 1. "VSET_VLT,Stores the VSET Voltage Monitor reading" rgroup.byte 0x75++0x1 line.byte 0x0 "THERM1,Thermal Trip Temperature Diode 1 Register" hexmask.byte 0x0 0.--7. 1. "THERM1,Stores the calculated ThermTrip temperature high limit derived from the voltage on VSET and compared against External Diode 1." line.byte 0x1 "FLSF_STS,FailSafe Status Register" hexmask.byte 0x1 0.--7. 1. "FLSF_STS,Stores the status indicate which ThermTrip input condition caused the SYS_SHDN# pin to be asserted." group.byte 0x77++0x0 line.byte 0x0 "FLSF_CFG,FailSafe Configuration Register" hexmask.byte 0x0 0.--7. 1. "FLSF_CFG,Stores configuration bits that are retained over all power modes" rgroup.byte 0x78++0x0 line.byte 0x0 "SHDN_STS,Shutdown Status Register" hexmask.byte 0x0 0.--7. 1. "SHDN_STS,Stores the status bits that indicate which diode caused the SYS_SHDN# output to assert." group.byte 0x79++0x5 line.byte 0x0 "SHDN_CFG,Shutdown Configuration Register" hexmask.byte 0x0 0.--7. 1. "SHDN_CFG,Stores configuration bits that are retained over all power modes" line.byte 0x1 "FLT_INTSTS_EN,Fault Interrupt Status Enable Register" hexmask.byte 0x1 0.--7. 1. "FLT_INTSTS_EN,Controls whether the External Diode Fault events generates interrupt if the associated status bit is 1." line.byte 0x2 "TMP_INTSTS,Temp Interrupt Status Enable Register" hexmask.byte 0x2 0.--7. 1. "TMP_INTSTS,Controls whether the External Diode events generate an interrupt if the associated status bit is set." line.byte 0x3 "SPCL_FN,Special Function Register" hexmask.byte 0x3 0.--7. 1. "TMP_INTSTS,Controls the bit that resets the FailSafe Status Register" line.byte 0x4 "INTTMP_INTEN,Int Temp Interrupt Status Enable Register" hexmask.byte 0x4 0.--7. 1. "INTTMP_INTEN,Controls whether the Internal Diode event generate an interrupt if the associated status bit is set." line.byte 0x5 "VLT_INTEN,Volt Interrupt Status Enable Register" hexmask.byte 0x5 0.--7. 1. "VLT_INTEN,Controls whether the Voltage event generate an interrupt if the associated status bit is set." group.byte 0x80++0x6 line.byte 0x0 "THRMTRP_TMP2,Thermal Trip Temperature Diode 2 Register" hexmask.byte 0x0 0.--7. 1. "THRMTRP_TMP2,ThermTrip temperature high limit compared against External Diode 2" line.byte 0x1 "THRMTRP_TMP3,Thermal Trip Temperature Diode 3 Register" hexmask.byte 0x1 0.--7. 1. "THRMTRP_TMP3,ThermTrip temperature high limit compared against External Diode 3" line.byte 0x2 "THRMTRP_TMP4,Thermal Trip Temperature Diode 4 Register" hexmask.byte 0x2 0.--7. 1. "THRMTRP_TMP4,ThermTrip temperature high limit compared against External Diode 4" line.byte 0x3 "THRMTRP_TMP1A,Thermal Trip Temperature Diode 1A Register" hexmask.byte 0x3 0.--7. 1. "THRMTRP_TMP1A,ThermTrip temperature high limit compared against External Diode 1A" line.byte 0x4 "THRMTRP_TMP2A,Thermal Trip Temperature Diode 2A Register" hexmask.byte 0x4 0.--7. 1. "THRMTRP_TMP2A,ThermTrip temperature high limit compared against External Diode 2A" line.byte 0x5 "THRMTRP_TMP3A,Thermal Trip Temperature Diode 3A Register" hexmask.byte 0x5 0.--7. 1. "THRMTRP_TMP3A,ThermTrip temperature high limit compared against External Diode 3A" line.byte 0x6 "THRMTRP_TMP4A,Thermal Trip Temperature Diode 4A Register" hexmask.byte 0x6 0.--7. 1. "THRMTRP_TMP4A,ThermTrip temperature high limit compared against External Diode 4A" group.byte 0x88++0x7 line.byte 0x0 "ADJ_CH1,Adjusted Channel 1 Register" hexmask.byte 0x0 0.--7. 1. "ADJ_CH1,Contain EMC IP Trim Adjust values for External Channel 1" line.byte 0x1 "ADJ_CH2,Adjusted Channel 2 Register" hexmask.byte 0x1 0.--7. 1. "ADJ_CH2,Contain EMC IP Trim Adjust values for External Channel 2" line.byte 0x2 "ADJ_CH3,Adjusted Channel 3 Register" hexmask.byte 0x2 0.--7. 1. "ADJ_CH3,Contain EMC IP Trim Adjust values for External Channel 3" line.byte 0x3 "ADJ_CH4,Adjusted Channel 4 Register" hexmask.byte 0x3 0.--7. 1. "ADJ_CH4,Contain EMC IP Trim Adjust values for External Channel 4" line.byte 0x4 "ADJ_CH1A,Adjusted Channel 1A Register" hexmask.byte 0x4 0.--7. 1. "ADJ_CH1A,Contain EMC IP Trim Adjust values for External Channel 1A" line.byte 0x5 "ADJ_CH2A,Adjusted Channel 2A Register" hexmask.byte 0x5 0.--7. 1. "ADJ_CH2A,Contain EMC IP Trim Adjust values for External Channel 2A" line.byte 0x6 "ADJ_CH3A,Adjusted Channel 3A Register" hexmask.byte 0x6 0.--7. 1. "ADJ_CH3A,Contain EMC IP Trim Adjust values for External Channel 3A" line.byte 0x7 "ADJ_CH4A,Adjusted Channel 4A Register" hexmask.byte 0x7 0.--7. 1. "ADJ_CH4A,Contain EMC IP Trim Adjust values for External Channel 4A" rgroup.byte 0xFC++0x0 line.byte 0x0 "UNLCK,Unlock Register" hexmask.byte 0x0 0.--7. 1. "UNLCK,Unlock Register" rgroup.byte 0x400++0x0 line.byte 0x0 "SYS_SHDN_RST,System Shutdown Reset Register" hexmask.byte 0x0 0.--7. 1. "SYS_SHDN_RST,Used to de-assert the SYS_SHDN# signal Register" tree.end endif sif (cpuis("CEC1702*")) tree "FAN (Fan Tachometer)" base ad:0x0 tree "FAN0" base ad:0x4000A000 group.word 0x0++0x3 line.word 0x0 "SET,The Fan Driver Setting used to control the output of the Fan Driver." hexmask.word 0x0 6.--15. 1. "FAN_SETTING,The Fan Driver Setting used to control the output of the Fan Driver." line.word 0x2 "CFG,The Fan Configuration Register controls the general operation of the RPM based Fan Control Algorithm used by the fan driver." bitfld.word 0x2 15. "EN_RRC,Enables the ramp rate control circuitry during the Manual Mode of operation.\n 1=The ramp rate control circuitry for the Manual Mode of operation is enabled. The PWM setting will follow the ramp rate controls\n as determined by the.." "0: The ramp rate control circuitry for the Manual..,1: The ramp rate control circuitry for the Manual.." newline bitfld.word 0x2 14. "DIS_GLITCH,Disables the low pass glitch filter that removes high frequency noise injected on the TACH pin.\n 1 - The glitch filter is disabled.\n 0 - The glitch filter is enabled." "0,1" newline bitfld.word 0x2 12.--13. "DER_OPT,Control some of the advanced options that affect the derivative portion of the RPM based fan control algorithm.\n These bits only apply if the Fan Speed Control Algorithm is used." "0,1,2,3" newline bitfld.word 0x2 10.--11. "ERR_RNG,Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed\n error window around the target speed the fan drive setting is not updated. These bits only apply if the Fan Speed.." "0: 0 RPM,1: 50 RPM\n,2: 100 RPM\n,3: 200 RPM\n" newline bitfld.word 0x2 9. "POLARITY,Determines the polarity of the PWM driver. This does NOT affect the drive setting registers. A setting of 0% drive will\n still correspond to 0% drive independent of the polarity.\n 1 - The Polarity of the PWM driver is inverted. A.." "0,1" newline bitfld.word 0x2 7. "EN_ALGO,Enables the RPM based Fan Control Algorithm.\n 1=The control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed\n as indicated by the TACH Target Register.\n.." "0: The control circuitry is disabled and the fan..,1: The control circuitry is enabled and the Fan.." newline bitfld.word 0x2 5.--6. "RANGE,Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all\n TACH values (including the Valid TACH Count TACH Target and TACH reading).\n 3=Reported Minimum RPM:.." "0: Reported Minimum RPM: 500,1: Reported Minimum RPM: 1000,2: Reported Minimum RPM: 2000,3: Reported Minimum RPM: 4000" newline bitfld.word 0x2 3.--4. "EDGES,Determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical\n fan measured 5 edges (for a 2-pole fan). Increasing the number of edges measured with respect to the number of poles of.." "0,1,2,3" newline bitfld.word 0x2 0.--2. "UPDATE,Determines the base time between fan driver updates. The Update Time along with the Fan Step Register is used to control\n the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan.." "0: 100ms\n Note: This ramp rate control applies for..,1: 200ms\n,2: 300ms\n,3: 400ms\n,4: 500ms\n,5: 800ms\n,6: 1200ms\n,7: 1600ms\n" group.byte 0x4++0x5 line.byte 0x0 "PWM_DIV,PWM Divide" hexmask.byte 0x0 0.--7. 1. "PWM_DIV,The PWM Divide value determines the final frequency of the PWM driver. The driver base frequency is divided by the\n PWM Divide value to determine the final frequency." line.byte 0x1 "GAIN,Gain Register stores the gain terms used by the proportional and integral portions of the RPM based Fan Control Algorithm." bitfld.byte 0x1 4.--5. "GAIND,The derivative gain term.\n Gain Factor:\n 3=8x\n 2=4x\n 1=2x\n 0=1x" "0: 1x,1: 2x\n,2: 4x\n,3: 8x\n" newline bitfld.byte 0x1 2.--3. "GAINI,The integral gain term.\n Gain Factor:\n 3=8x\n 2=4x\n 1=2x\n 0=1x" "0: 1x,1: 2x\n,2: 4x\n,3: 8x\n" newline bitfld.byte 0x1 0.--1. "GAINP,The proportional gain term.\n Gain Factor:\n 3=8x\n 2=4x\n 1=2x\n 0=1x" "0: 1x,1: 2x\n,2: 4x\n,3: 8x\n" line.byte 0x2 "SPIN_UP_CFG,The Fan Spin Up Configuration Register controls the settings of Spin Up Routine." bitfld.byte 0x2 6.--7. "DRIVE_FAIL_CNT,Determines how many update cycles are used for the Drive Fail detection function. This circuitry determines whether the\n fan can be driven to the desired Tach target. These settings only apply if the Fan Speed Control Algorithm is.." "0: Drive Fail detection circuitry is disabled,1: Drive Fail detection circuitry will count for 16..,2: Drive Fail detection circuitry will count for 32..,3: Drive Fail detection circuitry will count for 64.." newline bitfld.byte 0x2 5. "NOKICK,Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before\n driving it at the programmed level.\n 1=The Spin Up Routine will not drive the PWM to 100%. It will set.." "0: The Spin Up Routine will drive the PWM to 100%..,1: The Spin Up Routine will not drive the PWM to 100%" newline bitfld.byte 0x2 2.--4. "SPIN_LVL,Determines the final drive level that is used by the Spin Up Routine.\n 7=65%\n 6=60%\n 5=55%\n 4=50%\n 3=45%\n 2=40%\n 1=35%\n 0=30%" "0: 30%,1: 35%\n,2: 40%\n,3: 45%\n,4: 50%\n,5: 55%\n,6: 60%\n,7: 65%\n" newline bitfld.byte 0x2 0.--1. "SPINUP_TIME,Determines the maximum Spin Time that the Spin Up Routine will run for. If a valid tachometer measurement is not\n detected before the Spin Time has elapsed an interrupt will be generated. When the RPM based Fan Control Algorithm.." "0: 250 ms,1: 500 ms\n,2: 1 second\n,3: 2 seconds\n" line.byte 0x3 "STEP,FAN_STEP The Fan Step value represents the maximum step size the fan driver will take between update times" hexmask.byte 0x3 0.--7. 1. "FAN_STEP,The Fan Step value represents the maximum step size the fan driver will take between update times.\n When the PWM_BASE frequency range field in the PWM Driver Base Frequency Register is set to the value 1 2 or 3 this 8-bit field\n.." line.byte 0x4 "MIN_DRIVE,the minimum drive setting for the RPM based Fan Control Algorithm." hexmask.byte 0x4 0.--7. 1. "MIN_DRIVE,The minimum drive setting." line.byte 0x5 "VAL_TACH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." hexmask.byte 0x5 0.--7. 1. "VALID_TACH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." group.word 0xA++0x5 line.word 0x0 "DRIVE_FAIL_BAND,The number of Tach counts used by the Fan Drive Fail detection circuitry" hexmask.word 0x0 3.--15. 1. "FAN_DRIVE_FAIL_BAND,The number of Tach counts used by the Fan Drive Fail detection circuitry." line.word 0x2 "TACH_TGT,The target tachometer value." hexmask.word 0x2 3.--15. 1. "TACH_TGT,The target tachometer value." line.word 0x4 "TACH_RD,[15:3] The current tachometer reading value." hexmask.word 0x4 3.--15. 1. "TACH_RD,The current tachometer reading value." group.byte 0x10++0x1 line.byte 0x0 "DRIV_BASE_FREQ,[1:0] Determines the frequency range of the PWM fan driver" bitfld.byte 0x0 0.--1. "PWM_BASE,Determines the frequency range of the PWM fan driver (when enabled). PWM resolution is 10-bit except when this field\n is set to '0b' when it is 8-bit.\n 3=2.34KHz\n 2=4.67KHz\n.." "0: 26,1: 23,2: 4,3: 2" line.byte 0x1 "STS,The bits in this register are routed to interrupts." bitfld.byte 0x1 5. "DRIVE_FAIL,The bit Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting at\n maximum drive. (R/WC)\n 1- The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target.." "0,1" newline bitfld.byte 0x1 1. "FAN_SPIN,The bit Indicates that the Spin up Routine for the Fan could not detect a valid tachometer reading within its maximum\n time window. (R/WC)\n 1 - The Spin up Routine for the Fan could not detect a valid tachometer reading.." "0,1" newline bitfld.byte 0x1 0. "FAN_STALL,The bit Indicates that the tachometer measurement on the Fan detects a stalled fan. (R/WC)\n 0 - Stalled fan not detected.\n 1 - Stalled fan detected." "0,1" tree.end tree "FAN1" base ad:0x4000A080 group.word 0x0++0x3 line.word 0x0 "SET,The Fan Driver Setting used to control the output of the Fan Driver." hexmask.word 0x0 6.--15. 1. "FAN_SETTING,The Fan Driver Setting used to control the output of the Fan Driver." line.word 0x2 "CFG,The Fan Configuration Register controls the general operation of the RPM based Fan Control Algorithm used by the fan driver." bitfld.word 0x2 15. "EN_RRC,Enables the ramp rate control circuitry during the Manual Mode of operation.\n 1=The ramp rate control circuitry for the Manual Mode of operation is enabled. The PWM setting will follow the ramp rate controls\n as determined by the.." "0: The ramp rate control circuitry for the Manual..,1: The ramp rate control circuitry for the Manual.." newline bitfld.word 0x2 14. "DIS_GLITCH,Disables the low pass glitch filter that removes high frequency noise injected on the TACH pin.\n 1 - The glitch filter is disabled.\n 0 - The glitch filter is enabled." "0,1" newline bitfld.word 0x2 12.--13. "DER_OPT,Control some of the advanced options that affect the derivative portion of the RPM based fan control algorithm.\n These bits only apply if the Fan Speed Control Algorithm is used." "0,1,2,3" newline bitfld.word 0x2 10.--11. "ERR_RNG,Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed\n error window around the target speed the fan drive setting is not updated. These bits only apply if the Fan Speed.." "0: 0 RPM,1: 50 RPM\n,2: 100 RPM\n,3: 200 RPM\n" newline bitfld.word 0x2 9. "POLARITY,Determines the polarity of the PWM driver. This does NOT affect the drive setting registers. A setting of 0% drive will\n still correspond to 0% drive independent of the polarity.\n 1 - The Polarity of the PWM driver is inverted. A.." "0,1" newline bitfld.word 0x2 7. "EN_ALGO,Enables the RPM based Fan Control Algorithm.\n 1=The control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed\n as indicated by the TACH Target Register.\n.." "0: The control circuitry is disabled and the fan..,1: The control circuitry is enabled and the Fan.." newline bitfld.word 0x2 5.--6. "RANGE,Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all\n TACH values (including the Valid TACH Count TACH Target and TACH reading).\n 3=Reported Minimum RPM:.." "0: Reported Minimum RPM: 500,1: Reported Minimum RPM: 1000,2: Reported Minimum RPM: 2000,3: Reported Minimum RPM: 4000" newline bitfld.word 0x2 3.--4. "EDGES,Determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical\n fan measured 5 edges (for a 2-pole fan). Increasing the number of edges measured with respect to the number of poles of.." "0,1,2,3" newline bitfld.word 0x2 0.--2. "UPDATE,Determines the base time between fan driver updates. The Update Time along with the Fan Step Register is used to control\n the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan.." "0: 100ms\n Note: This ramp rate control applies for..,1: 200ms\n,2: 300ms\n,3: 400ms\n,4: 500ms\n,5: 800ms\n,6: 1200ms\n,7: 1600ms\n" group.byte 0x4++0x5 line.byte 0x0 "PWM_DIV,PWM Divide" hexmask.byte 0x0 0.--7. 1. "PWM_DIV,The PWM Divide value determines the final frequency of the PWM driver. The driver base frequency is divided by the\n PWM Divide value to determine the final frequency." line.byte 0x1 "GAIN,Gain Register stores the gain terms used by the proportional and integral portions of the RPM based Fan Control Algorithm." bitfld.byte 0x1 4.--5. "GAIND,The derivative gain term.\n Gain Factor:\n 3=8x\n 2=4x\n 1=2x\n 0=1x" "0: 1x,1: 2x\n,2: 4x\n,3: 8x\n" newline bitfld.byte 0x1 2.--3. "GAINI,The integral gain term.\n Gain Factor:\n 3=8x\n 2=4x\n 1=2x\n 0=1x" "0: 1x,1: 2x\n,2: 4x\n,3: 8x\n" newline bitfld.byte 0x1 0.--1. "GAINP,The proportional gain term.\n Gain Factor:\n 3=8x\n 2=4x\n 1=2x\n 0=1x" "0: 1x,1: 2x\n,2: 4x\n,3: 8x\n" line.byte 0x2 "SPIN_UP_CFG,The Fan Spin Up Configuration Register controls the settings of Spin Up Routine." bitfld.byte 0x2 6.--7. "DRIVE_FAIL_CNT,Determines how many update cycles are used for the Drive Fail detection function. This circuitry determines whether the\n fan can be driven to the desired Tach target. These settings only apply if the Fan Speed Control Algorithm is.." "0: Drive Fail detection circuitry is disabled,1: Drive Fail detection circuitry will count for 16..,2: Drive Fail detection circuitry will count for 32..,3: Drive Fail detection circuitry will count for 64.." newline bitfld.byte 0x2 5. "NOKICK,Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before\n driving it at the programmed level.\n 1=The Spin Up Routine will not drive the PWM to 100%. It will set.." "0: The Spin Up Routine will drive the PWM to 100%..,1: The Spin Up Routine will not drive the PWM to 100%" newline bitfld.byte 0x2 2.--4. "SPIN_LVL,Determines the final drive level that is used by the Spin Up Routine.\n 7=65%\n 6=60%\n 5=55%\n 4=50%\n 3=45%\n 2=40%\n 1=35%\n 0=30%" "0: 30%,1: 35%\n,2: 40%\n,3: 45%\n,4: 50%\n,5: 55%\n,6: 60%\n,7: 65%\n" newline bitfld.byte 0x2 0.--1. "SPINUP_TIME,Determines the maximum Spin Time that the Spin Up Routine will run for. If a valid tachometer measurement is not\n detected before the Spin Time has elapsed an interrupt will be generated. When the RPM based Fan Control Algorithm.." "0: 250 ms,1: 500 ms\n,2: 1 second\n,3: 2 seconds\n" line.byte 0x3 "STEP,FAN_STEP The Fan Step value represents the maximum step size the fan driver will take between update times" hexmask.byte 0x3 0.--7. 1. "FAN_STEP,The Fan Step value represents the maximum step size the fan driver will take between update times.\n When the PWM_BASE frequency range field in the PWM Driver Base Frequency Register is set to the value 1 2 or 3 this 8-bit field\n.." line.byte 0x4 "MIN_DRIVE,the minimum drive setting for the RPM based Fan Control Algorithm." hexmask.byte 0x4 0.--7. 1. "MIN_DRIVE,The minimum drive setting." line.byte 0x5 "VAL_TACH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." hexmask.byte 0x5 0.--7. 1. "VALID_TACH_CNT,The maximum TACH Reading Register value to indicate that the fan is spinning properly." group.word 0xA++0x5 line.word 0x0 "DRIVE_FAIL_BAND,The number of Tach counts used by the Fan Drive Fail detection circuitry" hexmask.word 0x0 3.--15. 1. "FAN_DRIVE_FAIL_BAND,The number of Tach counts used by the Fan Drive Fail detection circuitry." line.word 0x2 "TACH_TGT,The target tachometer value." hexmask.word 0x2 3.--15. 1. "TACH_TGT,The target tachometer value." line.word 0x4 "TACH_RD,[15:3] The current tachometer reading value." hexmask.word 0x4 3.--15. 1. "TACH_RD,The current tachometer reading value." group.byte 0x10++0x1 line.byte 0x0 "DRIV_BASE_FREQ,[1:0] Determines the frequency range of the PWM fan driver" bitfld.byte 0x0 0.--1. "PWM_BASE,Determines the frequency range of the PWM fan driver (when enabled). PWM resolution is 10-bit except when this field\n is set to '0b' when it is 8-bit.\n 3=2.34KHz\n 2=4.67KHz\n.." "0: 26,1: 23,2: 4,3: 2" line.byte 0x1 "STS,The bits in this register are routed to interrupts." bitfld.byte 0x1 5. "DRIVE_FAIL,The bit Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting at\n maximum drive. (R/WC)\n 1- The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target.." "0,1" newline bitfld.byte 0x1 1. "FAN_SPIN,The bit Indicates that the Spin up Routine for the Fan could not detect a valid tachometer reading within its maximum\n time window. (R/WC)\n 1 - The Spin up Routine for the Fan could not detect a valid tachometer reading.." "0,1" newline bitfld.byte 0x1 0. "FAN_STALL,The bit Indicates that the tachometer measurement on the Fan detects a stalled fan. (R/WC)\n 0 - Stalled fan not detected.\n 1 - Stalled fan detected." "0,1" tree.end tree.end endif sif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) tree "FPU (Floating Point Unit)" base ad:0xE000EF30 group.long 0x4++0xB line.long 0x0 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x0 31. "ASPEN" "0,1" bitfld.long 0x0 30. "LSPEN" "0,1" bitfld.long 0x0 8. "MONRDY" "0,1" bitfld.long 0x0 6. "BFRDY" "0,1" newline bitfld.long 0x0 5. "MMRDY" "0,1" bitfld.long 0x0 4. "HFRDY" "0,1" bitfld.long 0x0 3. "THREAD" "0,1" bitfld.long 0x0 1. "USER" "0,1" newline bitfld.long 0x0 0. "LSPACT" "0,1" line.long 0x4 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x4 3.--31. 1. "ADDRESS,Address for FP registers in exception stack frame" line.long 0x8 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP" "0,1" bitfld.long 0x8 25. "DN,Default value for FPSCR.DN" "0,1" bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ" "0,1" bitfld.long 0x8 22.--23. "RMODE,Default value for FPSCR.RMODE" "0: Round to Nearest,1: Round towards Positive Infinity,2: Round towards Negative Infinity,3: Round towards Zero" rgroup.long 0x10++0x7 line.long 0x0 "MVFR0,Media and FP Feature Register 0" hexmask.long.byte 0x0 28.--31. 1. "FP_rounding_modes" hexmask.long.byte 0x0 24.--27. 1. "Short_vectors" hexmask.long.byte 0x0 20.--23. 1. "Square_root" hexmask.long.byte 0x0 16.--19. 1. "Divide" newline hexmask.long.byte 0x0 12.--15. 1. "FP_excep_trapping" hexmask.long.byte 0x0 8.--11. 1. "Double_precision" hexmask.long.byte 0x0 4.--7. 1. "Single_precision" hexmask.long.byte 0x0 0.--3. 1. "A_SIMD_registers" line.long 0x4 "MVFR1,Media and FP Feature Register 1" hexmask.long.byte 0x4 28.--31. 1. "FP_fused_MAC" hexmask.long.byte 0x4 24.--27. 1. "FP_HPFP" hexmask.long.byte 0x4 4.--7. 1. "D_NaN_mode" hexmask.long.byte 0x4 0.--3. 1. "FtZ_mode" tree.end endif tree "GCR (Logical Device Configuration)" base ad:0x400FFF00 group.byte 0x7++0x0 line.byte 0x0 "LDN,A write to this register selects the current logical device. This allows access to the control and configuration\n registers for each logical device. Note: The Activate command operates only on the selected logical device." sif (cpuis("CEC1712*")) rgroup.byte 0x1C++0x1 line.byte 0x0 "DEV_REV,A read-only register which provides device revision information." line.byte 0x1 "DEV_SUBID,A read-only register which provides device sub ID information." rgroup.word 0x1E++0x1 line.word 0x0 "DEV_ID,A read-only register which provides device identification." rgroup.byte 0x20++0x0 line.byte 0x0 "LEG_DEV_ID,A read-only register which provides legacy device identification." endif sif (cpuis("CEC1734?2HW*")) rgroup.byte 0x1C++0x1 line.byte 0x0 "DEV_REV,A read-only register which provides device revision information." line.byte 0x1 "DEV_SUBID,A read-only register which provides device sub ID information." rgroup.word 0x1E++0x1 line.word 0x0 "DEV_ID,A read-only register which provides device identification LSB." rgroup.byte 0x20++0x0 line.byte 0x0 "LEG_DEV_ID,A read-only register which provides legacy device identification." endif sif (cpuis("CEC1734?2ZW*")) rgroup.byte 0x1C++0x1 line.byte 0x0 "DEV_REV,A read-only register which provides device revision information." line.byte 0x1 "DEV_SUBID,A read-only register which provides device sub ID information." rgroup.word 0x1E++0x1 line.word 0x0 "DEV_ID,A read-only register which provides device identification LSB." rgroup.byte 0x20++0x1 line.byte 0x0 "LEG_DEV_ID,A read-only register which provides legacy device identification." line.byte 0x1 "LEG_DEV_REV,A read-only register which provides legacy device revision information." rgroup.byte 0x24++0x1 line.byte 0x0 "OTP_ID,A read-only register which provides OTP ID information." line.byte 0x1 "VLD_ID,A read-only register which provides Validation ID information." endif sif (cpuis("CEC1736?2HW*")) rgroup.byte 0x1C++0x1 line.byte 0x0 "DEV_REV,A read-only register which provides device revision information." line.byte 0x1 "DEV_SUBID,A read-only register which provides device sub ID information." rgroup.word 0x1E++0x1 line.word 0x0 "DEV_ID,A read-only register which provides device identification LSB." rgroup.byte 0x20++0x1 line.byte 0x0 "LEG_DEV_ID,A read-only register which provides legacy device identification." line.byte 0x1 "LEG_DEV_REV,A read-only register which provides legacy device revision information." rgroup.byte 0x24++0x1 line.byte 0x0 "OTP_ID,A read-only register which provides OTP ID information." line.byte 0x1 "VLD_ID,A read-only register which provides Validation ID information." endif sif (cpuis("CEC1736?2ZW*")) rgroup.byte 0x1C++0x1 line.byte 0x0 "DEV_REV,A read-only register which provides device revision information." line.byte 0x1 "DEV_SUBID,A read-only register which provides device sub ID information." rgroup.word 0x1E++0x1 line.word 0x0 "DEV_ID,A read-only register which provides device identification LSB." rgroup.byte 0x20++0x1 line.byte 0x0 "LEG_DEV_ID,A read-only register which provides legacy device identification." line.byte 0x1 "LEG_DEV_REV,A read-only register which provides legacy device revision information." rgroup.byte 0x24++0x1 line.byte 0x0 "OTP_ID,A read-only register which provides OTP ID information." line.byte 0x1 "VLD_ID,A read-only register which provides Validation ID information." endif sif (cpuis("CEC1702*")) rgroup.byte 0x20++0x1 line.byte 0x0 "DEV_ID,A read-only register which provides device identification." line.byte 0x1 "DEV_REV,A read-only register which provides device revision information." endif sif (cpuis("CEC1712*")) rgroup.byte 0x21++0x0 line.byte 0x0 "LEG_DEV_REV,A read-only register which provides legacy device revision information." endif sif (cpuis("CEC1734?2HW*")) rgroup.byte 0x21++0x0 line.byte 0x0 "LEG_DEV_REV,A read-only register which provides legacy device revision information." rgroup.byte 0x24++0x2 line.byte 0x0 "OTP_ID,A read-only register which provides OTP ID information." line.byte 0x1 "VLD_ID,A read-only register which provides Validation ID information." line.byte 0x2 "BR_REV_ID,A read-only register which provides Boot ROM Revision ID information." endif sif (cpuis("CEC1734?2ZW*")) rgroup.byte 0x26++0x0 line.byte 0x0 "BR_REV_ID,A read-only register which provides Boot ROM Revision ID information." endif sif (cpuis("CEC1736?2HW*")) rgroup.byte 0x26++0x0 line.byte 0x0 "BR_REV_ID,A read-only register which provides Boot ROM Revision ID information." endif sif (cpuis("CEC1736?2ZW*")) rgroup.byte 0x26++0x0 line.byte 0x0 "BR_REV_ID,A read-only register which provides Boot ROM Revision ID information." endif tree.end sif (cpuis("CEC1702*")) tree "GP_SPI (General Purpose Serial Peripheral Interface)" base ad:0x40009400 group.long 0x0++0x7 line.long 0x0 "ENABLE,[0:0] 1=Enabled. The device is fully operational\n 0=Disabled. Clocks are gated to conserve power and the SPDOUT and SPI_CLK signals are set to their inactive state" line.long 0x4 "CTRL,SPI Control" bitfld.long 0x4 6. "CE,SPI Chip Select Enable.\n 1= SPI_CS# output signal is asserted i.e. driven to logic '0' \n 0= SPI_CS# output signal is deasserted i.e. driven to logic '1'" "0: SPI_CS# output signal is deasserted,1: SPI_CS# output signal is asserted" bitfld.long 0x4 5. "AUTO_RD,Auto Read Enable.\n 1=A read of the SPI RX_DATA Register will clear both the RXBF status bit and the TXBE status bit\n 0=A read of the SPI RX_DATA Register will clear the RXBF status bit. The TXBE status bit will not be.." "0: A read of the SPI RX_DATA Register will clear..,1: A read of the SPI RX_DATA Register will clear.." newline bitfld.long 0x4 4. "SOFT_RST,Soft Reset is a self-clearing bit. Writing zero to this bit has no effect. \n Writing a one to this bit resets the entire SPI Interface including all counters and registers back to their initial state." "0,1" bitfld.long 0x4 2.--3. "SPDIN_SEL,[3:2] 1xb=SPDIN1 and SPDIN2. Select this option for Dual Mode\n [3:2] 01b=SPDIN2 only. Select this option for Half Duplex\n [3:2] 00b=SPDIN1 only. Select this option for Full Duplex" "0,1,2,3" newline bitfld.long 0x4 1. "BIOEN,Bidirectional Output Enable control.\n 1=The SPDOUT_Direction signal configures the SPDOUT signal as an output.\n 0=The SPDOUT_Direction signal configures the SPDOUT signal as an input." "0: The SPDOUT_Direction signal configures the..,1: The SPDOUT_Direction signal configures the.." bitfld.long 0x4 0. "LSBF,Least Significant Bit First\n 1= The data is transferred in LSB-first order.\n 0= The data is transferred in MSB-first order. (default)" "0: The data is transferred in MSB-first order,1: The data is transferred in LSB-first order" rgroup.long 0x8++0x3 line.long 0x0 "STS,SPI Status" bitfld.long 0x0 2. "ACTIVE,ACTIVE status" "0,1" bitfld.long 0x0 1. "RXBF,1=RX_Data buffer is full 0=RX_Data buffer is not full" "0: RX_Data buffer is not full,1: RX_Data buffer is full" newline bitfld.long 0x0 0. "TXBE,1=TX_Data buffer is empty 0=TX_Data buffer is not empty" "0: TX_Data buffer is not empty,1: TX_Data buffer is empty" group.long 0xC++0xF line.long 0x0 "TX_DAT,[7:0] A write to this register when the \n Tx_Data buffer is empty (TXBE in the SPI Status Register is '1') initiates a SPI transaction." line.long 0x4 "RX_DAT,[7:0] This register is used to read the value returned by the external SPI device." line.long 0x8 "CLK_CTRL,SPI Clock Control. This register should not be changed during an active SPI transaction." bitfld.long 0x8 4. "CLKSRC,1=2MHz 0=48 MHz Ring Oscillator" "0: 48 MHz Ring Oscillator,1: 2MHz" bitfld.long 0x8 2. "CLKPOL,1=The SPI_CLK signal is high when the interface is idle and the first clock edge is a falling edge\n 0=The SPI_CLK is low when the interface is idle and the first clock edge is a rising edge" "0: The SPI_CLK is low when the interface is idle..,1: The SPI_CLK signal is high when the interface is.." newline bitfld.long 0x8 1. "RCLKPH,1=Valid data on SPDIN signal is expected after the first SPI_CLK edge. This data is sampled on the second and \n following even SPI_CLK edges (i.e. sample data on falling edge) 0=Valid data is expected on the SPDIN signal on the first.." "0: Valid data is expected on the SPDIN signal on..,1: Valid data on SPDIN signal is expected after the.." bitfld.long 0x8 0. "TCLKPH,1=Valid data is clocked out on the first SPI_CLK edge on SPDOUT signal. The slave device should sample this data on the second and \n following even SPI_CLK edges (i.e. sample data on falling edge) 0=Valid data is clocked out on the SPDOUT.." "0: Valid data is clocked out on the SPDOUT signal..,1: Valid data is clocked out on the first SPI_CLK.." line.long 0xC "CLK_GEN,[5:0] PRELOAD SPI Clock Generator Preload value." hexmask.long.byte 0xC 0.--5. 1. "PRLD,SPI Clock Generator Preload Value" tree.end endif tree "GPIO (General Purpose I/O)" base ad:0x40081000 sif (cpuis("CEC1702*")) repeat 172. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,Reads of this bit always return the state of GPIO input from the pad independent of the Mux selection for the pin\n or the Direction. This bit is forced high when the selected power well is off as selected by the POWER_GATING field in this.." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,Reads of this bit always return the last data written to the GPIO output data register bit; reads do not return the\n current output value of the GPIO pin if it is configured as an output. If the GPIO_OUTPUT_SEL T bit in this.." "0,1" newline bitfld.long 0x0 12.--13. "MUX_CTRL,This field determines the active signal function for a pin. 00 = GPIO Function Selected 01 = Signal Function 1 Selected \n 10 = Signal Function 2 Selected 11 = Signal Function 3 Selected." "0: GPIO Function Selected,1: Signal Function 1 Selected,?,?" bitfld.long 0x0 11. "POL,When the Polarity bit is set to '1' and the MUX_CONTROL bits are greater than '00' the selected signal function outputs\n are inverted and Interrupt Detection sense is inverted. When the MUX_CONTROL field selects the GPIO signal function.." "0: Non-inverted,1: Inverted" newline bitfld.long 0x0 10. "GPIO_OUT_SEL,This control bit determines which register is used to update the data register for GPIO outputs.\n 0=GPIO output data for this GPIO come from the ALTERNATE_GPIO_DATA field of this register; writes to the bit representing\n.." "0: GPIO output data for this GPIO come from the..,1: GPIO output data for this GPIO come from the bit.." bitfld.long 0x0 9. "GPIO_DIR,This bit controls the buffer direction only when the MUX_CONTROL field is '00' selecting the pin signal function to\n be GPIO. When the MUX_CONTROL field is greater than '00' (i.e. a non-GPIO signal function is selected) this bit has no.." "0: Input,1: Output" newline bitfld.long 0x0 8. "OUT_BUFF_TYPE,Unless explicitly stated otherwise pins with (I/O/OD) or (O/OD) in their buffer type column in the tables are\n compliant with the following Programmable OD/PP Multiplexing Design Rule: Each compliant pin has a programmable open.." "0: Push-Pull,1: Open Drain" bitfld.long 0x0 7. "EDGE_EN,When combined with the field INTERRUPT_DETECTION in this register determines the interrupt capability of the GPIO input.\n 0 = Edge detection disabled 1 = Edge detection enabled" "0: Edge detection disabled,1: Edge detection enabled" newline bitfld.long 0x0 4.--6. "INTR_DET,When combined with the field INTERRUPT_DETECTION in this register determines the interrupt capability of the GPIO input.\n 0 000 = Low Level Sensitive\n 0 001 = High Level Sensitive\n 0 100 = Interrupt.." "0: Low Level Sensitive\n 0,1: High Level Sensitive\n 0,?,?,?,?,?,?" bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off.\n 00 = VTR Power Rail 01 = VCC Main Power Rail (as determined by the VCC_PWRGD input) 1x = Reserved" "0: VTR Power Rail,1: VCC Main Power Rail,?,?" newline bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor.\n 00 = None 01 = Pull Up Enabled 10 = Pull Down Enabled 11 = None" "0: None,1: Pull Up Enabled,?,?" repeat.end repeat 172. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,These bits are used to select the drive strength on the pin. The drive strength is the same whether the pin is\n powered by 3.3V or 1.8V. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_RATE,This bit is used to select the slew rate on the pin. 0 = slow (half frequency) 1 = fast" "0: slow,1: fast" repeat.end endif repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x300)++0x3 line.long 0x0 "PARIN[$1],The GPIO Input Registers." repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x380)++0x3 line.long 0x0 "PAROUT[$1],The GPIO Output Registers." repeat.end sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL0[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "CTRL1[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "CTRL2[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "CTRL3[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "CTRL4[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xA0)++0x3 line.long 0x0 "CTRL5[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "CTRL6[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE0)++0x3 line.long 0x0 "CTRL7[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CTRL10[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x120)++0x3 line.long 0x0 "CTRL11[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "CTRL12[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x160)++0x3 line.long 0x0 "CTRL13[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "CTRL14[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A0)++0x3 line.long 0x0 "CTRL15[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "CTRL16[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E0)++0x3 line.long 0x0 "CTRL17[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "CTRL20[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x220)++0x3 line.long 0x0 "CTRL21[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "CTRL22[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x260)++0x3 line.long 0x0 "CTRL23[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CTRL24[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A0)++0x3 line.long 0x0 "CTRL25[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" repeat.end group.long 0x2C0++0x3 line.long 0x0 "CTRL260,GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,?,?,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0,1,2,3" endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P0[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x520)++0x3 line.long 0x0 "CTRL2P1[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x540)++0x3 line.long 0x0 "CTRL2P2[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x560)++0x3 line.long 0x0 "CTRL2P3[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x580)++0x3 line.long 0x0 "CTRL2P4[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5A0)++0x3 line.long 0x0 "CTRL2P5[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C0)++0x3 line.long 0x0 "CTRL2P6[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5E0)++0x3 line.long 0x0 "CTRL2P7[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x600)++0x3 line.long 0x0 "CTRL2P10[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x620)++0x3 line.long 0x0 "CTRL2P11[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x640)++0x3 line.long 0x0 "CTRL2P12[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x660)++0x3 line.long 0x0 "CTRL2P13[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "CTRL2P14[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6A0)++0x3 line.long 0x0 "CTRL2P15[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C0)++0x3 line.long 0x0 "CTRL2P16[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6E0)++0x3 line.long 0x0 "CTRL2P17[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "CTRL2P20[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x720)++0x3 line.long 0x0 "CTRL2P21[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x740)++0x3 line.long 0x0 "CTRL2P22[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x760)++0x3 line.long 0x0 "CTRL2P23[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "CTRL2P24[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1712*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x7A0)++0x3 line.long 0x0 "CTRL2P25[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end group.long 0x7C0++0x3 line.long 0x0 "CTRL2P260,The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,?,?" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL0[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "CTRL1[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "CTRL2[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "CTRL3[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "CTRL4[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xA0)++0x3 line.long 0x0 "CTRL5[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "CTRL6[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE0)++0x3 line.long 0x0 "CTRL7[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CTRL10[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x120)++0x3 line.long 0x0 "CTRL11[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "CTRL12[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x160)++0x3 line.long 0x0 "CTRL13[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "CTRL14[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A0)++0x3 line.long 0x0 "CTRL15[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "CTRL16[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E0)++0x3 line.long 0x0 "CTRL17[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "CTRL20[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x220)++0x3 line.long 0x0 "CTRL21[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "CTRL22[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x260)++0x3 line.long 0x0 "CTRL23[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CTRL24[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A0)++0x3 line.long 0x0 "CTRL25[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end group.long 0x2C0++0x3 line.long 0x0 "CTRL260,GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P0[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x520)++0x3 line.long 0x0 "CTRL2P1[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x540)++0x3 line.long 0x0 "CTRL2P2[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x560)++0x3 line.long 0x0 "CTRL2P3[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x580)++0x3 line.long 0x0 "CTRL2P4[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5A0)++0x3 line.long 0x0 "CTRL2P5[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C0)++0x3 line.long 0x0 "CTRL2P6[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5E0)++0x3 line.long 0x0 "CTRL2P7[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x600)++0x3 line.long 0x0 "CTRL2P10[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x620)++0x3 line.long 0x0 "CTRL2P11[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x640)++0x3 line.long 0x0 "CTRL2P12[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x660)++0x3 line.long 0x0 "CTRL2P13[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "CTRL2P14[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6A0)++0x3 line.long 0x0 "CTRL2P15[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C0)++0x3 line.long 0x0 "CTRL2P16[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6E0)++0x3 line.long 0x0 "CTRL2P17[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "CTRL2P20[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x720)++0x3 line.long 0x0 "CTRL2P21[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x740)++0x3 line.long 0x0 "CTRL2P22[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x760)++0x3 line.long 0x0 "CTRL2P23[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "CTRL2P24[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x7A0)++0x3 line.long 0x0 "CTRL2P25[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end group.long 0x7C0++0x3 line.long 0x0 "CTRL2P260,The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL0[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "CTRL1[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "CTRL2[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "CTRL3[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "CTRL4[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xA0)++0x3 line.long 0x0 "CTRL5[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "CTRL6[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE0)++0x3 line.long 0x0 "CTRL7[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CTRL10[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x120)++0x3 line.long 0x0 "CTRL11[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "CTRL12[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x160)++0x3 line.long 0x0 "CTRL13[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "CTRL14[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A0)++0x3 line.long 0x0 "CTRL15[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "CTRL16[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E0)++0x3 line.long 0x0 "CTRL17[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "CTRL20[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x220)++0x3 line.long 0x0 "CTRL21[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "CTRL22[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x260)++0x3 line.long 0x0 "CTRL23[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CTRL24[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A0)++0x3 line.long 0x0 "CTRL25[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end group.long 0x2C0++0x3 line.long 0x0 "CTRL260,GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P0[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x520)++0x3 line.long 0x0 "CTRL2P1[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x540)++0x3 line.long 0x0 "CTRL2P2[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x560)++0x3 line.long 0x0 "CTRL2P3[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x580)++0x3 line.long 0x0 "CTRL2P4[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5A0)++0x3 line.long 0x0 "CTRL2P5[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C0)++0x3 line.long 0x0 "CTRL2P6[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5E0)++0x3 line.long 0x0 "CTRL2P7[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x600)++0x3 line.long 0x0 "CTRL2P10[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x620)++0x3 line.long 0x0 "CTRL2P11[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x640)++0x3 line.long 0x0 "CTRL2P12[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x660)++0x3 line.long 0x0 "CTRL2P13[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "CTRL2P14[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6A0)++0x3 line.long 0x0 "CTRL2P15[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C0)++0x3 line.long 0x0 "CTRL2P16[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6E0)++0x3 line.long 0x0 "CTRL2P17[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "CTRL2P20[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x720)++0x3 line.long 0x0 "CTRL2P21[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x740)++0x3 line.long 0x0 "CTRL2P22[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x760)++0x3 line.long 0x0 "CTRL2P23[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "CTRL2P24[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1734?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x7A0)++0x3 line.long 0x0 "CTRL2P25[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end group.long 0x7C0++0x3 line.long 0x0 "CTRL2P260,The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL0[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "CTRL1[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "CTRL2[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "CTRL3[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "CTRL4[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xA0)++0x3 line.long 0x0 "CTRL5[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "CTRL6[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE0)++0x3 line.long 0x0 "CTRL7[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CTRL10[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x120)++0x3 line.long 0x0 "CTRL11[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "CTRL12[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x160)++0x3 line.long 0x0 "CTRL13[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "CTRL14[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A0)++0x3 line.long 0x0 "CTRL15[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "CTRL16[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E0)++0x3 line.long 0x0 "CTRL17[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "CTRL20[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x220)++0x3 line.long 0x0 "CTRL21[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "CTRL22[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x260)++0x3 line.long 0x0 "CTRL23[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CTRL24[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A0)++0x3 line.long 0x0 "CTRL25[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end group.long 0x2C0++0x3 line.long 0x0 "CTRL260,GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P0[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x520)++0x3 line.long 0x0 "CTRL2P1[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x540)++0x3 line.long 0x0 "CTRL2P2[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x560)++0x3 line.long 0x0 "CTRL2P3[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x580)++0x3 line.long 0x0 "CTRL2P4[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5A0)++0x3 line.long 0x0 "CTRL2P5[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C0)++0x3 line.long 0x0 "CTRL2P6[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5E0)++0x3 line.long 0x0 "CTRL2P7[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x600)++0x3 line.long 0x0 "CTRL2P10[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x620)++0x3 line.long 0x0 "CTRL2P11[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x640)++0x3 line.long 0x0 "CTRL2P12[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x660)++0x3 line.long 0x0 "CTRL2P13[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "CTRL2P14[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6A0)++0x3 line.long 0x0 "CTRL2P15[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C0)++0x3 line.long 0x0 "CTRL2P16[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6E0)++0x3 line.long 0x0 "CTRL2P17[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "CTRL2P20[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x720)++0x3 line.long 0x0 "CTRL2P21[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x740)++0x3 line.long 0x0 "CTRL2P22[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x760)++0x3 line.long 0x0 "CTRL2P23[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "CTRL2P24[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2HW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x7A0)++0x3 line.long 0x0 "CTRL2P25[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end group.long 0x7C0++0x3 line.long 0x0 "CTRL2P260,The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "CTRL0[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "CTRL1[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "CTRL2[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "CTRL3[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "CTRL4[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xA0)++0x3 line.long 0x0 "CTRL5[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xC0)++0x3 line.long 0x0 "CTRL6[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xE0)++0x3 line.long 0x0 "CTRL7[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "CTRL10[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x120)++0x3 line.long 0x0 "CTRL11[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x140)++0x3 line.long 0x0 "CTRL12[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x160)++0x3 line.long 0x0 "CTRL13[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "CTRL14[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1A0)++0x3 line.long 0x0 "CTRL15[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1C0)++0x3 line.long 0x0 "CTRL16[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x1E0)++0x3 line.long 0x0 "CTRL17[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "CTRL20[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x220)++0x3 line.long 0x0 "CTRL21[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x240)++0x3 line.long 0x0 "CTRL22[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x260)++0x3 line.long 0x0 "CTRL23[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x280)++0x3 line.long 0x0 "CTRL24[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x2A0)++0x3 line.long 0x0 "CTRL25[$1],GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." repeat.end group.long 0x2C0++0x3 line.long 0x0 "CTRL260,GPIO Pin Control Register" bitfld.long 0x0 24. "GPIO_INP,GPIO input from pin independent of the Mux selection for the pin or the Direction." "0,1" bitfld.long 0x0 16. "ALT_GPIO_DATA,GPIO Alternate Data Register." "0,1" newline bitfld.long 0x0 15. "INP_DIS,GPIO input disable" "0,1" bitfld.long 0x0 12.--14. "MUX_CTRL,00 = GPIO Function 01 = Function 1 10 = Function 2 11 = Function 3." "0: GPIO Function,1: Function 1,2: Signal function 2 selected,3: Signal function 3 selected,?,?,?,?" newline bitfld.long 0x0 11. "POL,1=Inverted; 0=Non-inverted" "0: Non-inverted,1: Inverted" bitfld.long 0x0 10. "GPIO_OUT_SEL,GPIO outputs registe select.0=GPIO ALTERNATE_GPIO_DATA 1=GPIO Output Register." "0: GPIO ALTERNATE_GPIO_DATA,1: GPIO Output Register" newline bitfld.long 0x0 9. "GPIO_DIR,Buffer direction when GPIO selected by pin mux 0 = Input 1 = Output" "0: Input,1: Output" bitfld.long 0x0 8. "OUT_BUFF_TYPE,0 = Push-Pull 1 = Open Drain" "0: Push-Pull,1: Open Drain" newline bitfld.long 0x0 7. "EDGE_EN,Determines the interrupt capability of the GPIO input." "0,1" bitfld.long 0x0 4.--6. "INTR_DET,Determines the interrupt capability of the GPIO input." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "PWR_GATING,The GPIO pin will be tristated when the selected power well is off." "0,1,2,3" bitfld.long 0x0 0.--1. "PU_PD,These bits are used to enable an internal pull-up or pull-down resistor." "0: None. Pin tristates when no active driver is..,1: Pull Up Enabled,2: Pull Down Enabled,3: Repeater mode. Pin is kept at previous voltage.." endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x500)++0x3 line.long 0x0 "CTRL2P0[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x520)++0x3 line.long 0x0 "CTRL2P1[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x540)++0x3 line.long 0x0 "CTRL2P2[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x560)++0x3 line.long 0x0 "CTRL2P3[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x580)++0x3 line.long 0x0 "CTRL2P4[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5A0)++0x3 line.long 0x0 "CTRL2P5[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5C0)++0x3 line.long 0x0 "CTRL2P6[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x5E0)++0x3 line.long 0x0 "CTRL2P7[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x600)++0x3 line.long 0x0 "CTRL2P10[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x620)++0x3 line.long 0x0 "CTRL2P11[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x640)++0x3 line.long 0x0 "CTRL2P12[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x660)++0x3 line.long 0x0 "CTRL2P13[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x680)++0x3 line.long 0x0 "CTRL2P14[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6A0)++0x3 line.long 0x0 "CTRL2P15[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C0)++0x3 line.long 0x0 "CTRL2P16[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6E0)++0x3 line.long 0x0 "CTRL2P17[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x700)++0x3 line.long 0x0 "CTRL2P20[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x720)++0x3 line.long 0x0 "CTRL2P21[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x740)++0x3 line.long 0x0 "CTRL2P22[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x760)++0x3 line.long 0x0 "CTRL2P23[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x780)++0x3 line.long 0x0 "CTRL2P24[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end endif sif (cpuis("CEC1736?2ZW*")) repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x7A0)++0x3 line.long 0x0 "CTRL2P25[$1],The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" repeat.end group.long 0x7C0++0x3 line.long 0x0 "CTRL2P260,The GPIO PIN_CTRL2 Registers" bitfld.long 0x0 4.--5. "DRIV_STREN,Selects the drive strength on the pin. 00 = 2mA 01 = 4mA 10 = 8mA 11 = 12mA" "0: 2mA,1: 4mA,2: For PIO12 = 8mA PIO24 = 16mA,3: For PIO12 = 12mA PIO24 = 24mA" bitfld.long 0x0 0. "SLEW_CTRL,Selects slew rate on the pin. 1=fast 0=slow" "0: slow,1: fast" endif tree.end tree "HTM (Hibernation Timer)" base ad:0x0 tree "HTM0" base ad:0x40009800 group.word 0x0++0x1 line.word 0x0 "PRLD,[15:0] This register is used to set the Hibernation Timer Preload value." group.word 0x4++0x1 line.word 0x0 "CTRL,HTimer Control Register" bitfld.word 0x0 0. "CTRL,1= The Hibernation Timer has a resolution of 0.125s per LSB which yields a maximum time in excess of 2 hours.\n 0= The Hibernation Timer has a resolution of 30.5us per LSB which yields a maximum time of ~2seconds." "0: The Hibernation Timer has a resolution of 30,1: The Hibernation Timer has a resolution of 0" rgroup.word 0x8++0x1 line.word 0x0 "CNT,The current state of the Hibernation Timer." tree.end tree "HTM1" base ad:0x40009820 group.word 0x0++0x1 line.word 0x0 "PRLD,[15:0] This register is used to set the Hibernation Timer Preload value." group.word 0x4++0x1 line.word 0x0 "CTRL,HTimer Control Register" bitfld.word 0x0 0. "CTRL,1= The Hibernation Timer has a resolution of 0.125s per LSB which yields a maximum time in excess of 2 hours.\n 0= The Hibernation Timer has a resolution of 30.5us per LSB which yields a maximum time of ~2seconds." "0: The Hibernation Timer has a resolution of 30,1: The Hibernation Timer has a resolution of 0" rgroup.word 0x8++0x1 line.word 0x0 "CNT,The current state of the Hibernation Timer." tree.end tree.end sif (cpuis("CEC1712*")) tree "I2C (Inter-Integrated Circuit)" base ad:0x0 tree "I2C0" base ad:0x40005100 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The (Last Received Bit) or (Address 0) (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." group.long 0x18++0x3 line.long 0x0 "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0x0 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD1,Reserved" group.long 0x20++0x3 line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." newline bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" newline bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x28++0x7 line.long 0x0 "CFG,Configuration Register" bitfld.long 0x0 15. "CNFG_PROMIS,This is the configur Promiscuous bit.\n 0: Normal operation is enabled. \n 1: Promiscuous Mode enabled General Call Address disabled Promiscuous Address Interrupt function enabled. Stall 9th clock of address byte.." "0: Normal operation is enabled,1: Promiscuous Mode enabled" bitfld.long 0x0 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x0 11.--13. "TEST0,Must be always written with 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x0 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x0 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x0 6.--7. "TEST,Must be always written with 0." "0,1,2,3" bitfld.long 0x0 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" newline bitfld.long 0x0 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0x4 "BUSCLK,Bus Clock Register" hexmask.long.byte 0x4 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0x4 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BB_CTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "CLKSYNC,This is Clock Sync Register. This register must not be written. or undesirable results may occur.\n" hexmask.byte 0x0 0.--7. 1. "CLK_SYNC,This register must not be written or undesirable results may occur." group.long 0x40++0x7 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled. \n 0=Start Bit Detection Interrupt disabled.\n" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register.\n" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores the value of the Slave Address and Direction Bit from the 1st byte of a Slave transfer.\n This is loaded immediately upon receipt of the address byte before the ACK/NAK 9th clock. \n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register. This register bit will be functional only in Promiscuous mode.\n" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt. This bit is functional only in Promiscuous mode. This bit is set \n on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. In other.." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register.\n" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register. This register is functional only in Promiscuous mode.\n" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. This bit has no effect in Normal mode of operation.\n 1= ACK the address byte. \n 0= NAK the address byte. \n" "0: NAK the address byte,1: ACK the address byte" tree.end tree "I2C1" base ad:0x40005200 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The (Last Received Bit) or (Address 0) (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." group.long 0x18++0x3 line.long 0x0 "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0x0 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD1,Reserved" group.long 0x20++0x3 line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." newline bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" newline bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x28++0x7 line.long 0x0 "CFG,Configuration Register" bitfld.long 0x0 15. "CNFG_PROMIS,This is the configur Promiscuous bit.\n 0: Normal operation is enabled. \n 1: Promiscuous Mode enabled General Call Address disabled Promiscuous Address Interrupt function enabled. Stall 9th clock of address byte.." "0: Normal operation is enabled,1: Promiscuous Mode enabled" bitfld.long 0x0 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x0 11.--13. "TEST0,Must be always written with 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x0 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x0 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x0 6.--7. "TEST,Must be always written with 0." "0,1,2,3" bitfld.long 0x0 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" newline bitfld.long 0x0 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0x4 "BUSCLK,Bus Clock Register" hexmask.long.byte 0x4 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0x4 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BB_CTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "CLKSYNC,This is Clock Sync Register. This register must not be written. or undesirable results may occur.\n" hexmask.byte 0x0 0.--7. 1. "CLK_SYNC,This register must not be written or undesirable results may occur." group.long 0x40++0x7 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled. \n 0=Start Bit Detection Interrupt disabled.\n" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register.\n" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores the value of the Slave Address and Direction Bit from the 1st byte of a Slave transfer.\n This is loaded immediately upon receipt of the address byte before the ACK/NAK 9th clock. \n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register. This register bit will be functional only in Promiscuous mode.\n" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt. This bit is functional only in Promiscuous mode. This bit is set \n on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. In other.." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register.\n" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register. This register is functional only in Promiscuous mode.\n" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. This bit has no effect in Normal mode of operation.\n 1= ACK the address byte. \n 0= NAK the address byte. \n" "0: NAK the address byte,1: ACK the address byte" tree.end tree "I2C2" base ad:0x40005300 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The (Last Received Bit) or (Address 0) (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." group.long 0x18++0x3 line.long 0x0 "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0x0 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD1,Reserved" group.long 0x20++0x3 line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." newline bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" newline bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x28++0x7 line.long 0x0 "CFG,Configuration Register" bitfld.long 0x0 15. "CNFG_PROMIS,This is the configur Promiscuous bit.\n 0: Normal operation is enabled. \n 1: Promiscuous Mode enabled General Call Address disabled Promiscuous Address Interrupt function enabled. Stall 9th clock of address byte.." "0: Normal operation is enabled,1: Promiscuous Mode enabled" bitfld.long 0x0 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x0 11.--13. "TEST0,Must be always written with 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x0 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x0 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x0 6.--7. "TEST,Must be always written with 0." "0,1,2,3" bitfld.long 0x0 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" newline bitfld.long 0x0 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0x4 "BUSCLK,Bus Clock Register" hexmask.long.byte 0x4 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0x4 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BB_CTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "CLKSYNC,This is Clock Sync Register. This register must not be written. or undesirable results may occur.\n" hexmask.byte 0x0 0.--7. 1. "CLK_SYNC,This register must not be written or undesirable results may occur." group.long 0x40++0x7 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled. \n 0=Start Bit Detection Interrupt disabled.\n" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register.\n" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores the value of the Slave Address and Direction Bit from the 1st byte of a Slave transfer.\n This is loaded immediately upon receipt of the address byte before the ACK/NAK 9th clock. \n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register. This register bit will be functional only in Promiscuous mode.\n" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt. This bit is functional only in Promiscuous mode. This bit is set \n on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. In other.." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register.\n" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register. This register is functional only in Promiscuous mode.\n" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. This bit has no effect in Normal mode of operation.\n 1= ACK the address byte. \n 0= NAK the address byte. \n" "0: NAK the address byte,1: ACK the address byte" tree.end tree.end endif sif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) tree "IMSPI (Internal Master SPI)" base ad:0x40220000 group.long 0x0++0xF line.long 0x0 "MODE,IMSPI Mode Register" bitfld.long 0x0 24.--25. "IF_MODE,This field sets the interface mode for the SPI controller. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single Mode." "0: Single Mode,1: Dual Mode,2: Quad Mode,3: Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "CLOCK_DIVIDE,This SPI clock divide in terms of the number of system clocks. 255:1=The SPI clock period is equal to this number of system clocks. 0=The SPI clock period is equal to 256 system clocks." newline bitfld.long 0x0 10. "CPHA_MISO,This field is the CPHA field of the underlying SPI controller which affects only the MISO Data. This field changes determines the clock edge on which data are captured in combination with the CPOL field. For standard SPI Modes this must.." "0: If CPOL=0,1: If CPOL=0" newline bitfld.long 0x0 9. "CPHA_MOSI,This field is the CPHA field of the underlying SPI controller which affects only the MOSI Data. This field changes determines the clock edge on which data are sent in combination with the CPOL field. 1=If CPOL=0 data sent on Rising Edge;.." "0: If CPOL=0,1: If CPOL=0" newline bitfld.long 0x0 8. "CPOL,This bit corresponds to the Polarity control for the underlying SPI controller. It describes the default state of the SPI Clock signal. 1=The clock starts in a high state; 0=The clock starts in a low state." "0: The clock starts in a low state,1: The clock starts in a high state" newline bitfld.long 0x0 2. "DLY2_SUSB,This bit is routed to the DLY2_SUSB# pin function." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,A write of '1b' to this bit resets the controller. This bit is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACTIVATE,This bit enables the controller. 1=The controller is enabled; 0=The controller is disabled and placed in its lowest power state." "0: The controller is disabled and placed in its..,1: The controller is enabled" line.long 0x4 "STATUS,IMSPI Status Register" bitfld.long 0x4 1. "INVALID_RESPONSE,The IMSPI has detected an invalid response field and therefore is aborting the transfer in failure. 1=A transfer error occurred due to an invalid response; 0=No error occurred. (R/WC)" "0: No error occurred,1: A transfer error occurred due to an invalid.." newline bitfld.long 0x4 0. "TIMEOUT,This flags when a transfer has terminated due to timeout on the response phase. 1=A transfer error occurred due to an invalid response; 0=No error occurred. (R/WC)" "0: No error occurred,1: A transfer error occurred due to an invalid.." line.long 0x8 "INT_ENABLE,IMSPI Interrupt Enable Register" bitfld.long 0x8 1. "INVALID_RESPONSE_LE,Assert an EEPROM interrupt when the INVALID_RESPONSE status is asserted. 1=Enable Interrupt; 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" newline bitfld.long 0x8 0. "TIMEOUT_LE,Assert an IMSPI interrupt when the TIMEOUT status is asserted. 1=Enable Interrupt; 0=Disable Interrupt" "0: Disable Interrupt,1: Enable Interrupt" line.long 0xC "TIMEOUT_CONTROL,IMSPI Timeout Control Register" hexmask.long.byte 0xC 0.--4. 1. "RESPONSE_TIMEOUT,This field is the maximum number of response cycles the IMSPI will wait until flagging a timeout. A setting of 0 will disable the timeout feature." tree.end endif sif (cpuis("CEC1702*")) tree "KSI (Keyboard Scan Interface)" base ad:0x40009C00 group.long 0x4++0x3 line.long 0x0 "KSO_SEL,KSO Select and control" bitfld.long 0x0 7. "INV,0= KSO[x] driven low when selected 1= KSO[x] driven high when selected." "0: KSO[x] driven low when selected,1: KSO[x] driven high when selected" bitfld.long 0x0 6. "KSEN,0= Keyboard scan enabled 1= Keyboard scan disabled. All KSO output buffers disabled." "0: Keyboard scan enabled,1: Keyboard scan disabled" bitfld.long 0x0 5. "ALL,0=When key scan is enabled KSO output controlled by the KSO_SELECT field.\n 1=KSO[x] driven high when selected." "0: When key scan is enabled,1: KSO[x] driven high when selected" hexmask.long.byte 0x0 0.--4. 1. "SEL,This field selects a KSO line (00000b = KSO[0] etc.) for output according to the value off KSO_INVERT in this register." rgroup.long 0x8++0x3 line.long 0x0 "KSI,[7:0] This field returns the current state of the KSI pins." group.long 0xC++0xB line.long 0x0 "KSI_STS,[7:0] Each bit in this field is set on the falling edge of the corresponding KSI input pin.\n A KSI interrupt is generated when its corresponding status bit and interrupt enable bit are both set. KSI interrupts are logically ORed together to.." line.long 0x4 "KSI_IEN,[7:0] Each bit in KSI_IEN enables interrupt generation due to highto-low transition on a KSI input.\n An interrupt is generated when the corresponding bits in KSI_STATUS and KSI_INT_EN are both set." line.long 0x8 "EXT_CTRL,[0:0] PREDRIVE_ENABLE enables the \n PREDRIVE mode to actively drive the KSO pins high for approximately 100ns before switching to open-drain operation.\n 0=Disable predrive on KSO pins\n 1=Enable predrive on KSO pins." tree.end endif tree "LED (Blinking-Breathing LED)" base ad:0x0 sif (cpuis("CEC1702*")||cpuis("CEC1712*")||cpuis("CEC1734?2HW*")) tree "LED0" base ad:0x4000B800 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode.\n 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RST Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing.\n Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,EN_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect.\n Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is.." "0,1" newline sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM:\n 3=Reserved\n 2=PWM is configured as a 6-bit PWM\n 1=PWM is configured as a 7-bit PWM\n 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM\n,2: PWM is configured as a 6-bit PWM\n,3: Reserved\n" bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" newline bitfld.long 0x0 0.--1. "CTRL,CTRL 3=PWM is always on\n 2=LED blinking (standard PWM)\n 1=LED breathing configuration\n 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration\n,2: LED blinking,3: PWM is always on\n" endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" newline endif bitfld.long 0x0 3. "SYNCH,SYNCH When this bit is '1' all counters for all LEDs are reset to their initial values.\n When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" endif line.long 0x4 "LIMIT,LED Limits This register may be written at any time.\n Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period.\n The two byte fields may be written.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds \n the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current.." hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds \n the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater\n than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal \n to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle \n is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed.\n When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the\n.." tree.end endif sif (cpuis("CEC1734?2ZW*")) tree "LED0" base ad:0x4000B800 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end endif sif (cpuis("CEC1736?2HW*")) tree "LED0" base ad:0x4000B800 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end endif sif (cpuis("CEC1736?2ZW*")) tree "LED0" base ad:0x4000B800 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")||cpuis("CEC1734?2HW*")) tree "LED1" base ad:0x4000B900 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode.\n 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RST Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing.\n Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,EN_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect.\n Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is.." "0,1" newline sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM:\n 3=Reserved\n 2=PWM is configured as a 6-bit PWM\n 1=PWM is configured as a 7-bit PWM\n 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM\n,2: PWM is configured as a 6-bit PWM\n,3: Reserved\n" bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" newline bitfld.long 0x0 0.--1. "CTRL,CTRL 3=PWM is always on\n 2=LED blinking (standard PWM)\n 1=LED breathing configuration\n 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration\n,2: LED blinking,3: PWM is always on\n" endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" newline endif bitfld.long 0x0 3. "SYNCH,SYNCH When this bit is '1' all counters for all LEDs are reset to their initial values.\n When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" endif line.long 0x4 "LIMIT,LED Limits This register may be written at any time.\n Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period.\n The two byte fields may be written.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds \n the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current.." hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds \n the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater\n than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal \n to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle \n is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed.\n When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the\n.." tree.end endif sif (cpuis("CEC1734?2ZW*")) tree "LED1" base ad:0x4000B900 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end endif sif (cpuis("CEC1736?2HW*")) tree "LED1" base ad:0x4000B900 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end endif sif (cpuis("CEC1736?2ZW*")) tree "LED1" base ad:0x4000B900 group.long 0x0++0x17 line.long 0x0 "CFG,LED Configuration" bitfld.long 0x0 16. "SYMMETRY,SYMMETRY 1=The rising and falling ramp times are in Asymmetric mode. 0=The rising and falling ramp times are in Symmetric mode." "0: The rising and falling ramp times are in..,1: The rising and falling ramp times are in.." hexmask.long.byte 0x0 8.--15. 1. "WDT_RELOAD,WDT_RELOAD The PWM Watchdog Timer counter reload value. On system reset it defaults to 14h which corresponds to a 4 second Watchdog timeout value." newline bitfld.long 0x0 7. "RST,RESET Writes of '1' to this bit resets the PWM registers to their default values. This bit is self clearing. Writes of '0' to this bit have no effect." "0,1" bitfld.long 0x0 6. "EN_UPDATE,ENABLE_UPDATE This bit is set to 1 when written with a '1'. Writes of '0' have no effect. Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the bit is readable.." "0,1" newline bitfld.long 0x0 4.--5. "PWM_SIZE,PWM_SIZE This bit controls the behavior of PWM: 3=Reserved 2=PWM is configured as a 6-bit PWM 1=PWM is configured as a 7-bit PWM 0=PWM is configured as an 8-bit PWM" "0: PWM is configured as an 8-bit PWM,1: PWM is configured as a 7-bit PWM,2: PWM is configured as a 6-bit PWM,3: Reserved" bitfld.long 0x0 3. "SYNCH,SYNCHRONIZE When this bit is '1' all counters for all LEDs are reset to their initial values. When this bit is '0' in the LED Configuration Register for all LEDs then all counters for LEDs that are configured to blink or breathe will increment.." "0,1" newline bitfld.long 0x0 2. "CLK_SRC,1=Clock source is the 48 MHz clock 0=Clock source is the 32.768 KHz clock" "0: Clock source is the 32,1: Clock source is the 48 MHz clock" bitfld.long 0x0 0.--1. "CTRL,CONTROL 3=PWM is always on 2=LED blinking (standard PWM) 1=LED breathing configuration 0=PWM is always off. All internal registers and counters are reset to 0. Clocks are gated" "0: PWM is always off,1: LED breathing configuration,2: LED blinking,3: PWM is always on" line.long 0x4 "LIMIT,LED Limits This register may be written at any time. Values written into the register are held in an holding register. which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads.." hexmask.long.byte 0x4 8.--15. 1. "MAX,In breathing mode when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field HD in register LED_DELAY then starts decrementing the current duty cycle" hexmask.long.byte 0x4 0.--7. 1. "MIN,In breathing mode when the current duty cycle is less than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field LD in register LED_DELAY then starts incrementing the current duty cycle In.." line.long 0x8 "DLY,LED Delay" hexmask.long.word 0x8 12.--23. 1. "HIGH_PULSE,In breathing mode the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MAX in register LED_LIMIT." hexmask.long.word 0x8 0.--11. 1. "LOW_PULSE,The number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than or equal to the value MIN in register LED_LIMIT." line.long 0xC "STEP,This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the.." hexmask.long.byte 0xC 28.--31. 1. "S7,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 111." hexmask.long.byte 0xC 24.--27. 1. "S6,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 110." newline hexmask.long.byte 0xC 20.--23. 1. "S5,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 101" hexmask.long.byte 0xC 16.--19. 1. "S4,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 100." newline hexmask.long.byte 0xC 12.--15. 1. "S3,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 011." hexmask.long.byte 0xC 8.--11. 1. "S2,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 010." newline hexmask.long.byte 0xC 4.--7. 1. "S1,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 001." hexmask.long.byte 0xC 0.--3. 1. "S0,Amount the current duty cycle is adjusted at the end of every PWM period when the segment index is equal to 000." line.long 0x10 "INTRVL,LED Update Interval" hexmask.long.byte 0x10 28.--31. 1. "I7,The number of PWM periods between updates to current duty cycle when the segment index is equal to 111b." hexmask.long.byte 0x10 24.--27. 1. "I6,The number of PWM periods between updates to current duty cycle when the segment index is equal to 110b." newline hexmask.long.byte 0x10 20.--23. 1. "I5,The number of PWM periods between updates to current duty cycle when the segment index is equal to 101b." hexmask.long.byte 0x10 16.--19. 1. "I4,The number of PWM periods between updates to current duty cycle when the segment index is equal to 100b." newline hexmask.long.byte 0x10 12.--15. 1. "I3,The number of PWM periods between updates to current duty cycle when the segment index is equal to 011b." hexmask.long.byte 0x10 8.--11. 1. "I2,The number of PWM periods between updates to current duty cycle when the segment index is equal to 010b." newline hexmask.long.byte 0x10 4.--7. 1. "I1,The number of PWM periods between updates to current duty cycle when the segment index is equal to 001b." hexmask.long.byte 0x10 0.--3. 1. "I0,The number of PWM periods between updates to current duty cycle when the segment index is equal to 000b." line.long 0x14 "OUTDLY,LED Output Delay" hexmask.long.byte 0x14 0.--7. 1. "DELAY,The delay in counts of the clock defined in Clock Source (CLKSRC) in which output transitions are delayed. When this field is 0 there is no added transition delay. When the LED is programmed to be Always On or Always Off the Output.." tree.end endif tree.end sif (cpuis("CEC1702*")) tree "MPU (Memory Protection Unit)" base ad:0xE000ED90 rgroup.long 0x0++0x3 line.long 0x0 "TYPE,MPU Type Register" hexmask.long.byte 0x0 16.--23. 1. "IREGION,Indicates the number of supported MPU data regions." hexmask.long.byte 0x0 8.--15. 1. "DREGION,Indicates the number of supported MPU instruction regions." bitfld.long 0x0 0. "SEPARATE,Indicates support for unified or separate instruction and date memory maps." "0,1" group.long 0x4++0xF line.long 0x0 "CTRL,MPU Control Register" bitfld.long 0x0 2. "PRIVDEFENA,Enables privileged software access to the default memory map." "0,1" bitfld.long 0x0 1. "HFNMIENA,Enables the operation of MPU during hard fault NMI and FAULTMASK handlers." "0,1" bitfld.long 0x0 0. "ENABLE,Enables the MPU" "0,1" line.long 0x4 "RNR,MPU Region Number Register" hexmask.long.byte 0x4 0.--7. 1. "REGION,Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers." line.long 0x8 "RBAR,MPU Region Base Address Register" hexmask.long 0x8 5.--31. 1. "ADDR,Region base address field." bitfld.long 0x8 4. "VALID,MPU Region Number valid bit." "0,1" hexmask.long.byte 0x8 0.--3. 1. "REGION,MPU region field." line.long 0xC "RASR,MPU Region Attribute and Size Register" bitfld.long 0xC 28. "XN,Instruction access disable bit." "0,1" bitfld.long 0xC 24.--26. "AP,Access permission field." "0,1,2,3,4,5,6,7" bitfld.long 0xC 19.--21. "TEX,MPU access permission attributes." "0,1,2,3,4,5,6,7" bitfld.long 0xC 18. "S,Shareable bit." "0,1" bitfld.long 0xC 17. "C,MPU access permission attributes." "0,1" bitfld.long 0xC 16. "B,MPU access permission attributes." "0,1" hexmask.long.byte 0xC 8.--15. 1. "SRD,Subregion disable bits." hexmask.long.byte 0xC 1.--5. 1. "SIZE,Specifies the size of the MPU protection region." newline bitfld.long 0xC 0. "ENABLE,Region enable bit." "0,1" tree.end endif tree "NVIC (Nested Vectored Interrupt Controller)" base ad:0xE000E100 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "ISER[$1],Interrupt Set Enable Register" hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt set enable bits" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x80)++0x3 line.long 0x0 "ICER[$1],Interrupt Clear Enable Register" hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt clear-enable bits" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x100)++0x3 line.long 0x0 "ISPR[$1],Interrupt Set Pending Register" hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt set-pending bits" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x180)++0x3 line.long 0x0 "ICPR[$1],Interrupt Clear Pending Register" hexmask.long 0x0 0.--31. 1. "CLRPEND,Interrupt clear-pending bits" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x200)++0x3 line.long 0x0 "IABR[$1],Interrupt Active Bit Register" hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt active bits" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x300)++0x0 line.byte 0x0 "IP[$1],Interrupt Priority Register n" bitfld.byte 0x0 0.--2. "PRI0,Priority of interrupt n" "0,1,2,3,4,5,6,7" repeat.end wgroup.long 0xE00++0x3 line.long 0x0 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID to trigger" tree.end sif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) tree "OTP (One Time Programmable)" base ad:0x40082000 group.byte 0x44++0x7 line.byte 0x0 "WR_LOCK0,This is the Write Lock Register." hexmask.byte 0x0 0.--7. 1. "WL0,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x1 "WR_LOCK1,This is the Write Lock Register." hexmask.byte 0x1 0.--7. 1. "WL1,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x2 "WR_LOCK2,This is the Write Lock Register." hexmask.byte 0x2 0.--7. 1. "WL2,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x3 "WR_LOCK3,This is the Write Lock Register." hexmask.byte 0x3 0.--7. 1. "WL3,When any of the bits are set the corresponding 32byte range in the OTP is not writable." line.byte 0x4 "RD_LOCK0,This is the Read Lock Register." hexmask.byte 0x4 0.--7. 1. "RL0,When any of the bits are set the corresponding 32byte range in the OTP is not readable." line.byte 0x5 "RD_LOCK1,This is the Read Lock Register." hexmask.byte 0x5 0.--7. 1. "RL1,When any of the bits are set the corresponding 32byte range in the OTP is not readable." line.byte 0x6 "RD_LOCK2,This is the Read Lock Register." hexmask.byte 0x6 0.--7. 1. "RL2,When any of the bits are set the corresponding 32byte range in the OTP is not readable." line.byte 0x7 "RD_LOCK3,This is the Read Lock Register." hexmask.byte 0x7 0.--7. 1. "RL3,When any of the bits are set the corresponding 32byte range in the OTP is not readable." group.long 0x4C++0x7 line.long 0x0 "WR_FINE_LCK,This is the Write Fine Lock Register." hexmask.long 0x0 0.--31. 1. "WR_FINE_LCK,Each bit locks write to a byte in the OTP range starting byte 320 to 351 0=Not Locked 1=Locked." line.long 0x4 "RD_FINE_LCK,This is the Read Fine Lock Register." hexmask.long 0x4 0.--31. 1. "RD_FINE_LCK,Each bit locks read to a byte in the OTP range starting byte 320 to 351 0=Not Locked 1=Locked." tree.end endif tree "PCR (Power Clocks and Resets)" base ad:0x40080100 sif (cpuis("CEC1702*")||cpuis("CEC1712*")) group.long 0x0++0x3 line.long 0x0 "SYS_SLP_CTRL,System Sleep Control" bitfld.long 0x0 3. "SLP_ALL,Initiates the System Sleep mode" "0,1" bitfld.long 0x0 2. "TEST,Test bit" "0,1" newline bitfld.long 0x0 0. "SLP_MOD,Selects the System Sleep mode" "0,1" group.long 0x14++0x3 line.long 0x0 "PWR_RST_CTRL,Power Reset Control Register" bitfld.long 0x0 8. "H_RST_SEL,Determines what generates the internal platform reset signal. 1=LRESET# pin; 0=eSPI PLTRST# VWire" "0: eSPI PLTRST# VWire,1: LRESET# pin" bitfld.long 0x0 0. "PWR_INV,Used by FW to control internal RESET_VCC signal function and external PWROK pin. This bit is read-only when VCC_PWRGD\n is de-asserted low." "0,1" group.long 0x38++0x3 line.long 0x0 "SLP_EN_2,Sleep Enable 2 Register" sif (cpuis("CEC1702*")) bitfld.long 0x0 18. "RTC_SLP_EN,RTC Sleep Enable" "0,1" bitfld.long 0x0 12. "GLBL_CFG_SLP_EN,GLBL_CFG" "0,1" newline endif bitfld.long 0x0 2. "UART1_SLP_EN,UART 1 Sleep Enable" "0,1" bitfld.long 0x0 1. "UART0_SLP_EN,UART 0 Sleep Enable" "0,1" group.long 0x50++0x13 line.long 0x0 "CLK_REQ_0,Clock Required 0 Register" sif (cpuis("CEC1702*")) bitfld.long 0x0 1. "EFUSE_CLK_REQ,eFuse Clock Reuqired" "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0x0 1. "OTP_CLK_REQ,OTP Enable" "0,1" newline endif bitfld.long 0x0 0. "JTAG_STAP_CLK_REQ,JTAG Clock Reuqired" "0,1" line.long 0x4 "CLK_REQ_1,Clock Required 1 Register" bitfld.long 0x4 31. "TMR16_1_CLK_REQ,TIMER16_1 Clock Reuqired" "0,1" bitfld.long 0x4 30. "TMR16_0_CLK_REQ,TIMER16_0 Clock Reuqired" "0,1" newline bitfld.long 0x4 29. "EC_REG_BANK_CLK_REQ,EC_REG_BANK Clock Reuqired" "0,1" sif (cpuis("CEC1712*")) bitfld.long 0x4 26. "PWM7_CLK_REQ,PWM7 Clock Required (PWM7_CLK_REQ)" "0,1" newline bitfld.long 0x4 25. "PWM6_CLK_REQ,PWM6 Clock Required (PWM6_CLK_REQ)" "0,1" endif sif (cpuis("CEC1702*")) bitfld.long 0x4 24. "PWM5_CLK_REQ,PWM5 Clock Reuqired" "0,1" newline bitfld.long 0x4 22. "PWM3_CLK_REQ,PWM3 Clock Reuqired" "0,1" bitfld.long 0x4 21. "PWM2_CLK_REQ,PWM2 Clock Reuqired" "0,1" newline bitfld.long 0x4 11. "TACH1_CLK_REQ,TACH1 Clock Reuqired" "0,1" bitfld.long 0x4 8. "PROCESSOR_CLK_REQ,PROCESSOR Clock Reuqired" "0,1" newline endif bitfld.long 0x4 23. "PWM4_CLK_REQ,PWM4 Clock Reuqired" "0,1" bitfld.long 0x4 20. "PWM1_CLK_REQ,PWM1 Clock Reuqired" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x4 12. "TACH2_CLK_REQ,TACH2 Clock Required (TACH2_CLK_REQ)" "0,1" endif bitfld.long 0x4 10. "SMB0_CLK_REQ,SMB0 Clock Reuqired" "0,1" newline bitfld.long 0x4 9. "WDT_CLK_REQ,WDT Clock Reuqired" "0,1" sif (cpuis("CEC1712*")) bitfld.long 0x4 8. "PROC_CLK_REQ,PROCESSOR Clock Required (PROCESSOR_CLK_REQ)" "0,1" newline endif bitfld.long 0x4 7. "TFDP_CLK_REQ,TFDP Clock Reuqired" "0,1" bitfld.long 0x4 6. "DMA_CLK_REQ,DMA Clock Reuqired" "0,1" newline bitfld.long 0x4 5. "PMC_CLK_REQ,PMC Clock Reuqired" "0,1" bitfld.long 0x4 4. "PWM0_CLK_REQ,PWM0 Clock Reuqired" "0,1" newline bitfld.long 0x4 2. "TACH0_CLK_REQ,TACH0 Clock Reuqired" "0,1" bitfld.long 0x4 0. "INT_CLK_REQ,Interrupt Clock Reuqired" "0,1" line.long 0x8 "CLK_REQ_2,Clock Required 2 Register" bitfld.long 0x8 18. "RTC_CLK_REQ,RTC Clock Reuqired" "0,1" bitfld.long 0x8 12. "GLBL_CFG_CLK_REQ,GLBL_CFG Clock Reuqired" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x8 2. "UART1_CLK_REQ,UART 1 Clock Required" "0,1" bitfld.long 0x8 1. "UART0_CLK_REQ,UART 0 Clock Required" "0,1" newline bitfld.long 0x8 0. "IMAP_CLK_REQ,IMAP Clock Required (IMAP_CLK_REQ)" "0,1" endif sif (cpuis("CEC1702*")) bitfld.long 0x8 2. "UART_1_CLK_REQ,UART 1 Clock Reuqired" "0,1" newline bitfld.long 0x8 1. "UART_0_CLK_REQ,UART 0 Clock Reuqired" "0,1" endif line.long 0xC "CLK_REQ_3,Clock Required 3 Register" sif (cpuis("CEC1702*")) bitfld.long 0xC 30. "CCTMR_CLK_REQ,Capture Compare Timer Clock Reuqired" "0,1" bitfld.long 0xC 29. "HTMR_1_CLK_REQ,HTIMER 1 Clock Reuqired" "0,1" newline bitfld.long 0xC 22. "TMR16_3_CLK_REQ,TIMER16_3 Clock Reuqired" "0,1" bitfld.long 0xC 21. "TMR16_2_CLK_REQ,TIMER16_2 Clock Reuqired" "0,1" newline bitfld.long 0xC 17. "LED1_CLK_REQ,LED1 Clock Reuqired" "0,1" bitfld.long 0xC 12. "RPMPWM_CLK_REQ,RPM-PWM Clock Reuqired" "0,1" newline bitfld.long 0xC 11. "KEYSCAN_CLK_REQ,KEYSCAN Clock Reuqired" "0,1" bitfld.long 0xC 10. "HTMR_0_CLK_REQ,HTIMER 0 Clock Reuqired" "0,1" newline bitfld.long 0xC 9. "GP_SPI0_CLK_REQ,GP SPI0 Clock Reuqired" "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0xC 30. "CCTIMER_CLK_REQ,Capture Compare Timer Clock Required (CCTIMER_CLK_REQ)" "0,1" newline bitfld.long 0xC 29. "HTM_1_CLK_REQ,Hibernation TIMER 1 Clock Required (HTM_1_CLK_REQ)" "0,1" bitfld.long 0xC 28. "AES_HASH_CLK_REQ,AES_HASH Clock Required" "0,1" newline bitfld.long 0xC 27. "RNG_CLK_REQ,RNG Clock Required" "0,1" bitfld.long 0xC 26. "PKE_CLK_REQ,PKE Clock Required" "0,1" newline endif bitfld.long 0xC 24. "TMR32_1_CLK_REQ,TIMER32_1 Clock Reuqired" "0,1" bitfld.long 0xC 23. "TMR32_0_CLK_REQ,TIMER32_0 Clock Reuqired" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0xC 20. "SMB_4_CLK_REQ,SMB 4 Clock Required (SMB_4_CLK_REQ)" "0,1" endif bitfld.long 0xC 16. "LED0_CLK_REQ,LED0 Clock Reuqired" "0,1" newline bitfld.long 0xC 15. "SMB3_CLK_REQ,SMB3 Clock Reuqired" "0,1" bitfld.long 0xC 14. "SMB2_CLK_REQ,SMB2 Clock Reuqired" "0,1" newline bitfld.long 0xC 13. "SMB1_CLK_REQ,SMB1 Clock Reuqired" "0,1" sif (cpuis("CEC1712*")) bitfld.long 0xC 10. "HTM0_CLK_REQ,Hibernation TIMER 0 Clock Required (HTM_0_CLK_REQ)" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0xC 5. "PS2_0_CLK_REQ,PS2_0 Clock Required (PS2_0_CLK_REQ)" "0,1" endif bitfld.long 0xC 3. "ADC_CLK_REQ,ADC Clock Reuqired" "0,1" line.long 0x10 "CLK_REQ_4,Clock Required 4 Register" sif (cpuis("CEC1702*")) bitfld.long 0x10 15. "FUJICL_CLK_REQ,Fujitsu Custom Logic Clock Reuqired" "0,1" bitfld.long 0x10 13. "PROCHOT_CLK_REQ,PROCHOT Clock Reuqired" "0,1" newline bitfld.long 0x10 12. "RC_ID2_CLK_REQ,RC_ID2 Clock Reuqired" "0,1" bitfld.long 0x10 11. "RC_ID1_CLK_REQ,RC_ID1 Clock Reuqired" "0,1" newline bitfld.long 0x10 8. "QSPI_CLK_REQ,Quad SPI Clock Reuqired" "0,1" bitfld.long 0x10 7. "RPMPWM1_CLK_REQ,RPMPWM 1 Clock Reuqired" "0,1" newline bitfld.long 0x10 5. "CNT_TMER3_CLK_REQ,CNT_TMER3 Clock Reuqired" "0,1" bitfld.long 0x10 4. "CNT_TMER2_CLK_REQ,CNT_TMER2 Clock Reuqired" "0,1" newline bitfld.long 0x10 3. "CNT_TMER1_CLK_REQ,CNT_TMER1 Clock Reuqired" "0,1" bitfld.long 0x10 2. "CNT_TMER0_CLK_REQ,CNT_TMER0 Clock Reuqired" "0,1" newline bitfld.long 0x10 0. "PWM10_CLK_REQ,PWM10 Clock Reuqired" "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0x10 8. "QMSPI_CLK_REQ,Quad Master SPI Clock Required" "0,1" newline endif bitfld.long 0x10 6. "RTOS_CLK_REQ,PWM6 Clock Reuqired" "0,1" group.long 0x78++0x3 line.long 0x0 "RST_EN_2,Reset Enable 2 Register" sif (cpuis("CEC1712*")) bitfld.long 0x0 26. "PORT_80_1_RST_EN,Port 80 1 Reset Enable" "0,1" bitfld.long 0x0 25. "PORT_80_0_RST_EN,Port 80 0 Reset Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 22. "ACPI_EC_3_RST_EN,ACPI EC 3 Reset Enable (ACPI_EC_3_RST_EN)" "0,1" bitfld.long 0x0 21. "ACPI_EC_2_RST_EN,ACPI EC 2 Reset Enable (ACPI_EC_2_RST_EN)" "0,1" newline bitfld.long 0x0 20. "SCRATCH_32_RST_EN,SCRATCH 32 Reset Enable" "0,1" endif bitfld.long 0x0 18. "RTC_RST_EN,RTC Reset Enable" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x0 17. "MBX_RST_EN,Mailbox Reset Enable (MBX_RST_EN)" "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0x0 15. "ACPI_PM1_RST_EN,ACPI PM1 Reset Enable (ACPI_PM1_RST_EN)" "0,1" newline bitfld.long 0x0 14. "ACPI_EC1_RST_EN,ACPI EC 1 Reset Enable (ACPI_EC_1_RST_EN)" "0,1" bitfld.long 0x0 13. "ACPI_EC0_RST_EN,ACPI EC 0 Reset Enable (ACPI_EC_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1702*")) bitfld.long 0x0 12. "GLBL_CFG_RST_EN,GLBL_CFG Reset Enable" "0,1" bitfld.long 0x0 2. "UART_1_RST_EN,UART 1 Reset Enable" "0,1" newline bitfld.long 0x0 1. "UART_0_RST_EN,UART 0 Reset Enable" "0,1" endif sif (cpuis("CEC1712*")) bitfld.long 0x0 2. "UART1_RST_EN,UART 1 Reset Enable" "0,1" newline bitfld.long 0x0 1. "UART0_RST_EN,UART 0 Reset Enable" "0,1" bitfld.long 0x0 0. "IMAP_RST_EN,IMAP Reset Enable (IMAP_RST_EN)" "0,1" endif endif group.long 0x4++0xF line.long 0x0 "PROC_CLK_CTRL,Processor Clock Control Register [7:0] Processor Clock Divide Value (PROC_DIV)\n 1: divide 48 MHz Ring Oscillator by 1.\n 3: divide 48 MHz Ring Oscillator by 3.\n 4: divide.." sif (cpuis("CEC1702*")) hexmask.long.byte 0x0 0.--7. 1. "DIV,Selects the EC clock rate" newline endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x0 0.--7. 1. "DIV,Selects the EC clock rate" newline endif sif (cpuis("CEC1734?2HW*")) hexmask.long.byte 0x0 0.--7. 1. "DIV,Selects the EC clock rate" newline endif sif (cpuis("CEC1734?2ZW*")) hexmask.long.byte 0x0 0.--7. 1. "DIV,Selects the EC clock rate" newline endif sif (cpuis("CEC1736?2HW*")) hexmask.long.byte 0x0 0.--7. 1. "DIV,Selects the EC clock rate" newline endif sif (cpuis("CEC1736?2ZW*")) hexmask.long.byte 0x0 0.--7. 1. "DIV,Selects the EC clock rate" endif line.long 0x4 "SLOW_CLK_CTRL,Configures the EC_CLK clock domain" hexmask.long.word 0x4 0.--9. 1. "DIV,DIV. n=Divide by n; 0=Clock off" line.long 0x8 "OSC_ID,Oscillator ID Register" bitfld.long 0x8 8. "PLL_LOCK,PLL Lock Status" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "TEST,Test bits" line.long 0xC "PWR_RST_STS,PCR Power Reset Status Register" sif (cpuis("CEC1702*")) bitfld.long 0xC 12. "ESPI_CLK_ACTIVE,ESPI_CLK_ACTIVE" "0,1" newline bitfld.long 0xC 10. "_32K_ACTIVE,32K_ACTIVE" "0,1" newline bitfld.long 0xC 6. "RST_VTR_STS,Indicates the status of VTR_RESET.(R/WC)\n 0 = No reset occurred since the last time this bit was cleared.\n 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline endif bitfld.long 0xC 11. "PCICLK_ACTIVE,PCICLK_ACTIVE" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0xC 10. "ACTIVE_32K,ACTIVE_32K (32K_ACTIVE)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0xC 10. "ACTIVE_32K,32K ACTIVE (ACTIVE_32K)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0xC 10. "ACTIVE_32K,32K ACTIVE (ACTIVE_32K)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0xC 10. "ACTIVE_32K,32K ACTIVE (ACTIVE_32K)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0xC 10. "ACTIVE_32K,32K ACTIVE (ACTIVE_32K)" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0xC 8. "WDT_EVENT,Indicates that a WDT_EVENT happened. (R/W1C)\n 0 = Not active.\n 1 = A WDT_EVENT occured." "0: Not active,1: A WDT_EVENT occured" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0xC 8. "WDT_EVENT,Indicates that a WDT_EVENT happened. (R/W1C) 0 = Not active. 1 = A WDT_EVENT occured." "0: Not active,1: A WDT_EVENT occured" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0xC 8. "WDT_EVENT,Indicates that a WDT_EVENT happened. (R/W1C) 0 = Not active. 1 = A WDT_EVENT occured." "0: Not active,1: A WDT_EVENT occured" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0xC 8. "WDT_EVENT,Indicates that a WDT_EVENT happened. (R/W1C) 0 = Not active. 1 = A WDT_EVENT occured." "0: Not active,1: A WDT_EVENT occured" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0xC 8. "WDT_EVENT,Indicates that a WDT_EVENT happened. (R/W1C) 0 = Not active. 1 = A WDT_EVENT occured." "0: Not active,1: A WDT_EVENT occured" newline endif bitfld.long 0xC 7. "JTAG_RST_STS,Indicates s RESET_SYS was triggered by a JTAG action.(R/WC)\n 0 = No JTAG reset occurred since the last time this bit was cleared.\n 1 = A reset occurred because of a JATAG command." "0: No JTAG reset occurred since the last time this..,1: A reset occurred because of a JATAG command" newline sif (cpuis("CEC1712*")) bitfld.long 0xC 6. "RST_SYS_STS,Indicates the status of RESET_SYS.(R/W1C)\n 0 = No reset occurred since the last time this bit was cleared.\n 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0xC 6. "RST_SYS_STS,Indicates the status of RESET_SYS.(R/W1C) 0 = No reset occurred since the last time this bit was cleared. 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0xC 6. "RST_SYS_STS,Indicates the status of RESET_SYS.(R/W1C) 0 = No reset occurred since the last time this bit was cleared. 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0xC 6. "RST_SYS_STS,Indicates the status of RESET_SYS.(R/W1C) 0 = No reset occurred since the last time this bit was cleared. 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0xC 6. "RST_SYS_STS,Indicates the status of RESET_SYS.(R/W1C) 0 = No reset occurred since the last time this bit was cleared. 1 = A reset occurred." "0: No reset occurred since the last time this bit..,1: A reset occurred" newline endif bitfld.long 0xC 5. "VBAT_RST_STS,VBAT reset status 0 = No reset occurred while VTR was off or since the last time this bit was cleared. 1 = A reset occurred.(R/WC)" "0: No reset occurred while VTR was off or since the..,1: A reset occurred" newline sif (cpuis("CEC1712*")) bitfld.long 0xC 4. "RST_VTR_STS,Indicates the status of RESET_VTR. 0 = reset active. 1 = reset not active.(R/W1C)" "0: reset active,1: reset not active" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0xC 4. "RST_VTR_STS,Indicates the status of RESET_VTR. 0 = reset active. 1 = reset not active.(R/W1C)" "0: reset active,1: reset not active" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0xC 4. "RST_VTR_STS,Indicates the status of RESET_VTR. 0 = reset active. 1 = reset not active.(R/W1C)" "0: reset active,1: reset not active" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0xC 4. "RST_VTR_STS,Indicates the status of RESET_VTR. 0 = reset active. 1 = reset not active.(R/W1C)" "0: reset active,1: reset not active" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0xC 4. "RST_VTR_STS,Indicates the status of RESET_VTR. 0 = reset active. 1 = reset not active.(R/W1C)" "0: reset active,1: reset not active" newline endif bitfld.long 0xC 3. "RST_H_STS,Indicates the status of RESET_VCC. 0 = reset active. 1 = reset not active." "0: reset active,1: reset not active" newline bitfld.long 0xC 2. "VCC_PWRGD_STS,Indicates the status of VCC_PWRGD. 0 = PWRGD not asserted. 1 = PWRGD asserte." "0: PWRGD not asserted,1: PWRGD asserte" group.long 0x18++0x3 line.long 0x0 "SYS_RST,System Reset Register" bitfld.long 0x0 8. "SOFT_SYS_RST,A write of a 1 forces an assertion of the RESET_SYS reset signal resetting the device. A write of 0 has no effect." "0,1" sif (cpuis("CEC1734?2HW*")) group.long 0x24++0x3 line.long 0x0 "PRIV_EN_LOCK,Peripheral Privilege Register" bitfld.long 0x0 0. "LOCK_EN,Peripheral Privilege Lock Register. 1=Locked 0=Unlocked. Locks Itself and CHIP_PRIV_EN EC_PRIV_EN EC_PRIV_EN2 EC_PRIV_EN3 HOST_PRIV_EN registers" "0: Unlocked,1: Locked" endif sif (cpuis("CEC1734?2ZW*")) group.long 0x24++0x3 line.long 0x0 "PRIV_EN_LOCK,Peripheral Privilege Register" bitfld.long 0x0 0. "LOCK_EN,Peripheral Privilege Lock Register. 1=Locked 0=Unlocked. Locks Itself and CHIP_PRIV_EN EC_PRIV_EN EC_PRIV_EN2 EC_PRIV_EN3 HOST_PRIV_EN registers" "0: Unlocked,1: Locked" group.long 0x84++0x3 line.long 0x0 "PERIPH_RST_EN_LOCK,Peripheral Reset Lock Register" hexmask.long 0x0 0.--31. 1. "EN,PCR Reset Enable Lock Register." group.long 0xF0++0xB line.long 0x0 "EC_PRIV_EN0,EC Priviliges 0 Register" bitfld.long 0x0 7. "PCR,PCR Privilege Enable." "0,1" bitfld.long 0x0 6. "GPIO,GPIO Privilege Enable." "0,1" newline bitfld.long 0x0 5. "TST_SPI,Test SPI Privilege Enable." "0,1" bitfld.long 0x0 4. "HOST_REG,Host Register Bank Privilege Enable." "0,1" newline bitfld.long 0x0 1. "OTP,OTP Privilege Enable." "0,1" line.long 0x4 "EC_PRIV_EN1,EC Priviliges 1 Register" bitfld.long 0x4 31. "BASIC_TMR1,Basic Timer 1 Privilege Enable." "0,1" bitfld.long 0x4 30. "BASIC_TMR0,Basic Timer 0 Privilege Enable." "0,1" newline bitfld.long 0x4 29. "EC_REGS,EC Registers Privilege Enable." "0,1" bitfld.long 0x4 10. "SMB_I2C0,SMB I2C 0 Privilege Enable." "0,1" newline bitfld.long 0x4 9. "WDT,WDT Privilege Enable." "0,1" bitfld.long 0x4 7. "TFDP,TFDP Privilege Enable." "0,1" newline bitfld.long 0x4 6. "DMA,DMA Privilege Enable." "0,1" bitfld.long 0x4 5. "PMC,PMC Privilege Enable." "0,1" newline bitfld.long 0x4 4. "PWM0,PWM 0 Privilege Enable." "0,1" bitfld.long 0x4 0. "INTR,Interrupt Privilege Enable." "0,1" line.long 0x8 "EC_PRIV_EN3,EC Priviliges 3 Register" bitfld.long 0x8 30. "CCT0,Capture Compare Timer Privilege Enable." "0,1" bitfld.long 0x8 29. "HIB_TIM1,Hibernation Timer 1 Privilege Enable." "0,1" newline bitfld.long 0x8 26. "CRYPTO,Crypto Privilege Enable." "0,1" bitfld.long 0x8 20. "SMB_I2C4,SMB I2C 4 Privilege Enable." "0,1" newline bitfld.long 0x8 17. "LED1,LED 1 Privilege Enable." "0,1" bitfld.long 0x8 16. "LED0,LED 0 Privilege Enable." "0,1" newline bitfld.long 0x8 15. "SMB_I2C3,SMB I2C 3 Privilege Enable." "0,1" bitfld.long 0x8 14. "SMB_I2C2,SMB I2C 2 Privilege Enable." "0,1" newline bitfld.long 0x8 13. "SMB_I2C1,SMB I2C 1 Privilege Enable." "0,1" bitfld.long 0x8 10. "HIB_TIM0,Hibernation TIMER 0 Privilege Enable." "0,1" endif sif (cpuis("CEC1736?2HW*")) group.long 0x24++0x3 line.long 0x0 "PRIV_EN_LOCK,Peripheral Privilege Register" bitfld.long 0x0 0. "LOCK_EN,Peripheral Privilege Lock Register. 1=Locked 0=Unlocked. Locks Itself and CHIP_PRIV_EN EC_PRIV_EN EC_PRIV_EN2 EC_PRIV_EN3 HOST_PRIV_EN registers" "0: Unlocked,1: Locked" group.long 0x84++0x3 line.long 0x0 "PERIPH_RST_EN_LOCK,Peripheral Reset Lock Register" hexmask.long 0x0 0.--31. 1. "EN,PCR Reset Enable Lock Register." group.long 0xF0++0xB line.long 0x0 "EC_PRIV_EN0,EC Priviliges 0 Register" bitfld.long 0x0 7. "PCR,PCR Privilege Enable." "0,1" bitfld.long 0x0 6. "GPIO,GPIO Privilege Enable." "0,1" newline bitfld.long 0x0 5. "TST_SPI,Test SPI Privilege Enable." "0,1" bitfld.long 0x0 4. "HOST_REG,Host Register Bank Privilege Enable." "0,1" newline bitfld.long 0x0 1. "OTP,OTP Privilege Enable." "0,1" line.long 0x4 "EC_PRIV_EN1,EC Priviliges 1 Register" bitfld.long 0x4 31. "BASIC_TMR1,Basic Timer 1 Privilege Enable." "0,1" bitfld.long 0x4 30. "BASIC_TMR0,Basic Timer 0 Privilege Enable." "0,1" newline bitfld.long 0x4 29. "EC_REGS,EC Registers Privilege Enable." "0,1" bitfld.long 0x4 10. "SMB_I2C0,SMB I2C 0 Privilege Enable." "0,1" newline bitfld.long 0x4 9. "WDT,WDT Privilege Enable." "0,1" bitfld.long 0x4 7. "TFDP,TFDP Privilege Enable." "0,1" newline bitfld.long 0x4 6. "DMA,DMA Privilege Enable." "0,1" bitfld.long 0x4 5. "PMC,PMC Privilege Enable." "0,1" newline bitfld.long 0x4 4. "PWM0,PWM 0 Privilege Enable." "0,1" bitfld.long 0x4 0. "INTR,Interrupt Privilege Enable." "0,1" line.long 0x8 "EC_PRIV_EN3,EC Priviliges 3 Register" bitfld.long 0x8 30. "CCT0,Capture Compare Timer Privilege Enable." "0,1" bitfld.long 0x8 29. "HIB_TIM1,Hibernation Timer 1 Privilege Enable." "0,1" newline bitfld.long 0x8 26. "CRYPTO,Crypto Privilege Enable." "0,1" bitfld.long 0x8 20. "SMB_I2C4,SMB I2C 4 Privilege Enable." "0,1" newline bitfld.long 0x8 17. "LED1,LED 1 Privilege Enable." "0,1" bitfld.long 0x8 16. "LED0,LED 0 Privilege Enable." "0,1" newline bitfld.long 0x8 15. "SMB_I2C3,SMB I2C 3 Privilege Enable." "0,1" bitfld.long 0x8 14. "SMB_I2C2,SMB I2C 2 Privilege Enable." "0,1" newline bitfld.long 0x8 13. "SMB_I2C1,SMB I2C 1 Privilege Enable." "0,1" bitfld.long 0x8 10. "HIB_TIM0,Hibernation TIMER 0 Privilege Enable." "0,1" endif sif (cpuis("CEC1736?2ZW*")) group.long 0x24++0x3 line.long 0x0 "PRIV_EN_LOCK,Peripheral Privilege Register" bitfld.long 0x0 0. "LOCK_EN,Peripheral Privilege Lock Register. 1=Locked 0=Unlocked. Locks Itself and CHIP_PRIV_EN EC_PRIV_EN EC_PRIV_EN2 EC_PRIV_EN3 HOST_PRIV_EN registers" "0: Unlocked,1: Locked" group.long 0x84++0x3 line.long 0x0 "PERIPH_RST_EN_LOCK,Peripheral Reset Lock Register" hexmask.long 0x0 0.--31. 1. "EN,PCR Reset Enable Lock Register." group.long 0xF0++0xB line.long 0x0 "EC_PRIV_EN0,EC Priviliges 0 Register" bitfld.long 0x0 7. "PCR,PCR Privilege Enable." "0,1" bitfld.long 0x0 6. "GPIO,GPIO Privilege Enable." "0,1" newline bitfld.long 0x0 5. "TST_SPI,Test SPI Privilege Enable." "0,1" bitfld.long 0x0 4. "HOST_REG,Host Register Bank Privilege Enable." "0,1" newline bitfld.long 0x0 1. "OTP,OTP Privilege Enable." "0,1" line.long 0x4 "EC_PRIV_EN1,EC Priviliges 1 Register" bitfld.long 0x4 31. "BASIC_TMR1,Basic Timer 1 Privilege Enable." "0,1" bitfld.long 0x4 30. "BASIC_TMR0,Basic Timer 0 Privilege Enable." "0,1" newline bitfld.long 0x4 29. "EC_REGS,EC Registers Privilege Enable." "0,1" bitfld.long 0x4 10. "SMB_I2C0,SMB I2C 0 Privilege Enable." "0,1" newline bitfld.long 0x4 9. "WDT,WDT Privilege Enable." "0,1" bitfld.long 0x4 7. "TFDP,TFDP Privilege Enable." "0,1" newline bitfld.long 0x4 6. "DMA,DMA Privilege Enable." "0,1" bitfld.long 0x4 5. "PMC,PMC Privilege Enable." "0,1" newline bitfld.long 0x4 4. "PWM0,PWM 0 Privilege Enable." "0,1" bitfld.long 0x4 0. "INTR,Interrupt Privilege Enable." "0,1" line.long 0x8 "EC_PRIV_EN3,EC Priviliges 3 Register" bitfld.long 0x8 30. "CCT0,Capture Compare Timer Privilege Enable." "0,1" bitfld.long 0x8 29. "HIB_TIM1,Hibernation Timer 1 Privilege Enable." "0,1" newline bitfld.long 0x8 26. "CRYPTO,Crypto Privilege Enable." "0,1" bitfld.long 0x8 20. "SMB_I2C4,SMB I2C 4 Privilege Enable." "0,1" newline bitfld.long 0x8 17. "LED1,LED 1 Privilege Enable." "0,1" bitfld.long 0x8 16. "LED0,LED 0 Privilege Enable." "0,1" newline bitfld.long 0x8 15. "SMB_I2C3,SMB I2C 3 Privilege Enable." "0,1" bitfld.long 0x8 14. "SMB_I2C2,SMB I2C 2 Privilege Enable." "0,1" newline bitfld.long 0x8 13. "SMB_I2C1,SMB I2C 1 Privilege Enable." "0,1" bitfld.long 0x8 10. "HIB_TIM0,Hibernation TIMER 0 Privilege Enable." "0,1" endif group.long 0x30++0x7 line.long 0x0 "SLP_EN_0,Sleep Enable 0 Register" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 7. "PCR_SLP_EN,PCR Sleep Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_SLP_EN,GPIO Sleep Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_SLP_EN,Test SPI Sleep Enable" "0,1" newline bitfld.long 0x0 4. "HRBNK_SLP_EN,Host Register Bank Sleep Enable" "0,1" newline bitfld.long 0x0 3. "CHPTST_SLP_EN,Chip Test Sleep Enable" "0,1" newline bitfld.long 0x0 2. "IMSPI_SLP_EN,IMSPI Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 7. "PCR_SLP_EN,PCR Sleep Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_SLP_EN,GPIO Sleep Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_SLP_EN,Test SPI Sleep Enable" "0,1" newline bitfld.long 0x0 4. "HRBNK_SLP_EN,Host Register Bank Sleep Enable" "0,1" newline bitfld.long 0x0 3. "CHPTST_SLP_EN,Chip Test Sleep Enable" "0,1" newline bitfld.long 0x0 2. "IMSPI_SLP_EN,IMSPI Sleep Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 7. "PCR_SLP_EN,PCR Sleep Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_SLP_EN,GPIO Sleep Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_SLP_EN,Test SPI Sleep Enable" "0,1" newline bitfld.long 0x0 4. "HRBNK_SLP_EN,Host Register Bank Sleep Enable" "0,1" newline bitfld.long 0x0 3. "CHPTST_SLP_EN,Chip Test Sleep Enable" "0,1" newline bitfld.long 0x0 2. "IMSPI_SLP_EN,IMSPI Sleep Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 7. "PCR_SLP_EN,PCR Sleep Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_SLP_EN,GPIO Sleep Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_SLP_EN,Test SPI Sleep Enable" "0,1" newline bitfld.long 0x0 4. "HRBNK_SLP_EN,Host Register Bank Sleep Enable" "0,1" newline bitfld.long 0x0 3. "CHPTST_SLP_EN,Chip Test Sleep Enable" "0,1" newline bitfld.long 0x0 2. "IMSPI_SLP_EN,IMSPI Sleep Enable" "0,1" newline endif bitfld.long 0x0 1. "OTP_SLP_EN,eFuse Enable" "0,1" newline sif (cpuis("CEC1702*")) bitfld.long 0x0 0. "JTAG_STAP_SLP_EN,JTAG STAP Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 0. "STAP_SLP_EN,STAP Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 0. "STAP_SLP_EN,STAP Sleep Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 0. "STAP_SLP_EN,STAP Sleep Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 0. "STAP_SLP_EN,STAP Sleep Enable" "0,1" endif line.long 0x4 "SLP_EN_1,Sleep Enable 1 Register" sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x4 31. "TMR16_1_SLP_EN,TIMER16_1 Sleep Enable" "0,1" newline bitfld.long 0x4 30. "TMR16_0_SLP_EN,TIMER16_0 Sleep Enable" "0,1" newline bitfld.long 0x4 23. "PWM4_SLP_EN,PWM4 Sleep Enable" "0,1" newline bitfld.long 0x4 20. "PWM1_SLP_EN,PWM1 Sleep Enable" "0,1" newline bitfld.long 0x4 2. "TACH0_SLP_EN,TACH0 Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 31. "TMR32_1_SLP_EN,TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_SLP_EN,TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 31. "TMR32_1_SLP_EN,TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_SLP_EN,TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 31. "TMR32_1_SLP_EN,TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_SLP_EN,TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 31. "TMR32_1_SLP_EN,TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_SLP_EN,TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN)" "0,1" newline endif bitfld.long 0x4 29. "EC_REG_BANK_SLP_EN,EC_REG_BANK Sleep Enable" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x4 26. "PWM7_SLP_EN,PWM7 Sleep Enable (PWM7_SLP_EN)" "0,1" newline bitfld.long 0x4 25. "PWM6_SLP_EN,PWM6 Sleep Enable (PWM6_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1702*")) bitfld.long 0x4 24. "PWM5_SLP_EN,PWM5 Sleep Enable" "0,1" newline bitfld.long 0x4 22. "PWM3_SLP_EN,PWM3 Sleep Enable" "0,1" newline bitfld.long 0x4 21. "PWM2_SLP_EN,PWM2 Sleep Enable" "0,1" newline bitfld.long 0x4 11. "TACH1_SLP_EN,TACH1 Sleep Enable" "0,1" newline bitfld.long 0x4 9. "WDT_SLP_EN,WDT Sleep Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x4 12. "TACH2_SLP_EN,TACH2 Sleep Enable (TACH2_SLP_EN)" "0,1" newline endif bitfld.long 0x4 10. "SMB0_SLP_EN,SMB0 Sleep Enable" "0,1" newline sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 9. "WDT_SLP_EN,Watch Dog Sleep Enable (WDT_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 9. "WDT_SLP_EN,Watch Dog Sleep Enable (WDT_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 9. "WDT_SLP_EN,Watch Dog Sleep Enable (WDT_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 9. "WDT_SLP_EN,Watch Dog Sleep Enable (WDT_SLP_EN)" "0,1" newline endif bitfld.long 0x4 8. "PROC_SLP_EN,PROCESSOR Sleep Enable" "0,1" newline bitfld.long 0x4 7. "TFDP_SLP_EN,TFDP Sleep Enable" "0,1" newline bitfld.long 0x4 6. "DMA_SLP_EN,DMA Sleep Enable" "0,1" newline bitfld.long 0x4 5. "PMC_SLP_EN,PMC Sleep Enable" "0,1" newline bitfld.long 0x4 4. "PWM0_SLP_EN,PWM0 Sleep Enable" "0,1" newline bitfld.long 0x4 0. "INT_SLP_EN,Interrupt Sleep Enable" "0,1" group.long 0x3C++0x7 line.long 0x0 "SLP_EN_3,Sleep Enable 3 Register" sif (cpuis("CEC1702*")) bitfld.long 0x0 30. "CCTMR_SLP_EN,Capture Compare Timer Sleep Enable" "0,1" newline bitfld.long 0x0 29. "HTMR_1_SLP_EN,HTIMER 1 Sleep Enable" "0,1" newline bitfld.long 0x0 22. "TMR16_3_SLP_EN,TIMER16_3 Sleep Enable" "0,1" newline bitfld.long 0x0 21. "TMR16_2_SLP_EN,TIMER16_2_Sleep Enable" "0,1" newline bitfld.long 0x0 17. "LED1_SLP_EN,LED1 Sleep Enable" "0,1" newline bitfld.long 0x0 12. "RPMPWM_SLP_EN,RPM-PWM Sleep Enable" "0,1" newline bitfld.long 0x0 11. "KEYSCAN_SLP_EN,KEYSCAN Sleep Enable" "0,1" newline bitfld.long 0x0 10. "HTMR_0_SLP_EN,HTIMER 0 Sleep Enable" "0,1" newline bitfld.long 0x0 9. "GP_SPI0_SLP_EN,GP SPI0 Sleep Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 30. "CCT_SLP_EN,Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_SLP_EN,Hibernation TIMER 1 Sleep Enable (HTM_1_SLP_EN)" "0,1" newline bitfld.long 0x0 28. "AES_HASH_SLP_EN,AES_HASH Sleep Enable" "0,1" newline bitfld.long 0x0 27. "RNG_SLP_EN,RNG Sleep Enable" "0,1" newline bitfld.long 0x0 26. "PKE_SLP_EN,PKE Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 30. "CCT_SLP_EN,Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_SLP_EN,Hibernation TIMER 1 Sleep Enable (HTM_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 30. "CCT_SLP_EN,Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_SLP_EN,Hibernation TIMER 1 Sleep Enable (HTM_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 30. "CCT_SLP_EN,Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_SLP_EN,Hibernation TIMER 1 Sleep Enable (HTM_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 30. "CCT_SLP_EN,Capture Compare Timer Sleep Enable (CCTIMER_SLP_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_SLP_EN,Hibernation TIMER 1 Sleep Enable (HTM_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 26. "CRYPTO_SLP_EN,CRYPTO Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 26. "CRYPTO_SLP_EN,CRYPTO Sleep Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 26. "CRYPTO_SLP_EN,CRYPTO Sleep Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 26. "CRYPTO_SLP_EN,CRYPTO Sleep Enable" "0,1" newline endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x0 24. "TMR32_1_SLP_EN,TIMER32_1 Sleep Enable" "0,1" newline bitfld.long 0x0 23. "TMR32_0_SLP_EN,TIMER32_0 Sleep Enable" "0,1" newline bitfld.long 0x0 3. "ADC_SLP_EN,ADC Sleep Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 20. "SMB4_SLP_EN,SMB4 Sleep Enable (SMB4_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 20. "SMB4_SLP_EN,SMB4 Sleep Enable (SMB4_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 20. "SMB4_SLP_EN,SMB4 Sleep Enable (SMB4_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 20. "SMB4_SLP_EN,SMB4 Sleep Enable (SMB4_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 20. "SMB4_SLP_EN,SMB4 Sleep Enable (SMB4_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 17. "LED1_SLP_EN,LED1 Sleep Enable (LED1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 17. "LED1_SLP_EN,LED1 Sleep Enable (LED1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 17. "LED1_SLP_EN,LED1 Sleep Enable (LED1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 17. "LED1_SLP_EN,LED1 Sleep Enable (LED1_SLP_EN)" "0,1" newline endif bitfld.long 0x0 16. "LED0_SLP_EN,LED0 Sleep Enable" "0,1" newline bitfld.long 0x0 15. "SMB3_SLP_EN,SMB3 Sleep Enable" "0,1" newline bitfld.long 0x0 14. "SMB2_SLP_EN,SMB2 Sleep Enable" "0,1" newline bitfld.long 0x0 13. "SMB1_SLP_EN,SMB1 Sleep Enable" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x0 10. "HTM_0_SLP_EN,Hibernation Timer 0 Sleep Enable (HTM_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 10. "HTM_0_SLP_EN,Hibernation Timer 0 Sleep Enable (HTM_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 10. "HTM_0_SLP_EN,Hibernation Timer 0 Sleep Enable (HTM_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 10. "HTM_0_SLP_EN,Hibernation Timer 0 Sleep Enable (HTM_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 10. "HTM_0_SLP_EN,Hibernation Timer 0 Sleep Enable (HTM_0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 5. "PS2_0_SLP_EN,PS2_0 Sleep Enable (PS2_0_SLP_EN)" "0,1" endif line.long 0x4 "SLP_EN_4,Sleep Enable 4 Register" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 23. "VBAT_REG_SLP_EN,VBAT REG Sleep Enable (VBAT_REG_SLP_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_SLP_EN,QMSPI 1 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_SLP_EN,SPI Peropheral 1 Sleep Enable (SPIPER1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 23. "VBAT_REG_SLP_EN,VBAT REG Sleep Enable (VBAT_REG_SLP_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_SLP_EN,QMSPI 1 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_SLP_EN,SPI Peropheral 1 Sleep Enable (SPIPER1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 23. "VBAT_REG_SLP_EN,VBAT REG Sleep Enable (VBAT_REG_SLP_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_SLP_EN,QMSPI 1 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_SLP_EN,SPI Peropheral 1 Sleep Enable (SPIPER1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 23. "VBAT_REG_SLP_EN,VBAT REG Sleep Enable (VBAT_REG_SLP_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_SLP_EN,QMSPI 1 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_SLP_EN,SPI Peropheral 1 Sleep Enable (SPIPER1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 16. "SPIPER0_SLP_EN,SPI Peropheral 0 Sleep Enable (SPIPER0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 16. "SPIPER0_SLP_EN,SPI Peropheral 0 Sleep Enable (SPIPER0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 16. "SPIPER0_SLP_EN,SPI Peropheral 0 Sleep Enable (SPIPER0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 16. "SPIPER0_SLP_EN,SPI Peropheral 0 Sleep Enable (SPIPER0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1702*")) bitfld.long 0x4 15. "FUJICL_SLP_EN,Fujitsu Custom Logic Sleep Enable" "0,1" newline bitfld.long 0x4 13. "PROCHOT_SLP_EN,PROCHOT Sleep Enable" "0,1" newline bitfld.long 0x4 12. "RC_ID2_SLP_EN,RC_ID2 Sleep Enable" "0,1" newline bitfld.long 0x4 11. "RC_ID1_SLP_EN,RC_ID1 Sleep Enable" "0,1" newline bitfld.long 0x4 7. "RPMPWM1_SLP_EN,RPMPWM 1 Sleep Enable" "0,1" newline bitfld.long 0x4 6. "RTOS_SLP_EN,PWM6 Sleep Enable" "0,1" newline bitfld.long 0x4 5. "CNT_TMER3_SLP_EN,CNT_TMER3 Sleep Enable" "0,1" newline bitfld.long 0x4 4. "CNT_TMER2_SLP_EN,CNT_TMER2 Sleep Enable" "0,1" newline bitfld.long 0x4 3. "CNT_TMER1_SLP_EN,CNT_TMER1 Sleep Enable" "0,1" newline bitfld.long 0x4 2. "CNT_TMER0_SLP_EN,CNT_TMER0 Sleep Enable" "0,1" newline bitfld.long 0x4 0. "PWM10_SLP_EN,PWM10 Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 9. "UART0_SLP_EN,UART0 Sleep Enable (UART_1_SLP_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_SLP_EN,Quad Master SPI 0 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 9. "UART0_SLP_EN,UART0 Sleep Enable (UART_1_SLP_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_SLP_EN,Quad Master SPI 0 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 9. "UART0_SLP_EN,UART0 Sleep Enable (UART_1_SLP_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_SLP_EN,Quad Master SPI 0 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 9. "UART0_SLP_EN,UART0 Sleep Enable (UART_1_SLP_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_SLP_EN,Quad Master SPI 0 Sleep Enable (QMSPI_1_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x4 8. "QMSPI_SLP_EN,Quad SPI Sleep Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 6. "RTOS_SLP_EN,RTOS Sleep Enable (RTOS_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 6. "RTOS_SLP_EN,RTOS Sleep Enable (RTOS_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 6. "RTOS_SLP_EN,RTOS Sleep Enable (RTOS_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 6. "RTOS_SLP_EN,RTOS Sleep Enable (RTOS_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 1. "SECMON1_SLP_EN,SPI Monitor 1 Sleep Enable (SECMON1_SLP_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_SLP_EN,SPI Monitor 0 Sleep Enable (SECMON0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 1. "SECMON1_SLP_EN,SPI Monitor 1 Sleep Enable (SECMON1_SLP_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_SLP_EN,SPI Monitor 0 Sleep Enable (SECMON0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 1. "SECMON1_SLP_EN,SPI Monitor 1 Sleep Enable (SECMON1_SLP_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_SLP_EN,SPI Monitor 0 Sleep Enable (SECMON0_SLP_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 1. "SECMON1_SLP_EN,SPI Monitor 1 Sleep Enable (SECMON1_SLP_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_SLP_EN,SPI Monitor 0 Sleep Enable (SECMON0_SLP_EN)" "0,1" endif group.long 0x70++0x7 line.long 0x0 "RST_EN_0,Reset Enable 0 Register" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 7. "PCR_RST_EN,PCR Reset Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_RST_EN,GPIO Reset Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_RST_EN,Test SPI Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 7. "PCR_RST_EN,PCR Reset Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_RST_EN,GPIO Reset Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_RST_EN,Test SPI Reset Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 7. "PCR_RST_EN,PCR Reset Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_RST_EN,GPIO Reset Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_RST_EN,Test SPI Reset Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 7. "PCR_RST_EN,PCR Reset Enable" "0,1" newline bitfld.long 0x0 6. "GPIO_RST_EN,GPIO Reset Enable" "0,1" newline bitfld.long 0x0 5. "TSTSPI_RST_EN,Test SPI Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 3. "CHPTST_RST_EN,Chip Test Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 3. "CHPTST_RST_EN,Chip Test Reset Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 3. "CHPTST_RST_EN,Chip Test Reset Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 3. "CHPTST_RST_EN,Chip Test Reset Enable" "0,1" newline endif sif (cpuis("CEC1702*")) bitfld.long 0x0 1. "EFUSE_RST_EN,eFuse Reset Enable" "0,1" newline bitfld.long 0x0 0. "JTAG_STAP_RST_EN,JTAG STAP Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 1. "OTP_RST_EN,OTP Reset Enable" "0,1" newline bitfld.long 0x0 0. "JTAG_STAP_CLK_REQ,JTAG STAP Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 1. "OTP_RST_EN,OTP Reset Enable" "0,1" newline bitfld.long 0x0 0. "JTAG_STAP_CLK_REQ,JTAG STAP Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 1. "OTP_RST_EN,OTP Reset Enable" "0,1" newline bitfld.long 0x0 0. "JTAG_STAP_CLK_REQ,JTAG STAP Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 1. "OTP_RST_EN,OTP Reset Enable" "0,1" newline bitfld.long 0x0 0. "JTAG_STAP_CLK_REQ,JTAG STAP Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 1. "OTP_RST_EN,OTP Reset Enable" "0,1" endif line.long 0x4 "RST_EN_1,Reset Enable 1 Register" sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x4 31. "TMR16_1_RST_EN,TIMER16_1 Reset Enable" "0,1" newline bitfld.long 0x4 30. "TMR16_0_RST_EN,TIMER16_0 Reset Enable" "0,1" newline bitfld.long 0x4 23. "PWM4_RST_EN,PWM4 Reset Enable" "0,1" newline bitfld.long 0x4 20. "PWM1_RST_EN,PWM1 Reset Enable" "0,1" newline bitfld.long 0x4 2. "TACH0_RST_EN,TACH0 Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 31. "TMR32_1_RST_EN,TIMER32_1 Reset Enable (TIMER32_1_RST_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_RST_EN,TIMER32_0 Reset Enable (TIMER32_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 31. "TMR32_1_RST_EN,TIMER32_1 Reset Enable (TIMER32_1_RST_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_RST_EN,TIMER32_0 Reset Enable (TIMER32_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 31. "TMR32_1_RST_EN,TIMER32_1 Reset Enable (TIMER32_1_RST_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_RST_EN,TIMER32_0 Reset Enable (TIMER32_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 31. "TMR32_1_RST_EN,TIMER32_1 Reset Enable (TIMER32_1_RST_EN)" "0,1" newline bitfld.long 0x4 30. "TMR32_0_RST_EN,TIMER32_0 Reset Enable (TIMER32_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1702*")) bitfld.long 0x4 29. "EC_REG_BANK_RST_EN,EC_REG_BANK Reset Enable" "0,1" newline bitfld.long 0x4 24. "PWM5_RST_EN,PWM5 Reset Enable" "0,1" newline bitfld.long 0x4 22. "PWM3_RST_EN,PWM3 Reset Enable" "0,1" newline bitfld.long 0x4 21. "PWM2_RST_EN,PWM2 Reset Enable" "0,1" newline bitfld.long 0x4 11. "TACH1_RST_EN,TACH1 Reset Enable" "0,1" newline bitfld.long 0x4 8. "PROCESSOR_RST_EN,PROCESSOR Reset Enable" "0,1" newline bitfld.long 0x4 5. "PMC_RST_EN,PMC Reset Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x4 26. "PWM7_RST_EN,PWM7 Reset Enable (PWM7_RST_EN)" "0,1" newline bitfld.long 0x4 25. "PWM6_RST_EN,PWM6 Reset Enable (PWM6_RST_EN)" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x4 12. "TACH2_RST_EN,TACH2 Reset Enable (TACH2_RST_EN)" "0,1" newline endif bitfld.long 0x4 10. "SMB0_RST_EN,SMB0 Reset Enable" "0,1" newline bitfld.long 0x4 9. "WDT_RST_EN,WDT Reset Enable" "0,1" newline bitfld.long 0x4 7. "TFDP_RST_EN,TFDP Reset Enable" "0,1" newline bitfld.long 0x4 6. "DMA_RST_EN,DMA Reset Enable" "0,1" newline bitfld.long 0x4 4. "PWM0_RST_EN,PWM0 Reset Enable" "0,1" newline bitfld.long 0x4 0. "INT_RST_EN,Interrupt Reset Enable" "0,1" group.long 0x7C++0x7 line.long 0x0 "RST_EN_3,Reset Enable 3 Register" sif (cpuis("CEC1702*")) bitfld.long 0x0 30. "CCTMR_RST_EN,Capture Compare Timer Reset Enable" "0,1" newline bitfld.long 0x0 29. "HTMR_1_RST_EN,HTIMER 1 Reset Enable" "0,1" newline bitfld.long 0x0 22. "TMR16_3_RST_EN,TIMER16_3 Reset Enable" "0,1" newline bitfld.long 0x0 21. "TMR16_2_RST_EN,TIMER16_2 Reset Enable" "0,1" newline bitfld.long 0x0 17. "LED1_RST_EN,LED1 Reset Enable" "0,1" newline bitfld.long 0x0 12. "RPMPWM_RST_EN,RPM-PWM Reset Enable" "0,1" newline bitfld.long 0x0 11. "KEYSCAN_RST_EN,KEYSCAN Reset Enable" "0,1" newline bitfld.long 0x0 10. "HTMR_0_RST_EN,HTIMER 0 Reset Enable" "0,1" newline bitfld.long 0x0 9. "GP_SPI0_RST_EN,GP SPI0 Reset Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 30. "CCTIMER_RST_EN,Capture Compare Timer Reset Enable (CCTIMER_RST_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_RST_EN,Hibernation TIMER 1 Reset Enable (HTM_1_RST_EN)" "0,1" newline bitfld.long 0x0 28. "AES_HASH_RST_EN,AES_HASH Reset Enable" "0,1" newline bitfld.long 0x0 27. "RNG_RST_EN,RNG Reset Enable" "0,1" newline bitfld.long 0x0 26. "PKE_RST_EN,PKE Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 30. "CCTIMER_RST_EN,Capture Compare Timer Reset Enable (CCTIMER_RST_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_RST_EN,Hibernation TIMER 1 Reset Enable (HTM_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 30. "CCTIMER_RST_EN,Capture Compare Timer Reset Enable (CCTIMER_RST_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_RST_EN,Hibernation TIMER 1 Reset Enable (HTM_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 30. "CCTIMER_RST_EN,Capture Compare Timer Reset Enable (CCTIMER_RST_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_RST_EN,Hibernation TIMER 1 Reset Enable (HTM_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 30. "CCTIMER_RST_EN,Capture Compare Timer Reset Enable (CCTIMER_RST_EN)" "0,1" newline bitfld.long 0x0 29. "HTM_1_RST_EN,Hibernation TIMER 1 Reset Enable (HTM_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 26. "CRYPTO_RST_EN,CRYPTO Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 26. "CRYPTO_RST_EN,CRYPTO Reset Enable" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 26. "CRYPTO_RST_EN,CRYPTO Reset Enable" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 26. "CRYPTO_RST_EN,CRYPTO Reset Enable" "0,1" newline endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.long 0x0 24. "TMR32_1_RST_EN,TIMER32_1 Reset Enable" "0,1" newline bitfld.long 0x0 23. "TMR32_0_RST_EN,TIMER32_0 Reset Enable" "0,1" newline bitfld.long 0x0 3. "ADC_RST_EN,ADC Reset Enable" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 20. "SMB_4_RST_EN,SMB 4 Reset Enable (SMB_4_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 20. "SMB_4_RST_EN,SMB 4 Reset Enable (SMB_4_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 20. "SMB_4_RST_EN,SMB 4 Reset Enable (SMB_4_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 20. "SMB_4_RST_EN,SMB 4 Reset Enable (SMB_4_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 20. "SMB_4_RST_EN,SMB 4 Reset Enable (SMB_4_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 17. "LED1_RST_EN,LED1 Reset Enable (LED1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 17. "LED1_RST_EN,LED1 Reset Enable (LED1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 17. "LED1_RST_EN,LED1 Reset Enable (LED1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 17. "LED1_RST_EN,LED1 Reset Enable (LED1_RST_EN)" "0,1" newline endif bitfld.long 0x0 16. "LED0_RST_EN,LED0 Reset Enable" "0,1" newline bitfld.long 0x0 15. "SMB3_RST_EN,SMB3 Reset Enable" "0,1" newline bitfld.long 0x0 14. "SMB2_RST_EN,SMB2 Reset Enable" "0,1" newline bitfld.long 0x0 13. "SMB1_RST_EN,SMB1 Reset Enable" "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x0 10. "HTM_0_RST_EN,Hibernation TIMER 0 Reset Enable (HTM_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 10. "HTM_0_RST_EN,Hibernation TIMER 0 Reset Enable (HTM_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 10. "HTM_0_RST_EN,Hibernation TIMER 0 Reset Enable (HTM_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 10. "HTM_0_RST_EN,Hibernation TIMER 0 Reset Enable (HTM_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 10. "HTM_0_RST_EN,Hibernation TIMER 0 Reset Enable (HTM_0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x0 5. "PS2_0_RST_EN,PS2_0 Reset Enable (PS2_0_RST_EN)" "0,1" endif line.long 0x4 "RST_EN_4,Reset Enable 4 Register" sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 23. "VBAT_REG_RST_EN,VBAT REG Reset Enable (VBAT_REG_RST_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_RST_EN,QMSPI 1 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_RST_EN,SPI Peropheral 1 Reset Enable (SPIPER1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 23. "VBAT_REG_RST_EN,VBAT REG Reset Enable (VBAT_REG_RST_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_RST_EN,QMSPI 1 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_RST_EN,SPI Peropheral 1 Reset Enable (SPIPER1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 23. "VBAT_REG_RST_EN,VBAT REG Reset Enable (VBAT_REG_RST_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_RST_EN,QMSPI 1 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_RST_EN,SPI Peropheral 1 Reset Enable (SPIPER1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 23. "VBAT_REG_RST_EN,VBAT REG Reset Enable (VBAT_REG_RST_EN)" "0,1" newline bitfld.long 0x4 22. "QMSPI_1_RST_EN,QMSPI 1 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline bitfld.long 0x4 21. "SPIPER1_RST_EN,SPI Peropheral 1 Reset Enable (SPIPER1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 16. "SPIPER0_RST_EN,SPI Peropheral 0 Reset Enable (SPIPER0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 16. "SPIPER0_RST_EN,SPI Peropheral 0 Reset Enable (SPIPER0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 16. "SPIPER0_RST_EN,SPI Peropheral 0 Reset Enable (SPIPER0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 16. "SPIPER0_RST_EN,SPI Peropheral 0 Reset Enable (SPIPER0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1702*")) bitfld.long 0x4 15. "FUJICL_RST_EN,Fujitsu Custom Logic Reset Enable" "0,1" newline bitfld.long 0x4 13. "PROCHOT_RST_EN,PROCHOT Reset Enable" "0,1" newline bitfld.long 0x4 12. "RC_ID2_RST_EN,RC_ID2 Reset Enable" "0,1" newline bitfld.long 0x4 11. "RC_ID1_RST_EN,RC_ID1 Reset Enable" "0,1" newline bitfld.long 0x4 8. "QSPI_RST_EN,Quad SPI Reset Enable" "0,1" newline bitfld.long 0x4 7. "RPMPWM1_RST_EN,RPMPWM 1 Reset Enable" "0,1" newline bitfld.long 0x4 5. "CNT_TMER3_RST_EN,CNT_TMER3 Reset Enable" "0,1" newline bitfld.long 0x4 4. "CNT_TMER2_RST_EN,CNT_TMER2 Reset Enable" "0,1" newline bitfld.long 0x4 3. "CNT_TMER1_RST_EN,CNT_TMER1 Reset Enable" "0,1" newline bitfld.long 0x4 2. "CNT_TMER0_RST_EN,CNT_TMER0 Reset Enable" "0,1" newline bitfld.long 0x4 0. "PWM10_RST_EN,PWM10 Reset Enable" "0,1" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 9. "UART0_RST_EN,UART0 Reset Enable (UART_0_RST_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_RST_EN,Quad Master SPI 0 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 9. "UART0_RST_EN,UART0 Reset Enable (UART_0_RST_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_RST_EN,Quad Master SPI 0 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 9. "UART0_RST_EN,UART0 Reset Enable (UART_0_RST_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_RST_EN,Quad Master SPI 0 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 9. "UART0_RST_EN,UART0 Reset Enable (UART_0_RST_EN)" "0,1" newline bitfld.long 0x4 8. "QMSPI0_RST_EN,Quad Master SPI 0 Reset Enable (QMSPI_1_RST_EN)" "0,1" newline endif sif (cpuis("CEC1712*")) bitfld.long 0x4 8. "QMSPI_RST_EN,Quad Master SPI Reset Enable" "0,1" newline endif bitfld.long 0x4 6. "RTOS_RST_EN,PWM6 Reset Enable" "0,1" newline sif (cpuis("CEC1734?2HW*")) bitfld.long 0x4 1. "SECMON1_RST_EN,SPI Monitor 1 Reset Enable (SECMON1_RST_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_RST_EN,SPI Monitor 0 Reset Enable (SECMON0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x4 1. "SECMON1_RST_EN,SPI Monitor 1 Reset Enable (SECMON1_RST_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_RST_EN,SPI Monitor 0 Reset Enable (SECMON0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x4 1. "SECMON1_RST_EN,SPI Monitor 1 Reset Enable (SECMON1_RST_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_RST_EN,SPI Monitor 0 Reset Enable (SECMON0_RST_EN)" "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x4 1. "SECMON1_RST_EN,SPI Monitor 1 Reset Enable (SECMON1_RST_EN)" "0,1" newline bitfld.long 0x4 0. "SECMON0_RST_EN,SPI Monitor 0 Reset Enable (SECMON0_RST_EN)" "0,1" endif sif (cpuis("CEC1712*")) group.long 0x84++0x3 line.long 0x0 "LOCK_REG,LOCK Register" hexmask.long 0x0 0.--31. 1. "PCR_RST_EN_LOCK,PCR Reset Enable Lock Register." endif sif (cpuis("CEC1734?2HW*")) group.long 0x84++0x3 line.long 0x0 "PERIPH_RST_EN_LOCK,Peripheral Reset Lock Register" hexmask.long 0x0 0.--31. 1. "EN,PCR Reset Enable Lock Register." group.long 0xF0++0xF line.long 0x0 "EC_PRIV_EN0,EC Priviliges 0 Register" bitfld.long 0x0 7. "PCR,PCR Privilege Enable." "0,1" bitfld.long 0x0 6. "GPIO,GPIO Privilege Enable." "0,1" newline bitfld.long 0x0 5. "TST_SPI,Test SPI Privilege Enable." "0,1" bitfld.long 0x0 4. "HOST_REG,Host Register Bank Privilege Enable." "0,1" newline bitfld.long 0x0 1. "OTP,OTP Privilege Enable." "0,1" line.long 0x4 "EC_PRIV_EN1,EC Priviliges 1 Register" bitfld.long 0x4 31. "BASIC_TMR1,Basic Timer 1 Privilege Enable." "0,1" bitfld.long 0x4 30. "BASIC_TMR0,Basic Timer 0 Privilege Enable." "0,1" newline bitfld.long 0x4 29. "EC_REGS,EC Registers Privilege Enable." "0,1" bitfld.long 0x4 10. "SMB_I2C0,SMB I2C 0 Privilege Enable." "0,1" newline bitfld.long 0x4 9. "WDT,WDT Privilege Enable." "0,1" bitfld.long 0x4 7. "TFDP,TFDP Privilege Enable." "0,1" newline bitfld.long 0x4 6. "DMA,DMA Privilege Enable." "0,1" bitfld.long 0x4 5. "PMC,PMC Privilege Enable." "0,1" newline bitfld.long 0x4 4. "PWM0,PWM 0 Privilege Enable." "0,1" bitfld.long 0x4 0. "INTR,Interrupt Privilege Enable." "0,1" line.long 0x8 "EC_PRIV_EN3,EC Priviliges 3 Register" bitfld.long 0x8 30. "CCT0,Capture Compare Timer Privilege Enable." "0,1" bitfld.long 0x8 29. "HIB_TIM1,Hibernation Timer 1 Privilege Enable." "0,1" newline bitfld.long 0x8 26. "CRYPTO,Crypto Privilege Enable." "0,1" bitfld.long 0x8 20. "SMB_I2C4,SMB I2C 4 Privilege Enable." "0,1" newline bitfld.long 0x8 17. "LED1,LED 1 Privilege Enable." "0,1" bitfld.long 0x8 16. "LED0,LED 0 Privilege Enable." "0,1" newline bitfld.long 0x8 15. "SMB_I2C3,SMB I2C 3 Privilege Enable." "0,1" bitfld.long 0x8 14. "SMB_I2C2,SMB I2C 2 Privilege Enable." "0,1" newline bitfld.long 0x8 13. "SMB_I2C1,SMB I2C 1 Privilege Enable." "0,1" bitfld.long 0x8 10. "HIB_TIM0,Hibernation TIMER 0 Privilege Enable." "0,1" line.long 0xC "EC_PRIV_EN4,EC Priviliges 4 Register" bitfld.long 0xC 23. "VBAT_REG,VBAT Register Privilege Enable." "0,1" bitfld.long 0xC 22. "QMSPI1,QMSPI 1 Privilege Enable." "0,1" newline bitfld.long 0xC 21. "SPISLV1,SPISLV 1 Privilege Enable." "0,1" bitfld.long 0xC 16. "SPISLV0,SPISLV 0 Privilege Enable." "0,1" newline bitfld.long 0xC 9. "UART0,UART 0 Privilege Enable." "0,1" bitfld.long 0xC 8. "QMSPI0,QMSPI 0 Privilege Enable." "0,1" newline bitfld.long 0xC 6. "RTOS_TIM,RTOS Timer Privilege Enable." "0,1" bitfld.long 0xC 1. "SPIMON1,SPI Monitor 1 Privilege Enable." "0,1" newline bitfld.long 0xC 0. "SPIMON0,SPI Monitor 0 Privilege Enable." "0,1" endif sif (cpuis("CEC1734?2ZW*")) group.long 0xFC++0x3 line.long 0x0 "EC_PRIV_EN4,EC Priviliges 4 Register" bitfld.long 0x0 23. "VBAT_REG,VBAT Register Privilege Enable." "0,1" bitfld.long 0x0 22. "QMSPI1,QMSPI 1 Privilege Enable." "0,1" newline bitfld.long 0x0 21. "SPISLV1,SPISLV 1 Privilege Enable." "0,1" bitfld.long 0x0 16. "SPISLV0,SPISLV 0 Privilege Enable." "0,1" newline bitfld.long 0x0 9. "UART0,UART 0 Privilege Enable." "0,1" bitfld.long 0x0 8. "QMSPI0,QMSPI 0 Privilege Enable." "0,1" newline bitfld.long 0x0 6. "RTOS_TIM,RTOS Timer Privilege Enable." "0,1" bitfld.long 0x0 1. "SPIMON1,SPI Monitor 1 Privilege Enable." "0,1" newline bitfld.long 0x0 0. "SPIMON0,SPI Monitor 0 Privilege Enable." "0,1" endif sif (cpuis("CEC1736?2HW*")) group.long 0xFC++0x3 line.long 0x0 "EC_PRIV_EN4,EC Priviliges 4 Register" bitfld.long 0x0 23. "VBAT_REG,VBAT Register Privilege Enable." "0,1" bitfld.long 0x0 22. "QMSPI1,QMSPI 1 Privilege Enable." "0,1" newline bitfld.long 0x0 21. "SPISLV1,SPISLV 1 Privilege Enable." "0,1" bitfld.long 0x0 16. "SPISLV0,SPISLV 0 Privilege Enable." "0,1" newline bitfld.long 0x0 9. "UART0,UART 0 Privilege Enable." "0,1" bitfld.long 0x0 8. "QMSPI0,QMSPI 0 Privilege Enable." "0,1" newline bitfld.long 0x0 6. "RTOS_TIM,RTOS Timer Privilege Enable." "0,1" bitfld.long 0x0 1. "SPIMON1,SPI Monitor 1 Privilege Enable." "0,1" newline bitfld.long 0x0 0. "SPIMON0,SPI Monitor 0 Privilege Enable." "0,1" endif sif (cpuis("CEC1736?2ZW*")) group.long 0xFC++0x3 line.long 0x0 "EC_PRIV_EN4,EC Priviliges 4 Register" bitfld.long 0x0 23. "VBAT_REG,VBAT Register Privilege Enable." "0,1" bitfld.long 0x0 22. "QMSPI1,QMSPI 1 Privilege Enable." "0,1" newline bitfld.long 0x0 21. "SPISLV1,SPISLV 1 Privilege Enable." "0,1" bitfld.long 0x0 16. "SPISLV0,SPISLV 0 Privilege Enable." "0,1" newline bitfld.long 0x0 9. "UART0,UART 0 Privilege Enable." "0,1" bitfld.long 0x0 8. "QMSPI0,QMSPI 0 Privilege Enable." "0,1" newline bitfld.long 0x0 6. "RTOS_TIM,RTOS Timer Privilege Enable." "0,1" bitfld.long 0x0 1. "SPIMON1,SPI Monitor 1 Privilege Enable." "0,1" newline bitfld.long 0x0 0. "SPIMON0,SPI Monitor 0 Privilege Enable." "0,1" endif tree.end tree "PWM (Pulse Width Modulator)" base ad:0x0 tree "PWM0" base ad:0x40005800 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end sif (cpuis("CEC1702*")) tree "PWM1" base ad:0x40005810 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM4" base ad:0x40005840 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM10" base ad:0x400058A0 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "PWM2" base ad:0x40005820 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM3" base ad:0x40005830 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM5" base ad:0x40005850 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal.\n Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the.." line.long 0x8 "CFG,PWMx CFGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_EN is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end endif sif (cpuis("CEC1712*")) tree "PWM6" base ad:0x40005860 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the PWM_OUTPUT is.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end tree "PWM7" base ad:0x40005870 group.long 0x0++0xB line.long 0x0 "CNT_ON,This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will\n cause the On time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero and the.." line.long 0x4 "CNT_OFF,This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will\n cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source.\n When this field is set to zero. the PWM_OUTPUT is.." line.long 0x8 "CFG,PWMx CONFIGURATION REGISTER" hexmask.long.byte 0x8 3.--6. 1. "CLK_PRE_DIV,The Clock source for the 16-bit down counter (see PWMx Counter ON Time Register and PWMx Counter OFF Time Register)\n is determined by bit D1 of this register. The Clock source is then divided by the value of Pre-Divider+1 and the.." bitfld.long 0x8 2. "INV,1= PWM_OUTPUT ON State is active low; 0=PWM_OUTPUT ON State is active high." "0: PWM_OUTPUT ON State is active high,1: PWM_OUTPUT ON State is active low" bitfld.long 0x8 1. "CLK_SEL,This bit determines the clock source used by the PWM duty cycle and frequency control logic.\n 1=CLOCK_LOW\n 0=CLOCK_HIGH" "0: CLOCK_HIGH,1: CLOCK_LOW\n" bitfld.long 0x8 0. "PWM_EN,When the PWM_ENABLE is set to 0 the internal counters are reset and the internal state machine is set to the OFF state.\n In addition the PWM_OUTPUT signal is set to the inactive state as determined by the Invert bit. The PWMx Counter ON Time.." "0: Disabled,1: Enabled" tree.end endif tree.end sif (cpuis("CEC1702*")) base ad:0x40005400 elif (cpuis("CEC1712*")) base ad:0x40070000 elif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) base ad:0x0 endif tree "QMSPI (Quad SPI Master Controller)" sif (cpuis("CEC1702*")||cpuis("CEC1712*")) group.long 0x0++0x27 line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--24. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255.\n A value of 0 divides the master clock by 256." bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register.\n e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register.\n e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 1. "SOFT_RST,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block.\n 1=Enabled. The block is fully operational\n 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANS_LEN_BITS.\n A value of 0 means an infinite length transfer." bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used.\n 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER\n 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments\n 2=TRANSFER_LENGTH defined in units of 4-byte segments\n 1=TRANSFER_LENGTH defined in units of bytes\n 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes\n,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI \n interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit.." "0: The transaction is not terminated,1: The transaction is terminated\n" bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface\n reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes\n,3: DMA is enabled and set to 4 Bytes\n" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface.\n 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer\n 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either\n the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes\n,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface.\n 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used.\n 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either \n TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0.\n 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs.\n Any data stored in the FIFOs is discarded and all count fields are reset.\n Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect.\n This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing.\n This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven\n 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven\n 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted\n 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted\n 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven\n 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven\n" bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven.\n 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven\n 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven\n" bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven.\n 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing\n 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing\n" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer)\n 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field.\n 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER\n.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty\n 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty\n" bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full\n 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full\n" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer)\n 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field.\n 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty\n 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty\n" bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full\n 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full\n" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected.\n 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer)\n 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer)\n 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller.\n This occurs either when the SPI controller has closed the DMA transfer or the DMA channel.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH.\n If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In Description.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted\n" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted\n 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave.\n Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO.\n Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word.." endif sif (cpuis("CEC1702*")) repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer Register" hexmask.long.word 0x0 16.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TX_LEN_BITS. \n A value of 0 means an infinite length transfer." hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. \n This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 11. "DESCR_BUF_LAST,If this bit is 1 then this is the last Description Buffer in the chain. When the transfer described by this buffer \n completes the TRANSFER_ COMPLETE status will be set to 1. If this bit is 0 then this is not the last buffer in.." "0,1" bitfld.long 0x0 10. "TRANS_LEN_BITS,1=TRANSFER_LENGTH defined in bits\n 0=TRANSFER_LENGTH defined in bytes" "0: TRANSFER_LENGTH defined in bytes,1: TRANSFER_LENGTH defined in bits\n" newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer.\n 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface.." "0: The transfer is not closed,1: The transfer is terminated" bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO \n until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request.\n The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes\n,3: DMA is enabled and set to 4 Bytes\n" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface.\n 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface\n reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes\n,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface.\n 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used\n 2=Transmit Enabled in 0 Mode. The MOSI or.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE \n or RX_TRANSFER_ENABLE must be 0.3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end endif sif (cpuis("CEC1712*")) group.long 0x28++0x3 line.long 0x0 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.word 0x0 23.--31. 1. "DLY_OFF_TO_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum \n pulse width of CS deassertion." hexmask.long.byte 0x0 16.--19. 1. "DLY_LAST_DAT_HLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD \n switching from input to output. This is only used if the WP/HOLD functions are in use and only on IO2/WP \n and.." newline hexmask.long.byte 0x0 8.--11. 1. "DLY_CLK_STOP_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS.\n" hexmask.long.byte 0x0 0.--3. 1. "DLY_CS_ON_CLK_STRT" endif sif (cpuis("CEC1712*")) repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 16.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 11. "DESCR_BUF_LAST,If this bit is 1 then this is the last Description Buffer in the chain. When the transfer described by this buffer completes the TRANSFER_COMPLETE status will be set to 1.\n If this bit is 0 then this is not the last buffer in use." "0,1" bitfld.long 0x0 10. "TRANS_LEN_BITS,1=TRANSFER_LENGTH defined in bits\n 0=TRANSFER_LENGTH defined in bytes" "0: TRANSFER_LENGTH defined in bytes,1: TRANSFER_LENGTH defined in bits\n" newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer.\n 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request.\n The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes\n,3: DMA is enabled and set to 4 Bytes\n" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface.\n 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface\n reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes\n,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface.\n 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used\n 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0.\n 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end endif sif (cpuis("CEC1734?2HW*")) tree "QMSPI0" base ad:0x40070000 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_CS_OFF_TO_CS_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DATA_HOLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_TO_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_TO_CLOCK_START,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070110 ad:0x40070120 ad:0x40070130) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070140 ad:0x40070150 ad:0x40070160) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end endif sif (cpuis("CEC1734?2ZW*")) tree "QMSPI0" base ad:0x40070000 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_CS_OFF_TO_CS_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DATA_HOLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_TO_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_TO_CLOCK_START,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070110 ad:0x40070120 ad:0x40070130) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070140 ad:0x40070150 ad:0x40070160) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end tree "QMSPI1" base ad:0x40070200 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_CS_OFF_TO_CS_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DATA_HOLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_TO_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_TO_CLOCK_START,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070310 ad:0x40070320 ad:0x40070330) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070340 ad:0x40070350 ad:0x40070360) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end endif sif (cpuis("CEC1736?2HW*")) tree "QMSPI0" base ad:0x40070000 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_CS_OFF_TO_CS_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DATA_HOLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_TO_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_TO_CLOCK_START,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070110 ad:0x40070120 ad:0x40070130) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070140 ad:0x40070150 ad:0x40070160) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end endif sif (cpuis("CEC1736?2ZW*")) tree "QMSPI0" base ad:0x40070000 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_CS_OFF_TO_CS_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DATA_HOLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_TO_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_TO_CLOCK_START,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070110 ad:0x40070120 ad:0x40070130) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070140 ad:0x40070150 ad:0x40070160) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end tree "QMSPI1" base ad:0x40070200 group.long 0x0++0x2B line.long 0x0 "MODE,QMSPI Mode Register" hexmask.long.word 0x0 16.--31. 1. "CLK_DIV,The SPI clock divide in number of system clocks. A value of 1 divides the master clock by 1 a value of 255 divides the master clock by 255. A value of 0 divides the master clock by 256." newline bitfld.long 0x0 12.--13. "CS,This defines which Chip Select will be used by the H/W when doing a transfer." "0,1,2,3" newline bitfld.long 0x0 10. "CHPA_MISO,Clock phase of the Master data in. Common SPI modes require this field to be programmed with the same value as CHPA_MOSI in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data are captured on the rising edge of the SPI..,1: Data are captured on the falling edge of the SPI.." newline bitfld.long 0x0 9. "CHPA_MOSI,Clock phase of the Master data out. Common SPI modes require this field to be programmed with the same value as CHPA_MISO in this register. e.g. Mode 0: CPOL=0; CHPA_MISO=0; CHPA_MOSI=0; Mode 3: CPOL=1; CHPA_MISO=1; CHPA_MOSI=1. See.." "0: Data changes on the falling edge of the SPI clock,1: Data changes on the rising edge of the SPI clock" newline bitfld.long 0x0 8. "CPOL,Polarity of the SPI clock line when there are no transactions in process. 1=SPI Clock starts High; 0=SPI Clock starts Low." "0: SPI Clock starts Low,1: SPI Clock starts High" newline bitfld.long 0x0 4. "LDMA_TXEN,This enables the Local DMA TX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 3. "LDMA_RXEN,This enables the Local DMA RX usage (instead of the Central DMA) when the Control register enables the DMA." "0,1" newline bitfld.long 0x0 2. "DMA_UNLGND_MOD,When enabled the DMA is allowed to operate w/ unaligned transfer lengths." "0,1" newline bitfld.long 0x0 1. "SOFT_RESET,Writing this bit with a 1 will reset the Quad SPI block. It is self-clearing." "0,1" newline bitfld.long 0x0 0. "ACT,This bit is used to activate the QMSPI block. 1=Enabled. The block is fully operational 0=Disabled. Clocks are gated to conserve power and the output signals are set to their inactive state." "0: Disabled,1: Enabled" line.long 0x4 "CTRL,QMSPI SPI Control" hexmask.long.word 0x4 17.--31. 1. "TRANS_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x4 16. "DESCR_BUFF_EN,This enables the Description Buffers to be used. 1=Description Buffers in use. The first buffer is defined in DESCRIPTION_BUFFER_POINTER 0=Description Buffers disabled." "0: Description Buffers disabled,1: Description Buffers in use" newline hexmask.long.byte 0x4 12.--15. 1. "DESCR_BUFF_PTR,This field selects the first buffer used if Description Buffers are enabled." newline bitfld.long 0x4 10.--11. "TRANS_UNITS,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits." "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x4 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. When the transaction closes the Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface terminates When Description Buffers are in use this bit must.." "0: The transaction is not terminated,1: The transaction is terminated" newline bitfld.long 0x4 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer 0=Receive is disabled" "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x4 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x4 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used. 2=Transmit Enabled in 0 Mode." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x4 0.--1. "TX_MODE,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" line.long 0x8 "EXE,QMSPI Execute Register" bitfld.long 0x8 2. "CLR_DAT_BUFF,Writing a 1 to this bit will clear out the Transmit and Receive FIFOs. Any data stored in the FIFOs is discarded and all count fields are reset. Writing a 0 to this bit has no effect. This bit is self clearing." "0,1" newline bitfld.long 0x8 1. "STOP,Writing a 1 to this bit will stop any transfer in progress at the next byte boundary. Writing a 0 to this bit has no effect. This bit is self clearing. This bit must not be set to 1 if the field START in this register is set to 1." "0,1" newline bitfld.long 0x8 0. "START,Writing a 1 to this bit will start the SPI transfer. Writing a 0 to this bit has no effect. This bit is self-clearing. This bit must not be set to 1 if the field STOP in this register is set to 1." "0,1" line.long 0xC "IFCTRL,QMSPI Interface Control Register" bitfld.long 0xC 7. "PU_ON_NOTDRIVEN,1=Enable pull-up resistors on Transmit pins while the pins are not driven 0=No pull-up resistors enabled ion Transmit pins." "0: No pull-up resistors enabled ion Transmit pins,1: Enable pull-up resistors on Transmit pins while.." newline bitfld.long 0xC 6. "PD_ON_NOTDRIVEN,1=Enable pull-down resistors on Transmit pins while the pins are not driven 0=No pull-down resistors enabled ion Transmit pins." "0: No pull-down resistors enabled ion Transmit pins,1: Enable pull-down resistors on Transmit pins.." newline bitfld.long 0xC 5. "PU_ON_NOTSEL,1=Enable pull-up resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-up resistors enabled on Receive pins." "0: No pull-up resistors enabled on Receive pins,1: Enable pull-up resistors on Receive pins while.." newline bitfld.long 0xC 4. "PD_ON_NOT_SEL,1=Enable pull-down resistors on Receive pins while the SPI Chip Select signal is not asserted 0=No pull-down resistors enabled on Receive pins" "0: No pull-down resistors enabled on Receive pins,1: Enable pull-down resistors on Receive pins while.." newline bitfld.long 0xC 3. "HLD_OUT_EN,1=HOLD SPI Output Port is driven 0=HOLD SPI Output Port is not driven." "0: HOLD SPI Output Port is not driven,1: HOLD SPI Output Port is driven" newline bitfld.long 0xC 2. "HLD_OUT_VAL,This bit sets the value on the HOLD SPI Output Port if it is driven. 1=HOLD is driven to 1; 0=HOLD is driven to 0." "0: HOLD is driven to 0,1: HOLD is driven to 1" newline bitfld.long 0xC 1. "WR_PRCT_OUT_EN,1=WRITE PROTECT SPI Output Port is driven 0=WRITE PROTECT SPI Output Port is not driven" "0: WRITE PROTECT SPI Output Port is not driven,1: WRITE PROTECT SPI Output Port is driven" newline bitfld.long 0xC 0. "WR_PRCT_OUT_VAL,This bit sets the value on the WRITE PROTECT SPI Output Port if it is driven. 1=WRITE PROTECT is driven to 1; 0=WRITE PROTECT is driven to 0" "0: WRITE PROTECT is driven to 0,1: WRITE PROTECT is driven to 1" line.long 0x10 "STS,QMSPI Status Register" hexmask.long.byte 0x10 24.--27. 1. "CUR_DESCR_BUF,This field shows the Description Buffer currently active. This field has no meaning if Description Buffers are not enabled." newline bitfld.long 0x10 16. "TRANS_ACTIV,1=A transfer is currently executing 0=No transfer currently in progress." "0: No transfer currently in progress,1: A transfer is currently executing" newline bitfld.long 0x10 15. "RX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to write to a full Receive Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 14. "RX_BUFF_REQ,This status is asserted if the Receive Buffer reaches a high water mark established by the RECEIVE_BUFFER_TRIGGER field. 1=RECEIVE_BUFFER_COUNT is greater than or equal to RECEIVE_BUFFER_TRIGGER.." "0: RECEIVE_BUFFER_COUNT is less than..,1: RECEIVE_BUFFER_COUNT is greater than or equal to.." newline bitfld.long 0x10 13. "RX_BUFF_EMP,1=The Receive Buffer is empty 0=The Receive Buffer is not empty." "0: The Receive Buffer is not empty,1: The Receive Buffer is empty" newline bitfld.long 0x10 12. "RX_BUFF_FULL,1=The Receive Buffer is full 0=The Receive Buffer is not full." "0: The Receive Buffer is not full,1: The Receive Buffer is full" newline bitfld.long 0x10 11. "TX_BUFF_STALL,1=The SPI interface had been stalled due to a flow issue (an attempt by the interface to read from an empty Transmit Buffer) 0=No stalls occurred." "0: No stalls occurred,1: The SPI interface had been stalled due to a flow.." newline bitfld.long 0x10 10. "TX_BUFF_REQ,This status is asserted if the Transmit Buffer reaches a high water mark established by the TRANSMIT_BUFFER_TRIGGER field. 1=TRANSMIT_BUFFER_COUNT is less than or equal to TRANSMIT_BUFFER_TRIGGER; 0=TRANSMIT_BUFFER_COUNT is greater than.." "0: TRANSMIT_BUFFER_COUNT is greater than..,1: TRANSMIT_BUFFER_COUNT is less than or equal to.." newline bitfld.long 0x10 9. "TX_BUFF_EMP,1=The Transmit Buffer is empty 0=The Transmit Buffer is not empty." "0: The Transmit Buffer is not empty,1: The Transmit Buffer is empty" newline bitfld.long 0x10 8. "TX_BUFF_FULL,1=The Transmit Buffer is full 0=The Transmit Buffer is not full." "0: The Transmit Buffer is not full,1: The Transmit Buffer is full" newline bitfld.long 0x10 6. "LDMA_TXERR,This bit is set if Local DMA Transmit error is detected. 1=Local DMA TX Error detected; 0=No Local DMA TX detected." "0: No Local DMA TX detected,1: Local DMA TX Error detected" newline bitfld.long 0x10 5. "LDMA_RXERR,This bit is set if Local DMA Receive error is detected. 1=Local DMA RX Error detected; 0=No Local DMA RX detected." "0: No Local DMA RX detected,1: Local DMA RX Error detected" newline bitfld.long 0x10 4. "PRGM_ERR,This bit if a programming error is detected. 1=Programming Error detected; 0=No programming error detected." "0: No programming error detected,1: Programming Error detected" newline bitfld.long 0x10 3. "RX_BUFF_ERR,1=Underflow error occurred (attempt to read from an empty Receive Buffer) 0=No underflow occurred." "0: No underflow occurred,1: Underflow error occurred" newline bitfld.long 0x10 2. "TX_BUFF_ERR,1=Overflow error occurred (attempt to write to a full Transmit Buffer) 0=No overflow occurred." "0: No overflow occurred,1: Overflow error occurred" newline bitfld.long 0x10 1. "DMA_COMPL,This field has no meaning if DMA is not enabled. This bit will be set to 1 when the DMA controller asserts the DONE signal to the SPI controller. This occurs either when the SPI controller has closed the DMA transfer or the DMA channel has.." "0: DMA not completed,1: DMA completed" newline bitfld.long 0x10 0. "TRANS_COMPL,In Manual Mode (neither DMA nor Description Buffers are enabled) this bit will be set to 1 when the transfer matches TRANSFER_LENGTH. If DMA Mode is enabled this bit will be set to 1 when DMA_COMPLETE is set to 1. In.." "0: Transfer not complete,1: Transfer completed" line.long 0x14 "BUF_CNT_STS,QMSPI Buffer Count Status Register" hexmask.long.word 0x14 16.--31. 1. "RX_BUFF_CNT,This is a count of the number of bytes currently valid in the Receive Buffer." newline hexmask.long.word 0x14 0.--15. 1. "TX_BUFF_CNT,This is a count of the number of bytes currently valid in the Transmit Buffer." line.long 0x18 "IEN,QMSPI Interrupt Enable Register" bitfld.long 0x18 14. "RX_BUF_REQ_EN,1=Enable an interrupt if RECEIVE_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_REQUEST is.." newline bitfld.long 0x18 13. "RX_BUF_EMPTY_EN,1=Enable an interrupt if RECEIVE_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_EMPTY is.." newline bitfld.long 0x18 12. "RX_BUF_FUL_EN,1=Enable an interrupt if RECEIVE_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_FULL is.." newline bitfld.long 0x18 10. "TX_BUF_REQ_EN,1=Enable an interrupt if TRANSMIT_BUFFER_REQUEST is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_REQUEST.." newline bitfld.long 0x18 9. "TX_BUF_EMPTY_EN,1=Enable an interrupt if TRANSMIT_BUFFER_EMPTY is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_EMPTY is.." newline bitfld.long 0x18 8. "TX_BUF_FULL_EN,1=Enable an interrupt if TRANSMIT_BUFFER_FULL is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_FULL is.." newline bitfld.long 0x18 6. "LDMA_TXERRIE,1=Enable an interrupt if Local DMA TX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA TX Error is.." newline bitfld.long 0x18 5. "LDMA_RXERRIE,1=Enable an interrupt if Local DMA RX Error is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if Local DMA RX Error is.." newline bitfld.long 0x18 4. "PRGM_ERR_EN,1=Enable an interrupt if PROGRAMMING_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if PROGRAMMING_ERROR is.." newline bitfld.long 0x18 3. "RX_BUF_ERR_EN,1=Enable an interrupt if RECEIVE_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if RECEIVE_BUFFER_ERROR is.." newline bitfld.long 0x18 2. "TX_BUF_ERR_EN,1=Enable an interrupt if TRANSMIT_BUFFER_ERROR is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSMIT_BUFFER_ERROR is.." newline bitfld.long 0x18 1. "DMA_COMPL_EN,1=Enable an interrupt if DMA_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if DMA_COMPLETE is asserted" newline bitfld.long 0x18 0. "TRANS_COMPL_EN,1=Enable an interrupt if TRANSFER_COMPLETE is asserted 0=Disable the interrupt." "0: Disable the interrupt,1: Enable an interrupt if TRANSFER_COMPLETE is.." line.long 0x1C "BUF_CNT_TRIG,QMSPI Buffer Count Trigger Register" hexmask.long.word 0x1C 16.--31. 1. "RX_BUF_TRIG,An interrupt is triggered if the RECEIVE_BUFFER_COUNT field is greater than or equal to this value. A value of 0 disables the interrupt." newline hexmask.long.word 0x1C 0.--15. 1. "TX_BUF_TRIG,An interrupt is triggered if the TRANSMIT_BUFFER_COUNT field is less than or equal to this value. A value of 0 disables the interrupt." line.long 0x20 "TX_FIFO,QMSPI Transmit Buffer Register" hexmask.long 0x20 0.--31. 1. "TX_BUF,Writes to this register store data to be transmitted from the SPI Master to the external SPI Slave. Writes to this block will be written to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word write fills 2 Bytes and a Doubleword.." line.long 0x24 "RX_FIFO,QMSPI Receive Buffer Register" hexmask.long 0x24 0.--31. 1. "RX_BUF,Buffer that stores data from the external SPI Slave device to the SPI Master (this block) which is received over MISO or IO. Reads from this register will empty the Rx FIFO. A 1 Byte read will have valid data on bits [7:0] and a Word read.." line.long 0x28 "CSTM,QMSPI Chip Select Timing Register" hexmask.long.byte 0x28 24.--31. 1. "DLY_CS_OFF_TO_CS_ON,This selects the number of system clock cycles between CS deassertion to CS assertion. This is the minimum pulse width of CS deassertion." newline hexmask.long.byte 0x28 16.--19. 1. "DLY_LAST_DATA_HOLD,This selects the number of system clock cycles between CS deassertion to the data ports for WP and HOLD switching from input to output." newline hexmask.long.byte 0x28 8.--11. 1. "DLY_CLK_STOP_TO_CS_OFF,This selects the number of system clock cycles between the last clock edge and the deassertion of CS." newline hexmask.long.byte 0x28 0.--3. 1. "DLY_CS_ON_TO_CLOCK_START,This selects the number of system clock cycles between CS assertion to the start of the SPI Clock." repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x30)++0x3 line.long 0x0 "DESCR[$1],QMSPI Description Buffer 0 Register" hexmask.long.word 0x0 17.--31. 1. "TX_LEN,The length of the SPI transfer. The count is in bytes or bits depending on the value of TRANSFER_LENGTH_BITS. A value of 0 means an infinite length transfer." newline bitfld.long 0x0 16. "DESCR_BUF_LAST,Last Descriptor. 1=Last Description Buffer in the chain. 0=This is not the last buffer." "0: This is not the last buffer,1: Last Description Buffer in the chain" newline hexmask.long.byte 0x0 12.--15. 1. "DESCR_BUF_NXT_PTR,This defines the next buffer to be used if Description Buffers are enabled and this is not the last buffer. This can point to the current buffer creating an infinite loop." newline bitfld.long 0x0 10.--11. "TRANS_LEN,3=TRANSFER_LENGTH defined in units of 16-byte segments 2=TRANSFER_LENGTH defined in units of 4-byte segments 1=TRANSFER_LENGTH defined in units of bytes 0=TRANSFER_LENGTH defined in units of bits" "0: TRANSFER_LENGTH defined in units of bits,1: TRANSFER_LENGTH defined in units of bytes,2: TRANSFER_LENGTH defined in units of 4-byte..,3: TRANSFER_LENGTH defined in units of 16-byte.." newline bitfld.long 0x0 9. "CLOSE_TRANS_EN,This selects what action is taken at the end of a transfer. This bit must be set only on the Last Buffer. 1=The transfer is terminated. The Chip Select de-asserts the SPI interface returns to IDLE and the DMA interface completes the.." "0: The transfer is not closed,1: The transfer is terminated" newline bitfld.long 0x0 7.--8. "RX_DMA_EN,This bit enables DMA support for Receive Transfer. If enabled DMA will be requested to empty the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA programmed.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 6. "RX_TRANS_EN,This bit enables the receive function of the SPI interface. 1=Receive is enabled. Data received from the SPI Slave is stored in the Receive Buffer; 0=Receive is disabled." "0: Receive is disabled,1: Receive is enabled" newline bitfld.long 0x0 4.--5. "TX_DMA_EN,This bit enables DMA support for Transmit Transfer. If enabled DMA will be requested to fill the FIFO until either the interface reaches TRANSFER_LENGTH or the DMA sends a termination request. The size defined here must match DMA.." "0: DMA is disabled,1: DMA is enabled,2: DMA is enabled and set to 2 Bytes,3: DMA is enabled and set to 4 Bytes" newline bitfld.long 0x0 2.--3. "TX_TRANS_EN,This field bit selects the transmit function of the SPI interface. 3=Transmit Enabled in 1 Mode. The MOSI or IO Bus will send out only 1's. The Transmit Buffer will not be used 2=Transmit Enabled in 0 Mode. The MOSI or IO Bus will.." "0: Transmit is Disabled,1: Transmit Enabled,2: Transmit Enabled in 0 Mode,3: Transmit Enabled in 1 Mode" newline bitfld.long 0x0 0.--1. "INFACE_MOD,This field sets the transmission mode. If this field is set for Dual Mode or Quad Mode then either TX_TRANSFER_ENABLE or RX_TRANSFER_ENABLE must be 0. 3=Reserved; 2=Quad Mode; 1=Dual Mode; 0=Single/Duplex Mode." "0: Single/Duplex Mode,1: Dual Mode,2: Quad Mode,3: Reserved" repeat.end wgroup.long 0xB0++0x3 line.long 0x0 "ALIAS_CTRL,QMSPI Alias Control Register" hexmask.long.byte 0x0 24.--31. 1. "ALS_TXDBUF_DATA,The Byte of data written into the Tx Buffer if the write is enabled." newline hexmask.long.byte 0x0 16.--23. 1. "ALS_DBUF_XFR_LEN,The value of the data written to the Description Buffers Transfer Length field if the write is enabled." newline hexmask.long.byte 0x0 12.--15. 1. "ALS_DBUF_SEL,Which Description Buffer will be modified by a write if Alias Write Description Buffer Transfer Length is set." newline hexmask.long.byte 0x0 8.--11. 1. "ALS_CTRL_DBUF_PTR,Alias for the QMSPI Control:Description Buffer Pointer field." newline bitfld.long 0x0 6. "ALS_LDMA_INCR_ADD,Alias that overrides the value in all QMSPI Local DMA * [Tx/Rx] Control:Increment Address Enable fields w/ this value." "0,1" newline bitfld.long 0x0 4.--5. "ALS_MOD_CS,Alias for the QMSPI Mode:Chip Select field." "0,1,2,3" newline bitfld.long 0x0 3. "ALS_WRDBUF_XFRLEN,Alias that triggers a write to the Description Buffer pointed to by Alias Description Buffer Select in this register to modify the Transfer Length field with the value of Alias Description Buffer Transfer Length in this register." "0,1" newline bitfld.long 0x0 2. "ALS_WR_TXBUF,Alias that triggers a write to the Tx Buffer of 1 Byte using data from Alias Tx Buffer Data in this register." "0,1" newline bitfld.long 0x0 1. "CLS_ALTMODE_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" newline bitfld.long 0x0 0. "ALS_EXEC_STRT,Alias for the QMSPI Execution:Start field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MODE_ALT1,QMSPI Mode Alternate 1 Register" hexmask.long.word 0x0 16.--31. 1. "CS1_ALTCLK_DIV,The SPI clock divide in number of system clocks when CS1 is in use and CS1 Alt Mode Enable is set." newline bitfld.long 0x0 0. "CS1_ALTMOD_EN,Enable the CS1 Clock Divide to be active if CS1 is the interface in use." "0,1" group.long 0xD0++0xB line.long 0x0 "TAPS,QMSPI TAPs Register" hexmask.long.byte 0x0 8.--15. 1. "CTRL_TAP,This will select the tap point for signals that go from the System Domain." newline hexmask.long.byte 0x0 0.--7. 1. "SCK_TAP,This will select the tap point for the feed-back SCK." line.long 0x4 "TAP_ADJ,QMSPI TAP Control Register" hexmask.long.byte 0x4 8.--15. 1. "CTRL_ADJ,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." newline hexmask.long.byte 0x4 0.--7. 1. "SCK_ADJ,This is a signed value that will be added to the Select SCK Tap to come up with the final value for the delay." line.long 0x8 "TAP_CTRL,QMSPI TAP Adjustment Register" bitfld.long 0x8 16.--18. "AUTO_MULT,This will multiply the target delay value the Auto-trim H/W will search for." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "FW_GO,This will force the auto-trim H/W to run and find a new trim value." "0,1" newline bitfld.long 0x8 2. "CTRL,This is a signed value that will be added to the Select Control Tap to come up with the final value for the delay." "0,1" newline bitfld.long 0x8 0.--1. "AUTO_MOD,This enables the automatic H/W trim of the Tap." "0,1,2,3" group.long 0x104++0x3 line.long 0x0 "DESC_LDMA_TXEN,QMSPI Descriptor Local DMA Tx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_TXEN,This enables the Local TX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." group.long 0x100++0x3 line.long 0x0 "DESC_LDMA_RXEN,QMSPI Descriptor Local DMA Rx Enable Register" hexmask.long.word 0x0 0.--15. 1. "DESC_LDMA_RXEN,This enables the Local RX DMA usage (instead of the Central DMA) when the Descriptor Buffer register enables the DMA." repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070310 ad:0x40070320 ad:0x40070330) tree "LDMA_RX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_RXCTRL,QMSPI RX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local RX DMA Channel." "0,1" line.long 0x4 "LDMA_RXSTRT_ADDR,QMSPI Local DMA Rx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (write to this address on Rx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_RX_LEN,QMSPI Local DMA Rx Length Register" hexmask.long 0x8 0.--31. 1. "RX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070340 ad:0x40070350 ad:0x40070360) tree "LDMA_TX[$1]" base $2 group.long ($2)++0xB line.long 0x0 "LDMA_TXCTRL,QMSPI TX Control Register" bitfld.long 0x0 6. "INC_ADDR_EN,When set the DMA Channels Start Address will increment on every access. If not set the address will not increment." "0,1" bitfld.long 0x0 4.--5. "ACS_SZ,Access Size selects the AHB Access Size." "0,1,2,3" bitfld.long 0x0 3. "OVRD_LEN,Override Lenght will override the length field to the QMSPI protocol FSM with the length programmed into the Local DMA." "0,1" bitfld.long 0x0 2. "BUF_ADDR_EN,Address re-enable will automatically re-enables the same address upon completion previous transfer." "0,1" bitfld.long 0x0 1. "RSTRT_EN,This bit automatically re-enables the Local DMA Channel after completion of previous transfer." "0,1" bitfld.long 0x0 0. "CH_EN,This enables the Local TX DMA Channel." "0,1" line.long 0x4 "LDMA_TXSTRT_ADDR,QMSPI Local DMA Tx Start Address Register" hexmask.long 0x4 0.--31. 1. "STRT_ADDR,This is the Starting Address for the DMA access into the memory space (Read from this address on Tx). This address is updated by the transfer size based on the Local DMA Access Size after every access." line.long 0x8 "LDMA_TX_LEN,QMSPI Local DMA Tx Length Register" hexmask.long 0x8 0.--31. 1. "TX_LEN,This is the maximum Length of the transfer in Bytes that the DMA Channel will allow access to." rgroup.long ($2+0xC)++0x3 line.long 0x0 "RSVD,Reserved Register" tree.end repeat.end tree.end endif tree.end sif (cpuis("CEC1702*")) tree "RC_ID (Resistor/Capacitor Identification Detection)" base ad:0x0 tree "RC_ID0" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CTRL,RC_ID Control Register" bitfld.long 0x0 8.--9. "CLOCK_SET,This field selects the frequency of the Counter circuit clock. This field must retain the same value as long as the ENABLE bit in this register is 1." "0,1,2,3" bitfld.long 0x0 7. "ENABLE,Clearing the bit to 0 causes the RC_ID interface to enter the Reset state gating its clocks clearing the status bits in this register and entering \n into its lowest power state. Setting this bit to 1 causes the RC_ID interface to enter.." "0,1" bitfld.long 0x0 6. "START,Setting this bit to 1 initiates the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 2. "CY_ER,This bit is 1 if an RC_ID measurement encountered an error and the reading in the RC_ID Data Register is invalid. This bit is cleared to 0 when the RC_ID interface is in the Reset phase." "0,1" bitfld.long 0x0 1. "TC,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 0. "DONE,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes an RC_ID measurement." "0,1" line.long 0x4 "DAT,Reads of this register provide the result of an RC_ID measurement." hexmask.long.word 0x4 0.--15. 1. "RCID_DATA,Reads of this register provide the result of an RC_ID measurement." tree.end tree "RC_ID1" base ad:0x40001480 group.long 0x0++0x7 line.long 0x0 "CTRL,RC_ID Control Register" bitfld.long 0x0 8.--9. "CLOCK_SET,This field selects the frequency of the Counter circuit clock. This field must retain the same value as long as the ENABLE bit in this register is 1." "0,1,2,3" bitfld.long 0x0 7. "ENABLE,Clearing the bit to 0 causes the RC_ID interface to enter the Reset state gating its clocks clearing the status bits in this register and entering \n into its lowest power state. Setting this bit to 1 causes the RC_ID interface to enter.." "0,1" bitfld.long 0x0 6. "START,Setting this bit to 1 initiates the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 2. "CY_ER,This bit is 1 if an RC_ID measurement encountered an error and the reading in the RC_ID Data Register is invalid. This bit is cleared to 0 when the RC_ID interface is in the Reset phase." "0,1" bitfld.long 0x0 1. "TC,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes the Discharged phase of an RC_ID measurement." "0,1" bitfld.long 0x0 0. "DONE,This bit is cleared to 0 when the RC_ID interface is in the Reset phase and set to 1 when the interface completes an RC_ID measurement." "0,1" line.long 0x4 "DAT,Reads of this register provide the result of an RC_ID measurement." hexmask.long.word 0x4 0.--15. 1. "RCID_DATA,Reads of this register provide the result of an RC_ID measurement." tree.end tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "RTC (Real Time Clock)" base ad:0x400F5000 group.byte 0x0++0xD line.byte 0x0 "SEC,Seconds Register" line.byte 0x1 "SEC_ALARM,Seconds Alarm Register" line.byte 0x2 "MIN,Minutes Register" line.byte 0x3 "MIN_ALARM,Minutes Alarm Register" line.byte 0x4 "HR,Hours Register" line.byte 0x5 "HR_ALARM,Hours Alarm Register" line.byte 0x6 "DAY_OF_WK,Day of Week Register" line.byte 0x7 "DAY_OF_MON,Day of Month Register" line.byte 0x8 "MONTH,Month Register" line.byte 0x9 "YEAR,Year Register" line.byte 0xA "REGA,Register A" line.byte 0xB "REGB,Register B" line.byte 0xC "REGC,Register C" line.byte 0xD "REGD,Register D" group.long 0x10++0xF line.long 0x0 "CTRL,RTC Control Register" bitfld.long 0x0 3. "ALM_EN,ALM_EN 1=Enables the Alarm features 0=Disables the Alarm features" "0: Disables the Alarm features,1: Enables the Alarm features" bitfld.long 0x0 2. "TEST,TEST" "0,1" bitfld.long 0x0 1. "SOFT_RST,SOFT_RST A '1' written to this bit position will trigger the RTC_RST reset resetting the block and all registers except\n this one and the Test Register. This bit is self-clearing at the end of the reset one cycle of Host Bus Clock later .." "0,1" bitfld.long 0x0 0. "BLK_EN,BLK_EN This bit must be '1' in order for the block to function internally. Registers may be initialized first before\n setting this bit to '1' to start operation." "0,1" line.long 0x4 "WK_ALARM,Week Alarm Register[7:0] - ALARM_DAY_OF_WEEK This register. if written to a value in the range 1- -7. will inhibit the Alarm\n interrupt unless this field matches the contents of the Day of Week Register also." line.long 0x8 "DAYLT_SAVF,Daylight Savings Forward Register" bitfld.long 0x8 31. "DST_AM_PM,This bit selects AM vs. PM to match bit[7] of the Hours Register if 12-Hour mode is selected in Register B at the time\n of writing." "0,1" hexmask.long.byte 0x8 24.--30. 1. "DST_HR,This field holds the matching value for bits[6:0] of the Hours register. The written value will be interpreted according\n to the 24/12 Hour mode and DM mode settings at the time of writing." bitfld.long 0x8 16.--18. "DST_WK,5=Last week of month 4 =Fourth week of month 3=Third week of month 2=Second week of month 1=First week of month" "?,1: First week of month,2: Second week of month,3: Third week of month,4: Fourth week of month,5: Last week of month,?,?" bitfld.long 0x8 8.--10. "DST_DAY_OF_WK,This field matches the Day of Week Register bits[2:0]." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 0.--7. 1. "DST_MON,This field matches the Month Register." line.long 0xC "DAYLT_SAVB,Daylight Savings Backward Register" bitfld.long 0xC 31. "DST_AM_PM,This bit selects AM vs. PM to match bit[7] of the Hours Register if 12-Hour mode is selected in Register B at the time\n of writing." "0,1" hexmask.long.byte 0xC 24.--30. 1. "DST_HR,This field holds the matching value for bits[6:0] of the Hours register. The written value will be interpreted according\n to the 24/12 Hour mode and DM mode settings at the time of writing." bitfld.long 0xC 16.--18. "DST_WK,5=Last week of month 4 =Fourth week of month 3=Third week of month 2=Second week of month 1=First week of month" "?,1: First week of month,2: Second week of month,3: Third week of month,4: Fourth week of month,5: Last week of month,?,?" bitfld.long 0xC 8.--10. "DST_DAY_OF_WK,This field matches the Day of Week Register bits[2:0]." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--7. 1. "DST_MON,This field matches the Month Register." tree.end endif tree "RTOS (RTOS Timer)" base ad:0x40007400 group.long 0x0++0xB line.long 0x0 "CNT,RTOS Timer Count Register." hexmask.long 0x0 0.--31. 1. "CNTR,This register contains the current value of the RTOS Timer counter. This register should be read as a DWORD. There is no latching mechanism \n of the upper bytes implemented if the register is accessed as a byte or word. Reading the register.." line.long 0x4 "PRLD,RTOS Timer Preload Register" hexmask.long 0x4 0.--31. 1. "PRELOAD,The this register is loaded into the RTOS Timer counter either when the TIMER_START bit is written with a 1 or when the timer counter counts down to 0 and the AUTO_RELOAD bit is 1.\n This register must be programmed with a new count value.." line.long 0x8 "CTRL,RTOS Timer Control Register" bitfld.long 0x8 4. "FW_TMR_HALT,1=The timer counter is halted. If the counter was running clearing this bit will restart the counter from the value at which it halted\n 0=The timer counter if enabled will continue to run" "0: The timer counter,1: The timer counter is halted" bitfld.long 0x8 3. "EXT_HW_HALT_EN,1=The timer counter is halted when the external HALT signal is asserted. Counting is always enabled if HALT is de-asserted.\n 0=The HALT signal does not affect the RTOS Timer" "0: The HALT signal does not affect the RTOS Timer,1: The timer counter is halted when the external.." newline bitfld.long 0x8 2. "TMR_STRT,Writing a 1 to this bit will load the timer counter with the RTOS Timer Preload Register and start counting.\n If the Preload Register is 0 counting will not start and this bit will be cleared to 0.\n Writing a 0 to this bit will.." "0,1" bitfld.long 0x8 1. "AU_RELOAD,1=The the RTOS Timer Preload Register is loaded into the timer counter and the counter is restarted when the counter transitions from 1 to 0\n 0=The timer counter halts when it transitions from 1 to 0 and will not restart." "0: The timer counter halts when it transitions from..,1: The the RTOS Timer Preload Register is loaded.." newline bitfld.long 0x8 0. "BLK_EN,1=RTOS timer counter is enabled\n 0=RTOS timer disabled. All register bits are reset to their default state" "0: RTOS timer disabled,1: RTOS timer counter is enabled\n" wgroup.long 0xC++0x3 line.long 0x0 "SOFTIRQ,Soft Interrupt Register" bitfld.long 0x0 3. "SWI3,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC.\n Writes of a '0' have no effect. Reads return '0'." "0,1" bitfld.long 0x0 2. "SWI2,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC.\n Writes of a '0' have no effect. Reads return '0'." "0,1" newline bitfld.long 0x0 1. "SWI1,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC.\n Writes of a '0' have no effect. Reads return '0'." "0,1" bitfld.long 0x0 0. "SWI0,Software Interrupt. A write of a '1' to this bit will generate an SWI interrupt to the EC.\n Writes of a '0' have no effect. Reads return '0'." "0,1" tree.end tree "SCR (System Control Registers)" base ad:0xE000E000 rgroup.long 0x4++0x3 line.long 0x0 "ICTR,Interrupt Controller Type Register" hexmask.long.byte 0x0 0.--3. 1. "INTLINESNUM" group.long 0x8++0x3 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x0 9. "DISOOFP,Disable out-of-order FP instructions" "0,1" bitfld.long 0x0 8. "DISFPCA,Disable automatic update of CONTROL.FPCA" "0,1" newline bitfld.long 0x0 2. "DISFOLD,Disable IT folding" "0,1" bitfld.long 0x0 1. "DISDEFWBUF,Disable wruite buffer use during default memory map accesses" "0,1" newline bitfld.long 0x0 0. "DISMCYCINT,Disable interruption of LDM/STM instructions" "0,1" rgroup.long 0xD00++0x3 line.long 0x0 "CPUID,CPUID Base Register" hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer code 0x41=ARM" hexmask.long.byte 0x0 20.--23. 1. "VARIANT,Variant number" newline hexmask.long.byte 0x0 16.--19. 1. "CONSTANT,Constant" hexmask.long.word 0x0 4.--15. 1. "PARTNO,Process Part Number 0xC24=Cortex-M4" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Processor revision number" group.long 0xD04++0x3 line.long 0x0 "ICSR,Interrupt Control and State Register" bitfld.long 0x0 31. "NMIPENDSET,NMI set-pending bit" "0: Write: no effect; read: NMI exception is not..,1: Write: changes NMI exception state to pending;.." bitfld.long 0x0 28. "PENDSVSET,PendSV set-pending bit" "0: Write: no effect; read: PendSV exception is not..,1: Write: changes PendSV exception state to.." newline bitfld.long 0x0 27. "PENDSVCLR,PendSV clear-pending bit" "0: No effect,1: Removes the pending state from the PendSV.." bitfld.long 0x0 26. "PENDSTSET,SysTick set-pending bit" "0: Write: no effect; read: SysTick exception is not..,1: Write: changes SysTick exception state to.." newline bitfld.long 0x0 25. "PENDSTCLR,SysTick clear-pending bit" "0: No effect,1: Removes the pending state from the SysTick.." bitfld.long 0x0 23. "ISRPREEMPT,Debug only" "0,1" newline bitfld.long 0x0 22. "ISRPENDING,Interrupt pending flag" "0,1" hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Exception number of the highest priority pending enabled exception" newline bitfld.long 0x0 11. "RETTOBASE,No preempted active exceptions to execute" "0,1" hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Active exception number" group.long 0xD0C++0x33 line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x0 16.--31. 1. "VECTKEY,Register key" bitfld.long 0x0 15. "ENDIANNESS,Data endianness 0=little 1=big" "0: little,1: big" newline bitfld.long 0x0 8.--10. "PRIGROUP,Interrupt priority grouping" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request" "0: No system reset request,1: Asserts a signal to the outer system that.." newline bitfld.long 0x0 1. "VECTCLRACTIVE,Must write 0" "0,1" bitfld.long 0x0 0. "VECTRESET,Must write 0" "0,1" line.long 0x4 "SCR,System Control Register" bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup the..,1: Enabled events and all interrupts including.." bitfld.long 0x4 2. "SLEEPDEEP,Deep Sleep used as low power mode" "0: Sleep,1: Deep sleep" newline bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit on handler return" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR" line.long 0x8 "CCR,Configuration and Control Register" bitfld.long 0x8 9. "STKALIGN,Indicates stack alignment on exception entry" "0: 4-byte aligned,1: 8-byte aligned" bitfld.long 0x8 8. "BFHFNMIGN,Ignore LDM/STM BusFault for -1/-2 priority handlers" "0,1" newline bitfld.long 0x8 4. "DIV_0_TRP,Enables divide by 0 trap" "0,1" bitfld.long 0x8 3. "UNALIGN_TRP,Enables unaligned access traps" "0: Do not trap unaligned halfword and word accesses,1: Trap unaligned halfword and word accesses" newline bitfld.long 0x8 1. "USERSETMPEND,Enables unprivileged software access to STIR register" "0,1" bitfld.long 0x8 0. "NONBASETHRDENA,Indicates how processor enters Thread mode" "0,1" line.long 0xC "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0xC 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault" hexmask.long.byte 0xC 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault" newline hexmask.long.byte 0xC 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage" line.long 0x10 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x10 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall" line.long 0x14 "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x14 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick exception" hexmask.long.byte 0x14 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV" line.long 0x18 "SHCSR,System Handler Control and State Register" bitfld.long 0x18 18. "USGFAULTENA,UsageFault enable bit" "0,1" bitfld.long 0x18 17. "BUSFAULTENA,BusFault enable bit" "0,1" newline bitfld.long 0x18 16. "MEMFAULTENA,MemManage enable bit" "0,1" bitfld.long 0x18 15. "SVCALLPENDED,SVCall pending bit" "0,1" newline bitfld.long 0x18 14. "BUSFAULTPENDED,BusFault exception pending bit" "0,1" bitfld.long 0x18 13. "MEMFAULTPENDED,MemManage exception pending bit" "0,1" newline bitfld.long 0x18 12. "USGFAULTPENDED,UsageFault exception pending bit" "0,1" bitfld.long 0x18 11. "SYSTICKACT,SysTick exception active bit" "0,1" newline bitfld.long 0x18 10. "PENDSVACT,PendSV exception active bit" "0,1" bitfld.long 0x18 8. "MONITORACT,DebugMonitor exception active bit" "0,1" newline bitfld.long 0x18 7. "SVCALLACT,SVCall active bit" "0,1" bitfld.long 0x18 3. "USGFAULTACT,UsageFault exception active bit" "0,1" newline bitfld.long 0x18 1. "BUSFAULTACT,BusFault exception active bit" "0,1" bitfld.long 0x18 0. "MEMFAULTACT,MemManage exception active bit" "0,1" line.long 0x1C "CFSR,Configurable Fault Status Register" bitfld.long 0x1C 25. "DIVBYZERO,Divide by zero UsageFault" "0,1" bitfld.long 0x1C 24. "UNALIGNED,Unaligned access UsageFault" "0,1" newline bitfld.long 0x1C 19. "NOCP,No coprocessor UsageFault" "0,1" bitfld.long 0x1C 18. "INVPC,Invalid PC load UsageFault" "0,1" newline bitfld.long 0x1C 17. "INVSTATE,Invalid state UsageFault" "0,1" bitfld.long 0x1C 16. "UNDEFINSTR,Undefined instruction UsageFault" "0,1" newline bitfld.long 0x1C 15. "BFARVALID,BusFault Address Register valid" "0,1" bitfld.long 0x1C 13. "LSPERR,BusFault occured during FP lazy state preservation" "0,1" newline bitfld.long 0x1C 12. "STKERR,BusFault on stacking for exception entry" "0,1" bitfld.long 0x1C 11. "UNSTKERR,BusFault on unstacking for exception return" "0,1" newline bitfld.long 0x1C 10. "IMPRECISERR,Imprecise data bus error" "0,1" bitfld.long 0x1C 9. "PRECISERR,Precise data bus error" "0,1" newline bitfld.long 0x1C 8. "IBUSERR,Instruction bus error" "0,1" bitfld.long 0x1C 7. "MMARVALID,MemManage Fault Address Register valid" "0,1" newline bitfld.long 0x1C 5. "MLSPERR,MemManager Fault occured during FP lazy state preservation" "0,1" bitfld.long 0x1C 4. "MSTKERR,MemManage Fault on stacking for exception entry" "0,1" newline bitfld.long 0x1C 3. "MUNSTKERR,MemManage Fault on unstacking for exception return" "0,1" bitfld.long 0x1C 1. "DACCVIOL,Data access violation" "0,1" newline bitfld.long 0x1C 0. "IACCVIOL,Instruction access violation" "0,1" line.long 0x20 "HFSR,HardFault Status Register" bitfld.long 0x20 31. "DEBUGEVT,Debug: always write 0" "0,1" bitfld.long 0x20 30. "FORCED,Forced Hard Fault" "0,1" newline bitfld.long 0x20 1. "VECTTBL,BusFault on a Vector Table read during exception processing" "0,1" line.long 0x24 "DFSR,Debug Fault Status Register" bitfld.long 0x24 4. "EXTERNAL" "0,1" bitfld.long 0x24 3. "VCATCH" "0,1" newline bitfld.long 0x24 2. "DWTTRAP" "0,1" bitfld.long 0x24 1. "BKPT" "0,1" newline bitfld.long 0x24 0. "HALTED" "0,1" line.long 0x28 "MMFAR,MemManage Fault Address Register" hexmask.long 0x28 0.--31. 1. "ADDRESS,Address that generated the MemManage fault" line.long 0x2C "BFAR,BusFault Address Register" hexmask.long 0x2C 0.--31. 1. "ADDRESS,Address that generated the BusFault" line.long 0x30 "AFSR,Auxiliary Fault Status Register" hexmask.long 0x30 0.--31. 1. "IMPDEF,AUXFAULT input signals" repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xD40)++0x3 line.long 0x0 "PFR[$1],Processor Feature Register" repeat.end rgroup.long 0xD48++0x7 line.long 0x0 "DFR,Debug Feature Register" line.long 0x4 "ADR,Auxiliary Feature Register" repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xD50)++0x3 line.long 0x0 "MMFR[$1],Memory Model Feature Register" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) rgroup.long ($2+0xD60)++0x3 line.long 0x0 "ISAR[$1],Instruction Set Attributes Register" repeat.end group.long 0xD88++0x3 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11" "0: Access denied,1: Privileged access only,?,3: Full access" bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10" "0: Access denied,1: Privileged access only,?,3: Full access" tree.end tree "SMB (SMB Controller)" base ad:0x0 sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "SMB0" base ad:0x40004000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" endif bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,STXB" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SRXB" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MTXB" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MRXB" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" sif (cpuis("CEC1712*")) group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte.\n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address.\n This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear.\n R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register.\n 1= ACK. \n 0= NAK. \n" "0: NAK,1: ACK" endif tree.end endif sif (cpuis("CEC1734?2HW*")) tree "SMB0" base ad:0x40004000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB1" base ad:0x40004400 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB2" base ad:0x40004800 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB3" base ad:0x40004C00 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1734?2ZW*")) tree "SMB0" base ad:0x40004000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB1" base ad:0x40004400 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB2" base ad:0x40004800 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB3" base ad:0x40004C00 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1736?2HW*")) tree "SMB0" base ad:0x40004000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB1" base ad:0x40004400 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB2" base ad:0x40004800 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB3" base ad:0x40004C00 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1736?2ZW*")) tree "SMB0" base ad:0x40004000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB1" base ad:0x40004400 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB2" base ad:0x40004800 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end tree "SMB3" base ad:0x40004C00 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "SMB1" base ad:0x40004400 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" endif bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,STXB" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SRXB" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MTXB" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MRXB" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" sif (cpuis("CEC1712*")) group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte.\n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address.\n This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear.\n R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register.\n 1= ACK. \n 0= NAK. \n" "0: NAK,1: ACK" endif tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "SMB2" base ad:0x40004800 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" endif bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,STXB" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SRXB" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MTXB" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MRXB" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" sif (cpuis("CEC1712*")) group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte.\n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address.\n This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear.\n R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register.\n 1= ACK. \n 0= NAK. \n" "0: NAK,1: ACK" endif tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "SMB3" base ad:0x40004C00 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" endif bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,STXB" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SRXB" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MTXB" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MRXB" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" sif (cpuis("CEC1712*")) group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte.\n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address.\n This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear.\n R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register.\n 1= ACK. \n 0= NAK. \n" "0: NAK,1: ACK" endif tree.end endif sif (cpuis("CEC1712*")) tree "SMB4" base ad:0x40005000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0').\n When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register\n Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave.." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "RD_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold\n the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "RSVD2,Reserved" group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. \n 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. \n 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit.\n 0: the response to the General Call address as a slave is enabled\n 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State).\n The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available.\n 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter\n THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when\n written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable.\n 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte.\n" group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address.\n This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear.\n R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register.\n 1= Interrupt Enable. \n 0= Interrupt Disabled. \n" "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register.\n 1= ACK. \n 0= NAK. \n" "0: NAK,1: ACK" tree.end endif sif (cpuis("CEC1734?2HW*")) tree "SMB4" base ad:0x40005000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1734?2ZW*")) tree "SMB4" base ad:0x40005000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1736?2HW*")) tree "SMB4" base ad:0x40005000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif sif (cpuis("CEC1736?2ZW*")) tree "SMB4" base ad:0x40005000 wgroup.long 0x0++0x3 line.long 0x0 "WCTRL,Control Register" bitfld.long 0x0 7. "PIN,The Pending Interrupt Not (PIN) bit serves as a software reset function. Writing the PIN bit to a logic '1' de-asserts all status bits except for the nBB bit which is not affected by the PIN bit. The PIN bit is a self-clearing bit. Writing this bit.." "0,1" bitfld.long 0x0 6. "ESO,The Enable Serial Output bit (ESO) enables and disables the SMB Controller Core serial data output (SDAT)" "0,1" newline bitfld.long 0x0 3. "ENI,Enable Interrupt bit (ENI) controls the Interrupt Interface" "0,1" bitfld.long 0x0 2. "STA,The STA and STO bits control the generation of the I2C Start condition and the transmission of the Slave Address and R/nW bit (from the Data Register) generation of repeated Start condition and generation of the Stop condition" "0,1" newline bitfld.long 0x0 1. "STO,See STA description" "0,1" bitfld.long 0x0 0. "ACK,The Acknowledge bit (ACK) must normally be asserted ('1'). This causes the controller to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). The ACK bit must not be asserted ('0') when the controller is.." "0,1" rgroup.long 0x0++0x3 line.long 0x0 "RSTS,Status Register" bitfld.long 0x0 7. "PIN,Pending Interrupt bit" "0,1" bitfld.long 0x0 6. "SAD,SMBus Address Decoded (SAD)" "0,1" newline bitfld.long 0x0 5. "STS,When in slave receiver mode STS is asserted ('1') when an externally generated STOP condition is detected. Note that STS is used only in slave receiver mode." "0,1" bitfld.long 0x0 4. "BER,When Bus Error (BER) is asserted a misplaced START or STOP condition or Bus Time-Outs have been detected." "0,1" newline bitfld.long 0x0 3. "LRB_AD0,The Last Received Bit or Address 0 (general call) bit (LRB/AD0) serves a dual function and is valid only while the PIN bit is asserted ('0'). When the AAS bit is not asserted ('0') (i.e. not addressed as a slave) the LRB/AD0.." "0,1" bitfld.long 0x0 2. "AAS,The Addressed As Slave bit (AAS) is valid only when PIN is asserted ('0'). When acting as slave AAS is set when an incoming address over the bus matches the value in the Own Address Register or if the 'general call' address (00h) has been received" "0,1" newline bitfld.long 0x0 1. "LAB,The Lost Arbitration Bit (LAB) is set when in multi-master operation arbitration is lost to another master on the bus" "0,1" bitfld.long 0x0 0. "NBB,The Bus Busy bit (NBB) is a read-only flag indicating when the bus is in use. A zero indicates that the bus is busy and access is not possible." "0,1" group.long 0x4++0x3 line.long 0x0 "OWN_ADDR,Own Address Register Note that the Data Register and Own Address fields are offset by one bit. so that programming Own Address 1 with a value of 55h will result in the value AAh being recognized as the SMB Controller Core slave address." hexmask.long.byte 0x0 8.--14. 1. "ADDR2,The Own Address 2 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." hexmask.long.byte 0x0 0.--6. 1. "ADDR1,The Own Address 1 bits configure one of the two addresses to which the SMB Controller Core will respond when addressed as a slave." group.byte 0x8++0x0 line.byte 0x0 "I2CDATA,This register holds the data that are either shifted out to or shifted in from the I2C port." repeat 3. (increment 0x0 0x1)(increment 0x0 0x1) rgroup.byte ($2+0x9)++0x0 line.byte 0x0 "RSVD1[$1],Reserved" repeat.end group.long 0xC++0xF line.long 0x0 "MCMD,SMBus Master Command Register" hexmask.long.byte 0x0 24.--31. 1. "RD_CNT,This field is a count of the number of bytes to read in from the SMBus to the SMBus Master Receive Buffer Register and must be greater than 0 in order for the Master State Machine to initiate a read phase. It is decremented by 1 for each byte read.." hexmask.long.byte 0x0 16.--23. 1. "WR_CNT,This field is a count of the number of bytes to transmit to the SMBus from the SMBus Master Transmit Buffer Register It is decremented by 1 for each byte written to the SMBus from the SMBus Master Transmit Buffer Register." newline bitfld.long 0x0 13. "READ_PEC,If this bit is 0 reading from the SMBus stops when ReadCount reaches 0. If this bit is 1 reading continues when ReadCount is 0 for one more byte." "0,1" bitfld.long 0x0 12. "READM,If this bit is 1 then the ReadCount field is replaced by the byte that is read from the SMBus when ReadCount[7:0] is 1. After ReadCount[7:0] is updated this bit is cleared to 0." "0,1" newline bitfld.long 0x0 11. "PEC_TERM,If this bit is 1 a copy of the PEC register is transmitted when WriteCount is 0. After the PEC register is read both the PEC register and this bit are cleared to 0." "0,1" bitfld.long 0x0 10. "STOP,If this bit is 1 send a Stop bit after the transaction completes." "0,1" newline bitfld.long 0x0 9. "STARTN,If this bit is 1 send a Start bit just before the last byte of the WriteCount is sent to the SMBus transmitter." "0,1" bitfld.long 0x0 8. "START0,If this bit is 1 send a Start bit on the SMBus before the first byte of the WriteCount is sent to the SMBus transmitter." "0,1" newline bitfld.long 0x0 1. "MPROCEED,When this bit is 0 the Master State Machine does not transition out of the IDLE or PAUSE states. When this bit is 1 the Master State Machine immediately transitions to the WAIT-BUSBUSY and MRUN-RECEIVE states respectively." "0,1" bitfld.long 0x0 0. "MRUN,While this bit is 1 transfer bytes over SMBus. As long as WriteCount is non-zero a byte from the Master Transmit Buffer is transmitted to the slave device and WriteCount is decremented." "0,1" line.long 0x4 "SCMD,SMBus Slave Command Register" hexmask.long.byte 0x4 16.--23. 1. "RD_CNT,This field is decremented each time a byte is copied from DATA to the SMBus Slave Receive Buffer Register." hexmask.long.byte 0x4 8.--15. 1. "WR_CNT,This field is set to the number of bytes software expects to send to the Master." newline bitfld.long 0x4 2. "PEC,If Slave_WriteCount is 0 and Slave_PEC is 1 when the Master requests data the PEC Register is copied to the DATA register. After the PEC Register is copied to the SMBus the PEC Register is cleared and Slave_PEC is set to 0." "0,1" bitfld.long 0x4 1. "SPROCEED,When this bit is 0 the Slave State Machine does not transition out of the IDLE REPEAT_START_WRITE or REPEAT_START_READ states. When this bit is 1 the Slave State Machine immediately transitions to the START_WAIT RECEIVE and TRANSMIT states .." "0,1" newline bitfld.long 0x4 0. "SRUN,Setting this bit to 1 enables the Slave State Machine to operate." "0,1" line.long 0x8 "PEC,Packet Error Check (PEC) Register" hexmask.long.byte 0x8 0.--7. 1. "PEC,The SMBus Packet Error Check (PEC) byte." line.long 0xC "RSHTM,Repeated Start Hold Time Register" hexmask.long.byte 0xC 0.--7. 1. "RSHTM,This is the value of the timing requirement tHd:Sta in the I2C specification for a repeated START bit. This is used to hold the clock until the Hold Time for the repeated Start Bit has been satisfied." rgroup.long 0x1C++0x3 line.long 0x0 "EXTND_LEN,Extended Length Register" hexmask.long.byte 0x0 0.--7. 1. "EXTND_LEN,Extended Length Register adds 8 MSB bits to the SMBUS Master/Slave Tx/Rx Length fields." group.long 0x20++0xF line.long 0x0 "COMPL,Completion Register" bitfld.long 0x0 31. "SDONE,If this bit is 1 Slave State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect.(R/WC)" "0,1" bitfld.long 0x0 30. "MDONE,If this bit is 1 Master State machine completed operation and returned to the Idle state. It is cleared when written with a 1. Writes of a 0 have no effect. (R/WC)" "0,1" newline bitfld.long 0x0 29. "IDLE,This bit is set when the I2C bus becomes idle (on the rising edge of nBB). (R/WC)" "0,1" bitfld.long 0x0 25. "MTR,0: Master has just finished the receive phase of a transaction. 1: Master has just finished the transmit phase of a transaction." "0: Master has just finished the receive phase of a..,1: Master has just finished the transmit phase of a.." newline bitfld.long 0x0 24. "MNAKX,If this bit is 1 the Master state machine received a NACK from the receiving Slave while the Master was transmitting data over the SMBus interface. (R/WC)" "0,1" bitfld.long 0x0 21. "REP_WR,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 0 indicating that the Master requested a Write operation." "0,1" newline bitfld.long 0x0 20. "REP_RD,If this bit is 1 the Slave State Machine stopped because it detected a Repeat Start bit with bit[0] of the byte containing the slave address equal to 1 indicating that the Master requested a Read operation." "0,1" bitfld.long 0x0 19. "SPROT,If this bit is 1 the WriteCount[7:0] counter in the Slave state machine either counted down to 0 before the Master sent a NACK signal or the Slave received a NACK signal before the counter reached 0." "0,1" newline bitfld.long 0x0 17. "STR,0: Slave has just finished the receive phase of a transaction. 1: Slave has just finished the transmit phase of a transaction." "0: Slave has just finished the receive phase of a..,1: Slave has just finished the transmit phase of a.." bitfld.long 0x0 16. "SNAKR,If this bit is 1 the Slave state machine sent a NACK to the transmitting Master while the Slave was receiving data from the SMBus interface." "0,1" newline bitfld.long 0x0 14. "LAB,If this bit is 1 the LAB bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" bitfld.long 0x0 13. "BER,If this bit is 1 the BER bit in the Status register was set while either the Slave state machine or the Master state machine was not in the Idle state.(R/WC)" "0,1" newline bitfld.long 0x0 12. "CHDH,CHDH is the bus idle time-out detect bit(R/WC)" "0,1" bitfld.long 0x0 11. "CHDL,CHDL is the clock high time-out detect bit(R/WC)" "0,1" newline bitfld.long 0x0 10. "SCTO,SCTO is the Slave Cumulative Time-out bit(R/WC)" "0,1" bitfld.long 0x0 9. "MCTO,MCTO is the Master Cumulative Time-out bit. (R/WC)" "0,1" newline bitfld.long 0x0 8. "DTO,DTO is the Device Time-out bit. (R/WC)" "0,1" bitfld.long 0x0 6. "TIMERR,The Time-out Error Detected bit (TIMERR) is asserted ('1') whenever any of the enabled time-out error detect status bits (CHDH CHDL SCTO MCTO and DTO) are asserted." "0,1" newline bitfld.long 0x0 5. "BIDEN,When BIDEN is asserted ('1') Bus Idle Detect Time-Out checking is enabled. When BIDEN is not asserted ('0') Bus Idle Detect Time-Out checking is disabled." "0,1" bitfld.long 0x0 4. "SCEN,When SCEN is asserted ('1') Slave Cumulative Time-Out checking is enabled. When SCEN is not asserted ('0') Slave Cumulative Time-Out checking is disabled." "0,1" newline bitfld.long 0x0 3. "MCEN,When MCEN is asserted ('1') Master Cumulative Time-Out checking is enabled. When MCEN is not asserted ('0') Master Cumulative Time-Out checking is disabled." "0,1" bitfld.long 0x0 2. "DTEN,When DTEN is asserted ('1') Device Time-out checking is enabled. When DTEN is not asserted ('0') Device Time-out checking is disabled." "0,1" line.long 0x4 "IDLSC,Idle Scaling Register" hexmask.long.word 0x4 16.--27. 1. "FAIR_IDL_DLY,This field defines the number of ticks of the baud clock required to program the delay. The default value for this field sets the delay period to 32us which is the appropriate value for a 100 KHz bus" hexmask.long.word 0x4 0.--11. 1. "FAIR_BUS_IDL_MIN,This field defines the number of ticks of the baud clock required to satisfy the fairness protocol. The default value for this field sets the idle window to 31us which is the appropriate value for a 100 KHz bus" line.long 0x8 "CFG,Configuration Register" bitfld.long 0x8 31. "ENSI,If this bit is 1 the Slave Done interrupt is enabled. If this bit is 0 the Slave Done interrupt is disabled" "0,1" bitfld.long 0x8 30. "ENMI,If this bit is 1 the Master Done interrupt is enabled. If this bit is 0 the Master Done interrupt is disabled." "0,1" newline bitfld.long 0x8 29. "ENIDI,If this bit is 1 the Idle interrupt is enabled. If this bit is 0 the Idle interrupt is disabled." "0,1" bitfld.long 0x8 28. "EN_AAS,0: Disable the AAS 1: Enable the AAS Interrupt" "0: Disable the AAS,1: Enable the AAS Interrupt" newline bitfld.long 0x8 19. "FLUSH_MRBUF,A write of a 1 to this bit forces the SMBus Master Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 18. "FLUSH_MXBUF,A write of a 1 to this bit forces the SMBus Master Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 17. "FLUSH_SRBUF,A write of a 1 to this bit forces the SMBus Slave Receive Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" bitfld.long 0x8 16. "FLUSH_SXBUF,A write of a 1 to this bit forces the SMBus Slave Transmit Buffer Register to be marked empty. A write of 0 has no effect. This is a self-clearing bit." "0,1" newline bitfld.long 0x8 15. "CFG_PROMIS,This bit define the Mode of SM Bus Controler Mode of operation. 0= Normal Operation. 1= Promiscuous Mode Enable." "0: Normal Operation,1: Promiscuous Mode Enable" bitfld.long 0x8 14. "GC_DIS,This is the General Call Disable bit. 0: the response to the General Call address as a slave is enabled 1: the response to the General Call address as a slave is disabled." "0: the response to the General Call address as a..,1: the response to the General Call address as a.." newline bitfld.long 0x8 13. "TEST0,Must be always written with 0." "0,1" bitfld.long 0x8 12. "FAIR,If this bit is 1 the MCTP Fairness protocol is in effect." "0,1" newline bitfld.long 0x8 11. "DSA,0: Slave Address I2C Compatibility Mode (default). 1: SMBus Address Decode Mode" "0: Slave Address I2C Compatibility Mode,1: SMBus Address Decode Mode" bitfld.long 0x8 10. "EN,When ENAB (Enable) is not asserted ('0') (default) the SMB Controller Core is disabled and in the lowest power consumption state (Disabled State). The ENAB bit must be asserted ('1') for normal operation." "0,1" newline bitfld.long 0x8 9. "RST,When RESET is asserted ('1') all logic and registers except for the RESET bit itself are initialized to the power-on default state." "0,1" bitfld.long 0x8 8. "FEN,Input filtering enable. Input filtering is required by the I2C specification if external filtering is not available. 1=Input filtering is enabled; 0=Input filtering is disabled." "0: Input filtering is disabled,1: Input filtering is enabled" newline bitfld.long 0x8 7. "PECEN,When the PEC Enable bit (PECEN) is asserted ('1') Hardware PEC Support is enabled" "0,1" bitfld.long 0x8 6. "TEST,Must be always written with 0." "0,1" newline bitfld.long 0x8 5. "SLOW_CLK,When this bit is 1 the base period for the Bus Clock Register is multiplied by 4 and thus the frequency is divided by 4." "0,1" bitfld.long 0x8 4. "TCEN,When the Timing Check Enable bit (TCEN) is asserted ('1') Bus Time-Outs are enabled" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "PORT_SEL,The PORT SEL [3:0] bits determine which one of 16 possible bus ports apply to the active 2-wire SDAT and SCLK bus pair." line.long 0xC "BUSCLK,Bus Clock Register" hexmask.long.byte 0xC 8.--15. 1. "HIGH_PER,This field defines the number of I2C Baud Clock periods that make up the high phase of the I2C/SMBus bus clock." hexmask.long.byte 0xC 0.--7. 1. "LOW_PER,This field defines the number of I2C Baud Clock periods that make up the low phase of the I2C/SMBus bus clock." rgroup.byte 0x30++0x0 line.byte 0x0 "BLKID,Block ID Register" hexmask.byte 0x0 0.--7. 1. "ID,Block ID." rgroup.byte 0x34++0x0 line.byte 0x0 "BLKREV,Revision Register" hexmask.byte 0x0 0.--7. 1. "REV,Block Revision Number" group.long 0x38++0x3 line.long 0x0 "BBCTRL,Bit-Bang Control Register" bitfld.long 0x0 6. "BBDATI,Bit-Bang Data In. The BBDATI bit always returns the state of SDAT" "0,1" bitfld.long 0x0 5. "BBCLKI,Bit-Bang Clock In. The BBCLKI bit always returns the state of SCLK." "0,1" newline bitfld.long 0x0 4. "BBDAT,Bit-Bang Data. The BBDAT bit controls the state of SDAT when BBEN = and DADIR = '1'" "0,1" bitfld.long 0x0 3. "BBCLK,Bit-Bang Clock. The BBCLK bit controls the state of SCLK when BBEN = and CLDIR = '1'" "0,1" newline bitfld.long 0x0 2. "DADIR,Bit-Bang Data Direction. The DADIR bit controls the direction of SDAT. 0 - Input. 1 - Output" "0,1" bitfld.long 0x0 1. "CLDIR,Bit-Bang Clock Direction. The CLDIR bit controls the direction of SCLK. 0 - Input 1 - Output" "0,1" newline bitfld.long 0x0 0. "BBEN,Bit-Bang Mode Enable. 0 - Bit Bang Mode Disabled. 1 - Bit Bang Mode Enabled" "0,1" rgroup.byte 0x3C++0x0 line.byte 0x0 "TEST,Test" hexmask.byte 0x0 0.--7. 1. "TEST,This register must not be written or undesirable results may occur." group.long 0x40++0x17 line.long 0x0 "DATATM,Data Timing Register" hexmask.long.byte 0x0 24.--31. 1. "FIRST_START_HOLD,This field determines the SCL hold time following SDA driven low during the first START bit in a transfer. It is the parameter THD:STA in the I2C Specification for an initial START bit. Repeated START hold time is determined by the.." hexmask.long.byte 0x0 16.--23. 1. "STOP_SETUP,The Stop Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a STOP condition." newline hexmask.long.byte 0x0 8.--15. 1. "RESTART_SETUP,The Restart Setup [7:0] timer determines the SDAT setup time from the rising edge of SCLK for a repeated START condition." hexmask.long.byte 0x0 0.--7. 1. "DATA_HOLD,The Data Hold [7:0] timer determines the SDAT hold time following SCLK driven low." line.long 0x4 "TMOUTSC,Time-Out Scaling Register" hexmask.long.byte 0x4 24.--31. 1. "BUS_IDLE_MIN,Bus Idle Minimum time = Bus Idle Min [7:0] x Baud_Clock_Period" hexmask.long.byte 0x4 16.--23. 1. "MAST_CUM_TIM_OUT,Master Cumulative Time-Out duration = Master Cum Time-Out [7:0] x Baud_Clock_Period x 512" newline hexmask.long.byte 0x4 8.--15. 1. "SLV_CUM_TIM_OUT,Slave Cumulative Time-Out duration = Slave Cum Time-Out [7:0] x Baud_Clock_Period x 1024" hexmask.long.byte 0x4 0.--7. 1. "CLK_HIGH_TIM_OUT,Clock High time out period = Clock High Time-Out [7:0] x Baud_Clock_Period x 2" line.long 0x8 "SLV_TXB,SMBus Slave Transmit Buffer Register" hexmask.long.byte 0x8 0.--7. 1. "STXB,SLAVE_TRANSMIT_BUFFER" line.long 0xC "SLV_RXB,SMBus Slave Receive Buffer Register" hexmask.long.byte 0xC 0.--7. 1. "SRXB,SLAVE_RECEIVE_BUFFER" line.long 0x10 "MTR_TXB,SMBus Master Transmit Buffer Register" hexmask.long.byte 0x10 0.--7. 1. "MTXB,MASTER_TRANSMIT_BUFFER" line.long 0x14 "MTR_RXB,SMBus Master Receive Buffer Register" hexmask.long.byte 0x14 0.--7. 1. "MRXB,MASTER_RECEIVE_BUFFER" group.long 0x60++0x7 line.long 0x0 "WAKE_STS,WAKE STATUS Register" bitfld.long 0x0 0. "START_BIT_DET,This bit is set to '1' when a START bit is detected while the controller is enabled. This bit is cleared to '0' when written with a '1'. Writes of '0' have no effect. (R/WC)" "0,1" line.long 0x4 "WAKE_EN,WAKE ENABLE Register" bitfld.long 0x4 0. "START_DET_INT_EN,Enable Start Bit Detection Interrupt. The Start Bit Detection Interrupt is wake-capable. 1=Start Bit Detection Interrupt enabled; 0=Start Bit Detection Interrupt disabled" "0: Start Bit Detection Interrupt disabled,1: Start Bit Detection Interrupt enabled" group.byte 0x6C++0x0 line.byte 0x0 "SLV_ADDR,This is the Slave Address Register" hexmask.byte 0x0 0.--7. 1. "SADDR,This register stores value of address + LSB direction after the 8th clock of the Address Byte." group.byte 0x70++0x0 line.byte 0x0 "PRM_STS,This is the Promiscuous Interrupt Register" bitfld.byte 0x0 0. "ADDR_INTR,This is the Promiscuous Address Status interrupt and is set on the 8th clock of the I2C Address. This bit will hold the Clock line low till this register bit is cleared. This is Write 1 to clear. R/W1C." "0,1" group.byte 0x74++0x0 line.byte 0x0 "PRM_IEN,This is the Promiscuous Interrupt Enable Register" bitfld.byte 0x0 0. "ADDR,This is the Promiscuous interrupt enable register. 1= Interrupt Enable. 0= Interrupt Disabled." "0: Interrupt Disabled,1: Interrupt Enable" group.byte 0x78++0x0 line.byte 0x0 "PRM_CTRL,This is the Promiscuous Control Register" bitfld.byte 0x0 0. "ACK_NAK,This is the Promiscuous ACK / NAK response register. 1= ACK. 0= NAK." "0: NAK,1: ACK" group.byte 0x7C++0x0 line.byte 0x0 "SHDW_DATA,This is the I2C Shadow Data Register" hexmask.byte 0x0 0.--7. 1. "SHDW_DATA,This is the I2C Shadow Data Register" tree.end endif tree.end sif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) tree "SPI_MON (Serial Peripheral Interface Monitor Block)" base ad:0x0 tree "SPI_MON0" base ad:0x40010000 group.long 0x0++0xF line.long 0x0 "MNTR_CTRL,SPI Monitor Control Register" bitfld.long 0x0 21. "TAP_EN,CPTR_CLK_TAP_EN enable the delay taps. It is recommended that a customer set the TAP_EN bit to 1 and the TAP_SEL field to 04h." "0,1" hexmask.long.byte 0x0 16.--20. 1. "TAP_SEL,CPTR_CLK_TAP_SEL selects which 0.5ns delay tap to have the capture clock on. 00h = 0 ns delay (or if TAP_EN = 0). 01h = 0.5ns nom delay; +/- 50% 02h = 1.0ns 03h = 1.5ns 04h = 2.0ns etc. 1Fh = 15.5ns" bitfld.long 0x0 8. "SFT_RST,Soft Reset. This field is auto cleared by hardware. 1= Soft Reset SPI Monitor 0 = No Effect" "0: No Effect,1: Soft Reset SPI Monitor" newline bitfld.long 0x0 1. "LCK_ACT,Lock Activate 1= Activate field Locked 0= Activate field unlocked" "0: Activate field unlocked,1: Activate field Locked" bitfld.long 0x0 0. "ACT,Activate 1= Activate 0= De-activate" "0: De-activate,1: Activate" line.long 0x4 "CFG_STS,SPI Configuration Status Register" bitfld.long 0x4 31. "F1P,Flash 1 Present. 0=Not Present 1=Present" "0: Not Present,1: Present" bitfld.long 0x4 29. "E1W,Enable Wrap Detection. 0=Disable 1=Enable" "0: Disable,1: Enable" hexmask.long.byte 0x4 24.--28. 1. "F1SIZE,Flash 1 Size. Flash sizes are expressed in bytes as a power of 2 matching a Flash Get-ID convention. For the most common cases: 17h = 23d => 2^23 = 8MByte 18h = 24d => 2^24 = 16MByte 19h = 25d => 2^25 = 32MByte 1Ah = 26d =>.." newline bitfld.long 0x4 23. "F0P,Flash 0 Present. 0=Not Present 1=Present" "0: Not Present,1: Present" bitfld.long 0x4 21. "E0W,Enable Wrap Detection. 0=Disable 1=Enable." "0: Disable,1: Enable" hexmask.long.byte 0x4 16.--20. 1. "F0SIZE,Flash 0 Size. Flash sizes are expressed in bytes as a power of 2 matching a Flash Get-ID convention. For the most common cases: 17h = 23d => 2^23 = 8MByte 18h = 24d => 2^24 = 16MByte 19h = 25d => 2^25 = 32MByte 1Ah = 26d =>.." newline bitfld.long 0x4 15. "F1A,Set 3B/4B Address Mode for Flash 1. 0=3B Address Mode 1=4B Address Mode" "0: 3B Address Mode,1: 4B Address Mode" bitfld.long 0x4 14. "F0A,Set 3B/4B Address Mode for Flash 0. 0=3B Address Mode 1=4B Address Mode" "0: 3B Address Mode,1: 4B Address Mode" bitfld.long 0x4 13. "F1F,Enable following of Address Mode. (SPI Snooping) for each Flash. 0=Disable 1=Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 12. "F0F,Enable following of Address Mode. (SPI Snooping) for each Flash. 0=Disable 1=Enable" "0: Disable,1: Enable" bitfld.long 0x4 9.--11. "CSRT,Chip Select Routing. 000 = Both CSn#_In pass directly to CSn# Out both enabled out. 001 = CS1n_In passes to CS1# Output but CS0# Output is disabled (floats high). 010 = CS0n_In passes to CS0# Output but CS1# Output is disabled.." "0: Both CSn#_In pass directly to CSn# Out,1: CS1n_In passes to CS1# Output,?,?,?,?,?,?" bitfld.long 0x4 8. "EQS,Enable Q-Switch (Isolator) to Host. 0 = Disable 1 = Enable." "0: Disable,1: Enable" newline bitfld.long 0x4 7. "XQS,Cross-Over Q-Switch status. (BMC->CPU). RO image of Interbus bit which as 1 overrides EQS bit at both SPI buses without changing their states." "0,1" bitfld.long 0x4 6. "QBD,Quad Bus Disable 1 = Half Bus Mode 0 = IO[3:0] are all controlled by EQS." "0: IO[3:0] are all controlled by EQS,1: Half Bus Mode" hexmask.long.byte 0x4 1.--5. 1. "RST2CSH,RESET# to CS# High Delay. 2^n x 20us 00h=20us 1Fh= 1.3sec. IRQ triggers at this point also." newline bitfld.long 0x4 0. "IMD,Flash Intervention Mode. 0 = Power-Off (POR) 1 = RESET# Pulse" "0: Power-Off,1: RESET# Pulse" line.long 0x8 "SPICFG2,SPI Monitor Configuration 2 Register" bitfld.long 0x8 17. "ALL,ALG Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" bitfld.long 0x8 16. "ALG,Hash Algorithm Mode. 0 = SHA-384 1 = Reserved" "0: SHA-384,1: Reserved" bitfld.long 0x8 13. "RIL,RIV Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" newline bitfld.long 0x8 12. "RIV,Special Region InterVention Mode. If DIV=1 then RIV is ignored. If DIV=0 and RIV=1 then: Reads that are forbidden by the Runtime Region register set are only cancelled by gating off CSn# for that SPI command and setting the IRQ. No.." "0,1" bitfld.long 0x8 9. "DIL,DIV Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" bitfld.long 0x8 8. "DIV,Disable Inter Vention. 1 = IRQ-only Mode." "?,1: IRQ-only Mode" newline bitfld.long 0x8 1. "HRL,HRM Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" bitfld.long 0x8 0. "HRM,Host Reset Mode. 0 = APn_RESET# 1 = Pin." "0: APn_RESET#,1: Pin" line.long 0xC "VIOCTRLSTS,Violation IRQ Control/Status Register" bitfld.long 0xC 13. "EAW,Enable Address Wrap within a Flash device Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 12. "EMT,Enable Timeout in Match Phase Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 11. "ERG,Enable Runtime Region R/W Permission Violation Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 10. "EOB,Enable Out of Bounds Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 9. "EMC,Enable Data Mismatch Violation Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 8. "EOP,Enable Opcode Violation Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 5. "AW,Address Wrap within a Flash device." "0,1" bitfld.long 0xC 4. "MT,Timeout in Match Phase" "0,1" bitfld.long 0xC 3. "RG,Runtime Region R/W Permission Violation" "0,1" newline bitfld.long 0xC 2. "OB,Out of Bounds. Outside all Runtime Regions" "0,1" bitfld.long 0xC 1. "MC,Data Mismatch Violation" "0,1" bitfld.long 0xC 0. "OP,Opcode Violation" "0,1" rgroup.byte 0x10++0x0 line.byte 0x0 "IVN_STS,SPI Intervention Status Register" bitfld.byte 0x0 3. "HIS,Host held Isolated" "0,1" bitfld.byte 0x0 2. "HRS,Host held in Reset" "0,1" bitfld.byte 0x0 1. "FPO,Flash Power or RESET# Activated." "0,1" newline bitfld.byte 0x0 0. "FCS,Flash Chip Selects forced high and bus forced low." "0,1" wgroup.byte 0x11++0x0 line.byte 0x0 "IVN_REC,SPI Intervention Recovery Register" bitfld.byte 0x0 3. "HIC,Write 1 to clear HIS Host held Isolated" "0,1" bitfld.byte 0x0 2. "HRC,Write 1 to clear HRS Host held in Reset" "0,1" bitfld.byte 0x0 1. "FPC,Write 1 to clear FPO Flash Power or RESET# Activated." "0,1" newline bitfld.byte 0x0 0. "FCC,Write 1 to clear FCS Flash Chip Selects forced high and bus forced low." "0,1" group.long 0x14++0x3 line.long 0x0 "VIO_STS,Violation Log Register" hexmask.long.byte 0x0 24.--31. 1. "DAT,SPI Data Byte" hexmask.long.byte 0x0 16.--23. 1. "OPCOD,Flash Opcode" bitfld.long 0x0 15. "CLR,Clear Register RW1C. This bit is auto clearing" "0,1" newline bitfld.long 0x0 14. "AM,Flash Address Mode" "0,1" bitfld.long 0x0 13. "PE,Killed as a Program or Erase" "0,1" bitfld.long 0x0 12. "RD,Killed as a Read" "0,1" newline hexmask.long.byte 0x0 7.--11. 1. "REGION,Region Number" bitfld.long 0x0 6. "DV,Device Number" "0,1" bitfld.long 0x0 5. "AWP,Address Wrap" "0,1" newline bitfld.long 0x0 3. "REG,Runtime Region Violation" "0,1" bitfld.long 0x0 2. "ROB,Region Failure Out of Bounds" "0,1" bitfld.long 0x0 0. "OP,Opcode Violation" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ERR_ADDR,Error Byte Address Register" hexmask.long 0x0 0.--31. 1. "ADDR,Byte address at which the error occurred within the designated Flash" repeat 2. (list 0x0 0x1)(list ad:0x40010020 ad:0x400100A0) tree "FLASH_SET[$1]" base $2 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "OP_PRMT[$1],Permit Address Register" hexmask.long 0x0 0.--31. 1. "PRMT,Permit. Each array organized into 8 32-bit registers set per Flash device. 1 = Permit and if not recognized then ignore. 0 = Kill immediately upon seeing this opcode." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "OP_KILLMD[$1],Kill Address Register" hexmask.long 0x0 0.--31. 1. "KILL,Kill. Each array organized into 8 32-bit registers set per Flash device. 1 = If Killed then kill as a Write: Holding CS# low. 0 = If Killed then kill as a Read: Force CS# high first." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "OP_WPROT[$1],Write Protect Address Register" hexmask.long 0x0 0.--31. 1. "WPROT,Write Protect. Each array organized into 8 32-bit registers set per Flash device. 1 = Make the corresponding bits RO in Permit and Killmd regs. 0 = Corresponding bits are R/W." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "OP_LOCK[$1],Lock Address Register" hexmask.long 0x0 0.--31. 1. "LOCK,Lock. Each array organized into 8 32-bit registers set per Flash device. 1 = Make the corresponding bits RO in Permit and Killmd regs overriding the Wprot register. Any 1 bit in this register is locked. 0 = Corresponding bits are R/W or RO .." repeat.end tree.end repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40010120 ad:0x40010128 ad:0x40010130 ad:0x40010138 ad:0x40010140 ad:0x40010148 ad:0x40010150 ad:0x40010158 ad:0x40010160 ad:0x40010168 ad:0x40010170 ad:0x40010178 ad:0x40010180 ad:0x40010188 ad:0x40010190 ad:0x40010198) tree "RN_TM[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "RT_START,Runtime Monitoring Start Register" bitfld.long 0x0 31. "EN,Enable Register Pair for Monitoring. 0 = No 1 = Yes" "0: No,1: Yes" bitfld.long 0x0 29. "WR,Write Allowed for Region. 0 = No 1 = Yes" "0: No,1: Yes" bitfld.long 0x0 28. "RD,Read Allowed for Region. 0 = No 1 = Yes" "0: No,1: Yes" bitfld.long 0x0 27. "DV,Flash Device 0 = CS0# 1 = CS1#." "0: CS0#,1: CS1#" bitfld.long 0x0 25. "E64,Enable 64KByte Erase opcode for this region. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0x0 24. "E32,Enable 32KByte Erase opcode for this region. 0 = Disable 1 = Enable" "0: Disable,1: Enable" hexmask.long.tbyte 0x0 0.--19. 1. "STRT,A Flash address shifted by 12 (4K byte units). Bottom 12 address bits are 000h" line.long 0x4 "RT_LIMIT,Runtime Monitoring Limit Register" hexmask.long.tbyte 0x4 0.--19. 1. "LMT,Limit Register" tree.end repeat.end base ad:0x40010000 newline group.long 0x1D0++0xB line.long 0x0 "MTMON_CTRLSTS,Match Monitor Control/Status Register" bitfld.long 0x0 24. "CLR_FIFO,Clear FIFO. This field is autocleared by hardware" "0,1" bitfld.long 0x0 19. "FIFO_UDRF,FIFO Underflow" "0,1" bitfld.long 0x0 18. "FIFO_OVRF,FIFO Overflow" "0,1" newline bitfld.long 0x0 17. "FIFO_FUL,FIFO Full" "0,1" bitfld.long 0x0 16. "FIFO_MTY,FIFO Empty" "0,1" bitfld.long 0x0 10. "AM_IRQ,Enable 3B/4B Address Mode switch on either Flash Interrupt" "0,1" newline bitfld.long 0x0 9. "EF_IRQ,Enable First Fetch in any Match region Interrupt" "0,1" bitfld.long 0x0 8. "ET_IRQ,Enable Timeout Interrupt" "0,1" bitfld.long 0x0 2. "AM,Set to 1 on a 3B/4B Address Mode switch on either Flash." "0,1" newline bitfld.long 0x0 1. "F,First Fetch in any Match region" "0,1" bitfld.long 0x0 0. "T,Timeout" "0,1" line.long 0x4 "MTMON_ENMD,Match Monitor Enable/Mode Register" bitfld.long 0x4 8. "MON_MS,Match Pattern Source Mode: 0 = SRAM 1 = Internal Flash." "0: SRAM,1: Internal Flash" bitfld.long 0x4 0. "MON_EN,Enable Data Matching. 0 = Disabled 1 = Enabled" "0: Disabled,1: Enabled" line.long 0x8 "MTMON_TCTRL,Match Fetch Timeout Control Register" bitfld.long 0x8 21.--22. "TU,Timeout Unit 00 = none (off) 01 = 32ms 10 = 128ms 11 = 1sec" "0: none,1: 32ms,?,?" hexmask.long.byte 0x8 16.--20. 1. "TV,Timeout Value 0 to 32" bitfld.long 0x8 0. "ST,Start Timeout Counter" "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x400101E0 ad:0x400101EC ad:0x400101F8 ad:0x40010204 ad:0x40010210 ad:0x4001021C ad:0x40010228 ad:0x40010234) tree "MT_MON[$1]" base $2 group.long ($2)++0xB line.long 0x0 "MTMON_BEGIN,Match Monitor Region Begin Register" bitfld.long 0x0 31. "DV,Flash Device number applying to both Begin and End fields 0 = CS0# 1 = CS1#" "0: CS0#,1: CS1#" hexmask.long.tbyte 0x0 0.--18. 1. "BGN,The 19 bits of base address within the designated SPI Flash specifying the last aligned 8K block." line.long 0x4 "MTMON_END,Match Monitor Region End Register" hexmask.long.tbyte 0x4 0.--18. 1. "END,The 19 bits of base address within the designated SPI Flash specifying the last aligned 8K block." line.long 0x8 "MAP,Match Monitor Region Map Register" bitfld.long 0x8 31. "ME,Match Enable for individual Region R" "0,1" hexmask.long.tbyte 0x8 0.--18. 1. "MAP,The 19 bits of base address within the designated SPI Flash specifying the last aligned 8K block." tree.end repeat.end base ad:0x40010000 newline group.long 0x240++0x3 line.long 0x0 "MTMON_VIOSTS,Match Monitor Violation Log Register" hexmask.long.byte 0x0 24.--31. 1. "DATA,SPI Data Byte" hexmask.long.byte 0x0 16.--23. 1. "OPCOD,Flash Opcode" bitfld.long 0x0 15. "CLR,Clear Register RW1C. This bit is auto clearing" "0,1" newline bitfld.long 0x0 14. "AM,Flash Address Mode 0 = 3-byte 1 = 4-byte" "0: 3-byte,1: 4-byte" hexmask.long.byte 0x0 7.--11. 1. "RGN,Region. This is read-Only bit. Shows which of 8 Match regions [7:0] got the mismatch." bitfld.long 0x0 6. "DV,Device Number. This is read-Only bit. 0 = CS0 1 = CS1." "0: CS0,1: CS1" newline bitfld.long 0x0 4. "MTO,Match Monitor Timeout. This is read-Only bit." "0,1" rgroup.long 0x244++0x3 line.long 0x0 "MTMON_VIOADDR,Match Monitor Violation Address Register" hexmask.long 0x0 0.--31. 1. "ADDR,Byte address at which the error occurred within the designated Flash" group.long 0x250++0x3 line.long 0x0 "LTMON_AGGR,Loadtime (Hash) IRQ Aggregation Register" bitfld.long 0x0 15. "EN_IRQ7,Enable Load 7 Interrupt" "0,1" bitfld.long 0x0 14. "EN_IRQ6,Enable Load 6 Interrupt" "0,1" bitfld.long 0x0 13. "EN_IRQ5,Enable Load 5 Interrupt" "0,1" newline bitfld.long 0x0 12. "EN_IRQ4,Enable Load 4 Interrupt" "0,1" bitfld.long 0x0 11. "EN_IRQ3,Enable Load 3 Interrupt" "0,1" bitfld.long 0x0 10. "EN_IRQ2,Enable Load 2 Interrupt" "0,1" newline bitfld.long 0x0 9. "EN_IRQ1,Enable Load 1 Interrupt" "0,1" bitfld.long 0x0 8. "EN_IRQ0,Enable Load 0 Interrupt" "0,1" bitfld.long 0x0 7. "IRQ7,Load 7 Interrupt" "0,1" newline bitfld.long 0x0 6. "IRQ6,Load 6 Interrupt" "0,1" bitfld.long 0x0 5. "IRQ5,Load 5 Interrupt" "0,1" bitfld.long 0x0 4. "IRQ4,Load 4 Interrupt" "0,1" newline bitfld.long 0x0 3. "IRQ3,Load 3 Interrupt" "0,1" bitfld.long 0x0 2. "IRQ2,Load 2 Interrupt" "0,1" bitfld.long 0x0 1. "IRQ1,Load 1 Interrupt" "0,1" newline bitfld.long 0x0 0. "IRQ0,Load 0 Interrupt" "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40010254 ad:0x4001026C ad:0x40010284 ad:0x4001029C ad:0x400102B4 ad:0x400102CC ad:0x400102E4 ad:0x400102FC) tree "LT_MON[$1]" base $2 group.long ($2)++0xF line.long 0x0 "LM_CTRLSTS,Loadtime Monitor Control/Status Register" bitfld.long 0x0 11. "F_INTEN,Enable Finalized and result ready Interrupt" "0,1" bitfld.long 0x0 10. "E_INTEN,Enable End Byte seen Interrupt" "0,1" bitfld.long 0x0 9. "B_INTEN,Enable Begin Byte seen Interrupt" "0,1" bitfld.long 0x0 8. "W_INTEN,Enable Waiting Interrupt" "0,1" bitfld.long 0x0 3. "F,Finalized and result ready" "0,1" bitfld.long 0x0 2. "E,End Byte seen" "0,1" bitfld.long 0x0 1. "B,Begin Byte seen" "0,1" bitfld.long 0x0 0. "W,Waiting" "0,1" line.long 0x4 "LM_CHN_CTRL,Loadtime Monitor Channel Control Register" hexmask.long.byte 0x4 8.--11. 1. "FPTR,FPTR: Result FIFO pointer. In 32Bit. Ranges: 0 to 11 for SHA-384 result 0 to 7 for SHA-256 result" bitfld.long 0x4 2. "RSF,RSF: Reset just Result FIFO pointer when this bit is set to 1" "0,1" bitfld.long 0x4 1. "RST,RST: Stop and Reset calculation for this channel when set to 1" "0,1" bitfld.long 0x4 0. "GO,GO: Run the Load Monitor for this channel" "0,1" line.long 0x8 "LM_BEGIN,Loadtime Monitor Channel Begin Register" bitfld.long 0x8 31. "DV,Flash Device number applying to both Begin and End fields. 0 = CS0# 1 = CS1#" "0: CS0#,1: CS1#" hexmask.long 0x8 0.--30. 1. "BADDR,A byte address within the designated Flash specifying the first byte of the load image." line.long 0xC "LM_END,Loadtime Monitor Channel End Register" hexmask.long 0xC 0.--31. 1. "EADDR,A byte address within the designated Flash specifying the last byte of the load image." rgroup.long ($2+0x10)++0x7 line.long 0x0 "LM_COUNT,Loadtime Monitor Channel Count Register" hexmask.long 0x0 0.--31. 1. "CNT,A Read-Only count of bytes processed." line.long 0x4 "LM_DIGEST,Loadtime Monitor Channel Digest Register" hexmask.long 0x4 0.--31. 1. "DGST,A Read-Only FIFO Portal to Hash digest result. 12 or 8 Dwords depending on algorithm." tree.end repeat.end base ad:0x40010000 newline group.long 0x314++0x3 line.long 0x0 "LTMON_CTRLSTS,Load Monitor Control/Status Register" bitfld.long 0x0 8. "CLR_FIFO,Clear FIFO" "0,1" bitfld.long 0x0 3. "FIFO_UDRF,FIFO Underflow" "0,1" bitfld.long 0x0 2. "FIFO_OVRF,FIFO Overflow" "0,1" newline bitfld.long 0x0 1. "FIFO_FUL,FIFO Full" "0,1" bitfld.long 0x0 0. "FIFO_MTY,FIFO Empty" "0,1" tree.end tree "SPI_MON1" base ad:0x40010400 group.long 0x0++0xF line.long 0x0 "MNTR_CTRL,SPI Monitor Control Register" bitfld.long 0x0 21. "TAP_EN,CPTR_CLK_TAP_EN enable the delay taps. It is recommended that a customer set the TAP_EN bit to 1 and the TAP_SEL field to 04h." "0,1" hexmask.long.byte 0x0 16.--20. 1. "TAP_SEL,CPTR_CLK_TAP_SEL selects which 0.5ns delay tap to have the capture clock on. 00h = 0 ns delay (or if TAP_EN = 0). 01h = 0.5ns nom delay; +/- 50% 02h = 1.0ns 03h = 1.5ns 04h = 2.0ns etc. 1Fh = 15.5ns" bitfld.long 0x0 8. "SFT_RST,Soft Reset. This field is auto cleared by hardware. 1= Soft Reset SPI Monitor 0 = No Effect" "0: No Effect,1: Soft Reset SPI Monitor" newline bitfld.long 0x0 1. "LCK_ACT,Lock Activate 1= Activate field Locked 0= Activate field unlocked" "0: Activate field unlocked,1: Activate field Locked" bitfld.long 0x0 0. "ACT,Activate 1= Activate 0= De-activate" "0: De-activate,1: Activate" line.long 0x4 "CFG_STS,SPI Configuration Status Register" bitfld.long 0x4 31. "F1P,Flash 1 Present. 0=Not Present 1=Present" "0: Not Present,1: Present" bitfld.long 0x4 29. "E1W,Enable Wrap Detection. 0=Disable 1=Enable" "0: Disable,1: Enable" hexmask.long.byte 0x4 24.--28. 1. "F1SIZE,Flash 1 Size. Flash sizes are expressed in bytes as a power of 2 matching a Flash Get-ID convention. For the most common cases: 17h = 23d => 2^23 = 8MByte 18h = 24d => 2^24 = 16MByte 19h = 25d => 2^25 = 32MByte 1Ah = 26d =>.." newline bitfld.long 0x4 23. "F0P,Flash 0 Present. 0=Not Present 1=Present" "0: Not Present,1: Present" bitfld.long 0x4 21. "E0W,Enable Wrap Detection. 0=Disable 1=Enable." "0: Disable,1: Enable" hexmask.long.byte 0x4 16.--20. 1. "F0SIZE,Flash 0 Size. Flash sizes are expressed in bytes as a power of 2 matching a Flash Get-ID convention. For the most common cases: 17h = 23d => 2^23 = 8MByte 18h = 24d => 2^24 = 16MByte 19h = 25d => 2^25 = 32MByte 1Ah = 26d =>.." newline bitfld.long 0x4 15. "F1A,Set 3B/4B Address Mode for Flash 1. 0=3B Address Mode 1=4B Address Mode" "0: 3B Address Mode,1: 4B Address Mode" bitfld.long 0x4 14. "F0A,Set 3B/4B Address Mode for Flash 0. 0=3B Address Mode 1=4B Address Mode" "0: 3B Address Mode,1: 4B Address Mode" bitfld.long 0x4 13. "F1F,Enable following of Address Mode. (SPI Snooping) for each Flash. 0=Disable 1=Enable" "0: Disable,1: Enable" newline bitfld.long 0x4 12. "F0F,Enable following of Address Mode. (SPI Snooping) for each Flash. 0=Disable 1=Enable" "0: Disable,1: Enable" bitfld.long 0x4 9.--11. "CSRT,Chip Select Routing. 000 = Both CSn#_In pass directly to CSn# Out both enabled out. 001 = CS1n_In passes to CS1# Output but CS0# Output is disabled (floats high). 010 = CS0n_In passes to CS0# Output but CS1# Output is disabled.." "0: Both CSn#_In pass directly to CSn# Out,1: CS1n_In passes to CS1# Output,?,?,?,?,?,?" bitfld.long 0x4 8. "EQS,Enable Q-Switch (Isolator) to Host. 0 = Disable 1 = Enable." "0: Disable,1: Enable" newline bitfld.long 0x4 7. "XQS,Cross-Over Q-Switch status. (BMC->CPU). RO image of Interbus bit which as 1 overrides EQS bit at both SPI buses without changing their states." "0,1" bitfld.long 0x4 6. "QBD,Quad Bus Disable 1 = Half Bus Mode 0 = IO[3:0] are all controlled by EQS." "0: IO[3:0] are all controlled by EQS,1: Half Bus Mode" hexmask.long.byte 0x4 1.--5. 1. "RST2CSH,RESET# to CS# High Delay. 2^n x 20us 00h=20us 1Fh= 1.3sec. IRQ triggers at this point also." newline bitfld.long 0x4 0. "IMD,Flash Intervention Mode. 0 = Power-Off (POR) 1 = RESET# Pulse" "0: Power-Off,1: RESET# Pulse" line.long 0x8 "SPICFG2,SPI Monitor Configuration 2 Register" bitfld.long 0x8 17. "ALL,ALG Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" bitfld.long 0x8 16. "ALG,Hash Algorithm Mode. 0 = SHA-384 1 = Reserved" "0: SHA-384,1: Reserved" bitfld.long 0x8 13. "RIL,RIV Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" newline bitfld.long 0x8 12. "RIV,Special Region InterVention Mode. If DIV=1 then RIV is ignored. If DIV=0 and RIV=1 then: Reads that are forbidden by the Runtime Region register set are only cancelled by gating off CSn# for that SPI command and setting the IRQ. No.." "0,1" bitfld.long 0x8 9. "DIL,DIV Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" bitfld.long 0x8 8. "DIV,Disable Inter Vention. 1 = IRQ-only Mode." "?,1: IRQ-only Mode" newline bitfld.long 0x8 1. "HRL,HRM Bit Lock. 0 = Unlocked 1 = Locked." "0: Unlocked,1: Locked" bitfld.long 0x8 0. "HRM,Host Reset Mode. 0 = APn_RESET# 1 = Pin." "0: APn_RESET#,1: Pin" line.long 0xC "VIOCTRLSTS,Violation IRQ Control/Status Register" bitfld.long 0xC 13. "EAW,Enable Address Wrap within a Flash device Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 12. "EMT,Enable Timeout in Match Phase Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 11. "ERG,Enable Runtime Region R/W Permission Violation Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 10. "EOB,Enable Out of Bounds Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 9. "EMC,Enable Data Mismatch Violation Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0xC 8. "EOP,Enable Opcode Violation Interrupt. 0 = Disable 1 = Enable" "0: Disable,1: Enable" newline bitfld.long 0xC 5. "AW,Address Wrap within a Flash device." "0,1" bitfld.long 0xC 4. "MT,Timeout in Match Phase" "0,1" bitfld.long 0xC 3. "RG,Runtime Region R/W Permission Violation" "0,1" newline bitfld.long 0xC 2. "OB,Out of Bounds. Outside all Runtime Regions" "0,1" bitfld.long 0xC 1. "MC,Data Mismatch Violation" "0,1" bitfld.long 0xC 0. "OP,Opcode Violation" "0,1" rgroup.byte 0x10++0x0 line.byte 0x0 "IVN_STS,SPI Intervention Status Register" bitfld.byte 0x0 3. "HIS,Host held Isolated" "0,1" bitfld.byte 0x0 2. "HRS,Host held in Reset" "0,1" bitfld.byte 0x0 1. "FPO,Flash Power or RESET# Activated." "0,1" newline bitfld.byte 0x0 0. "FCS,Flash Chip Selects forced high and bus forced low." "0,1" wgroup.byte 0x11++0x0 line.byte 0x0 "IVN_REC,SPI Intervention Recovery Register" bitfld.byte 0x0 3. "HIC,Write 1 to clear HIS Host held Isolated" "0,1" bitfld.byte 0x0 2. "HRC,Write 1 to clear HRS Host held in Reset" "0,1" bitfld.byte 0x0 1. "FPC,Write 1 to clear FPO Flash Power or RESET# Activated." "0,1" newline bitfld.byte 0x0 0. "FCC,Write 1 to clear FCS Flash Chip Selects forced high and bus forced low." "0,1" group.long 0x14++0x3 line.long 0x0 "VIO_STS,Violation Log Register" hexmask.long.byte 0x0 24.--31. 1. "DAT,SPI Data Byte" hexmask.long.byte 0x0 16.--23. 1. "OPCOD,Flash Opcode" bitfld.long 0x0 15. "CLR,Clear Register RW1C. This bit is auto clearing" "0,1" newline bitfld.long 0x0 14. "AM,Flash Address Mode" "0,1" bitfld.long 0x0 13. "PE,Killed as a Program or Erase" "0,1" bitfld.long 0x0 12. "RD,Killed as a Read" "0,1" newline hexmask.long.byte 0x0 7.--11. 1. "REGION,Region Number" bitfld.long 0x0 6. "DV,Device Number" "0,1" bitfld.long 0x0 5. "AWP,Address Wrap" "0,1" newline bitfld.long 0x0 3. "REG,Runtime Region Violation" "0,1" bitfld.long 0x0 2. "ROB,Region Failure Out of Bounds" "0,1" bitfld.long 0x0 0. "OP,Opcode Violation" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "ERR_ADDR,Error Byte Address Register" hexmask.long 0x0 0.--31. 1. "ADDR,Byte address at which the error occurred within the designated Flash" repeat 2. (list 0x0 0x1)(list ad:0x40010420 ad:0x400104A0) tree "FLASH_SET[$1]" base $2 repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "OP_PRMT[$1],Permit Address Register" hexmask.long 0x0 0.--31. 1. "PRMT,Permit. Each array organized into 8 32-bit registers set per Flash device. 1 = Permit and if not recognized then ignore. 0 = Kill immediately upon seeing this opcode." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x20)++0x3 line.long 0x0 "OP_KILLMD[$1],Kill Address Register" hexmask.long 0x0 0.--31. 1. "KILL,Kill. Each array organized into 8 32-bit registers set per Flash device. 1 = If Killed then kill as a Write: Holding CS# low. 0 = If Killed then kill as a Read: Force CS# high first." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "OP_WPROT[$1],Write Protect Address Register" hexmask.long 0x0 0.--31. 1. "WPROT,Write Protect. Each array organized into 8 32-bit registers set per Flash device. 1 = Make the corresponding bits RO in Permit and Killmd regs. 0 = Corresponding bits are R/W." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x60)++0x3 line.long 0x0 "OP_LOCK[$1],Lock Address Register" hexmask.long 0x0 0.--31. 1. "LOCK,Lock. Each array organized into 8 32-bit registers set per Flash device. 1 = Make the corresponding bits RO in Permit and Killmd regs overriding the Wprot register. Any 1 bit in this register is locked. 0 = Corresponding bits are R/W or RO .." repeat.end tree.end repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40010520 ad:0x40010528 ad:0x40010530 ad:0x40010538 ad:0x40010540 ad:0x40010548 ad:0x40010550 ad:0x40010558 ad:0x40010560 ad:0x40010568 ad:0x40010570 ad:0x40010578 ad:0x40010580 ad:0x40010588 ad:0x40010590 ad:0x40010598) tree "RN_TM[$1]" base $2 group.long ($2)++0x7 line.long 0x0 "RT_START,Runtime Monitoring Start Register" bitfld.long 0x0 31. "EN,Enable Register Pair for Monitoring. 0 = No 1 = Yes" "0: No,1: Yes" bitfld.long 0x0 29. "WR,Write Allowed for Region. 0 = No 1 = Yes" "0: No,1: Yes" bitfld.long 0x0 28. "RD,Read Allowed for Region. 0 = No 1 = Yes" "0: No,1: Yes" bitfld.long 0x0 27. "DV,Flash Device 0 = CS0# 1 = CS1#." "0: CS0#,1: CS1#" bitfld.long 0x0 25. "E64,Enable 64KByte Erase opcode for this region. 0 = Disable 1 = Enable" "0: Disable,1: Enable" bitfld.long 0x0 24. "E32,Enable 32KByte Erase opcode for this region. 0 = Disable 1 = Enable" "0: Disable,1: Enable" hexmask.long.tbyte 0x0 0.--19. 1. "STRT,A Flash address shifted by 12 (4K byte units). Bottom 12 address bits are 000h" line.long 0x4 "RT_LIMIT,Runtime Monitoring Limit Register" hexmask.long.tbyte 0x4 0.--19. 1. "LMT,Limit Register" tree.end repeat.end base ad:0x40010400 newline group.long 0x1D0++0xB line.long 0x0 "MTMON_CTRLSTS,Match Monitor Control/Status Register" bitfld.long 0x0 24. "CLR_FIFO,Clear FIFO. This field is autocleared by hardware" "0,1" bitfld.long 0x0 19. "FIFO_UDRF,FIFO Underflow" "0,1" bitfld.long 0x0 18. "FIFO_OVRF,FIFO Overflow" "0,1" newline bitfld.long 0x0 17. "FIFO_FUL,FIFO Full" "0,1" bitfld.long 0x0 16. "FIFO_MTY,FIFO Empty" "0,1" bitfld.long 0x0 10. "AM_IRQ,Enable 3B/4B Address Mode switch on either Flash Interrupt" "0,1" newline bitfld.long 0x0 9. "EF_IRQ,Enable First Fetch in any Match region Interrupt" "0,1" bitfld.long 0x0 8. "ET_IRQ,Enable Timeout Interrupt" "0,1" bitfld.long 0x0 2. "AM,Set to 1 on a 3B/4B Address Mode switch on either Flash." "0,1" newline bitfld.long 0x0 1. "F,First Fetch in any Match region" "0,1" bitfld.long 0x0 0. "T,Timeout" "0,1" line.long 0x4 "MTMON_ENMD,Match Monitor Enable/Mode Register" bitfld.long 0x4 8. "MON_MS,Match Pattern Source Mode: 0 = SRAM 1 = Internal Flash." "0: SRAM,1: Internal Flash" bitfld.long 0x4 0. "MON_EN,Enable Data Matching. 0 = Disabled 1 = Enabled" "0: Disabled,1: Enabled" line.long 0x8 "MTMON_TCTRL,Match Fetch Timeout Control Register" bitfld.long 0x8 21.--22. "TU,Timeout Unit 00 = none (off) 01 = 32ms 10 = 128ms 11 = 1sec" "0: none,1: 32ms,?,?" hexmask.long.byte 0x8 16.--20. 1. "TV,Timeout Value 0 to 32" bitfld.long 0x8 0. "ST,Start Timeout Counter" "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x400105E0 ad:0x400105EC ad:0x400105F8 ad:0x40010604 ad:0x40010610 ad:0x4001061C ad:0x40010628 ad:0x40010634) tree "MT_MON[$1]" base $2 group.long ($2)++0xB line.long 0x0 "MTMON_BEGIN,Match Monitor Region Begin Register" bitfld.long 0x0 31. "DV,Flash Device number applying to both Begin and End fields 0 = CS0# 1 = CS1#" "0: CS0#,1: CS1#" hexmask.long.tbyte 0x0 0.--18. 1. "BGN,The 19 bits of base address within the designated SPI Flash specifying the last aligned 8K block." line.long 0x4 "MTMON_END,Match Monitor Region End Register" hexmask.long.tbyte 0x4 0.--18. 1. "END,The 19 bits of base address within the designated SPI Flash specifying the last aligned 8K block." line.long 0x8 "MAP,Match Monitor Region Map Register" bitfld.long 0x8 31. "ME,Match Enable for individual Region R" "0,1" hexmask.long.tbyte 0x8 0.--18. 1. "MAP,The 19 bits of base address within the designated SPI Flash specifying the last aligned 8K block." tree.end repeat.end base ad:0x40010400 newline group.long 0x240++0x3 line.long 0x0 "MTMON_VIOSTS,Match Monitor Violation Log Register" hexmask.long.byte 0x0 24.--31. 1. "DATA,SPI Data Byte" hexmask.long.byte 0x0 16.--23. 1. "OPCOD,Flash Opcode" bitfld.long 0x0 15. "CLR,Clear Register RW1C. This bit is auto clearing" "0,1" newline bitfld.long 0x0 14. "AM,Flash Address Mode 0 = 3-byte 1 = 4-byte" "0: 3-byte,1: 4-byte" hexmask.long.byte 0x0 7.--11. 1. "RGN,Region. This is read-Only bit. Shows which of 8 Match regions [7:0] got the mismatch." bitfld.long 0x0 6. "DV,Device Number. This is read-Only bit. 0 = CS0 1 = CS1." "0: CS0,1: CS1" newline bitfld.long 0x0 4. "MTO,Match Monitor Timeout. This is read-Only bit." "0,1" rgroup.long 0x244++0x3 line.long 0x0 "MTMON_VIOADDR,Match Monitor Violation Address Register" hexmask.long 0x0 0.--31. 1. "ADDR,Byte address at which the error occurred within the designated Flash" group.long 0x250++0x3 line.long 0x0 "LTMON_AGGR,Loadtime (Hash) IRQ Aggregation Register" bitfld.long 0x0 15. "EN_IRQ7,Enable Load 7 Interrupt" "0,1" bitfld.long 0x0 14. "EN_IRQ6,Enable Load 6 Interrupt" "0,1" bitfld.long 0x0 13. "EN_IRQ5,Enable Load 5 Interrupt" "0,1" newline bitfld.long 0x0 12. "EN_IRQ4,Enable Load 4 Interrupt" "0,1" bitfld.long 0x0 11. "EN_IRQ3,Enable Load 3 Interrupt" "0,1" bitfld.long 0x0 10. "EN_IRQ2,Enable Load 2 Interrupt" "0,1" newline bitfld.long 0x0 9. "EN_IRQ1,Enable Load 1 Interrupt" "0,1" bitfld.long 0x0 8. "EN_IRQ0,Enable Load 0 Interrupt" "0,1" bitfld.long 0x0 7. "IRQ7,Load 7 Interrupt" "0,1" newline bitfld.long 0x0 6. "IRQ6,Load 6 Interrupt" "0,1" bitfld.long 0x0 5. "IRQ5,Load 5 Interrupt" "0,1" bitfld.long 0x0 4. "IRQ4,Load 4 Interrupt" "0,1" newline bitfld.long 0x0 3. "IRQ3,Load 3 Interrupt" "0,1" bitfld.long 0x0 2. "IRQ2,Load 2 Interrupt" "0,1" bitfld.long 0x0 1. "IRQ1,Load 1 Interrupt" "0,1" newline bitfld.long 0x0 0. "IRQ0,Load 0 Interrupt" "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40010654 ad:0x4001066C ad:0x40010684 ad:0x4001069C ad:0x400106B4 ad:0x400106CC ad:0x400106E4 ad:0x400106FC) tree "LT_MON[$1]" base $2 group.long ($2)++0xF line.long 0x0 "LM_CTRLSTS,Loadtime Monitor Control/Status Register" bitfld.long 0x0 11. "F_INTEN,Enable Finalized and result ready Interrupt" "0,1" bitfld.long 0x0 10. "E_INTEN,Enable End Byte seen Interrupt" "0,1" bitfld.long 0x0 9. "B_INTEN,Enable Begin Byte seen Interrupt" "0,1" bitfld.long 0x0 8. "W_INTEN,Enable Waiting Interrupt" "0,1" bitfld.long 0x0 3. "F,Finalized and result ready" "0,1" bitfld.long 0x0 2. "E,End Byte seen" "0,1" bitfld.long 0x0 1. "B,Begin Byte seen" "0,1" bitfld.long 0x0 0. "W,Waiting" "0,1" line.long 0x4 "LM_CHN_CTRL,Loadtime Monitor Channel Control Register" hexmask.long.byte 0x4 8.--11. 1. "FPTR,FPTR: Result FIFO pointer. In 32Bit. Ranges: 0 to 11 for SHA-384 result 0 to 7 for SHA-256 result" bitfld.long 0x4 2. "RSF,RSF: Reset just Result FIFO pointer when this bit is set to 1" "0,1" bitfld.long 0x4 1. "RST,RST: Stop and Reset calculation for this channel when set to 1" "0,1" bitfld.long 0x4 0. "GO,GO: Run the Load Monitor for this channel" "0,1" line.long 0x8 "LM_BEGIN,Loadtime Monitor Channel Begin Register" bitfld.long 0x8 31. "DV,Flash Device number applying to both Begin and End fields. 0 = CS0# 1 = CS1#" "0: CS0#,1: CS1#" hexmask.long 0x8 0.--30. 1. "BADDR,A byte address within the designated Flash specifying the first byte of the load image." line.long 0xC "LM_END,Loadtime Monitor Channel End Register" hexmask.long 0xC 0.--31. 1. "EADDR,A byte address within the designated Flash specifying the last byte of the load image." rgroup.long ($2+0x10)++0x7 line.long 0x0 "LM_COUNT,Loadtime Monitor Channel Count Register" hexmask.long 0x0 0.--31. 1. "CNT,A Read-Only count of bytes processed." line.long 0x4 "LM_DIGEST,Loadtime Monitor Channel Digest Register" hexmask.long 0x4 0.--31. 1. "DGST,A Read-Only FIFO Portal to Hash digest result. 12 or 8 Dwords depending on algorithm." tree.end repeat.end base ad:0x40010400 newline group.long 0x314++0x3 line.long 0x0 "LTMON_CTRLSTS,Load Monitor Control/Status Register" bitfld.long 0x0 8. "CLR_FIFO,Clear FIFO" "0,1" bitfld.long 0x0 3. "FIFO_UDRF,FIFO Underflow" "0,1" bitfld.long 0x0 2. "FIFO_OVRF,FIFO Overflow" "0,1" newline bitfld.long 0x0 1. "FIFO_FUL,FIFO Full" "0,1" bitfld.long 0x0 0. "FIFO_MTY,FIFO Empty" "0,1" tree.end tree.end tree "SPT (SPI Peripheral Target)" base ad:0x0 tree "SPT0" base ad:0x40007000 group.long 0x0++0x2F line.long 0x0 "SPI_CFG,SPI Peripheral Target Communication Configuration Register." hexmask.long.byte 0x0 16.--23. 1. "WAIT_TIME,These bits set the amount of wait time in cycles before transmitting data back to master. During this wait time status bits will be transmitted" bitfld.long 0x0 8.--10. "TAR_TIM_SEL,Turn Around Time select for Quad wire mode. 0h = 1 cycle. 1h = 2 cycles. 2h = 4 cycles. 3h = 8 cycles. Other values are reserved." "0: 1 cycle,1: 2 cycle,2: 4 cycle,3: 8 cycle,?,?,?,?" bitfld.long 0x0 0. "SNG_QUD_SEL,This field defines the Single / Quad Wire mode of operation for SPI Peripheral Target block. 0 = Single Wire Slave SPI block operation. 1 = Quad Wire Slave SPI block operation." "0: Single Wire Slave SPI block operation,1: Quad Wire Slave SPI block operation" line.long 0x4 "SPI_STS,SPI Peripheral Target Status Register." bitfld.long 0x4 28. "RXF_OVRFLW,If SPI Master writes more than the space in the FIFO the FIFO will flag an overflow error and data will not be stored." "0,1" bitfld.long 0x4 27. "RXF_UNFLW,If the SPI Peripheral Target reads RX FIFO when it is empty RX FIFO Underflow flag will be set. This condition will never happen under normal situation." "0,1" bitfld.long 0x4 26. "TXF_OVRFLW,If Master doesn't read all of the data it requested from the posted read block cycle than data will still be left in the FIFO. This will cause misalignment with the following transactions and a new read cycle can cause overflow." "0,1" newline bitfld.long 0x4 25. "TXF_UNFLW,If Master reads more than what is in FIFO FIFO will flag an underflow error and the data returned will just be the last valid pointer value." "0,1" bitfld.long 0x4 24. "RXF_SIZE_ERR,If size requested is more than what Master provided and the Master terminates early error flag shut down request signal to ARM Bus. Size requested is less than what Master provided -- ignored and continue transaction may be.." "0,1" bitfld.long 0x4 23. "DV_BUSY,If the Master requested a transaction whose destination is busy the request is ignored. Should use the poll or wait for interrupts." "0,1" newline bitfld.long 0x4 22. "UNDEF_CMD_ERR,Undefined Command Error: The command received from the master isn't defined." "0,1" bitfld.long 0x4 21. "ARMBUS_ERR,ARM Bus Error returned for the curren data transfer." "0,1" bitfld.long 0x4 20. "OOL1_ERR,This flag is set with the transfer address requested by the master is out of Limit 1 range or when the BAR is disabled." "0,1" newline bitfld.long 0x4 19. "OOL0_ERR,This flag is set with the transfer address requested by the master is out of Limit 0 range or when the BAR is disabled." "0,1" bitfld.long 0x4 18. "TXF_RST_DN,Set after the SPI Master initiates a TX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" bitfld.long 0x4 17. "RXF_RST_DN,Set after the SPI Master initiates a RX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" newline bitfld.long 0x4 16. "SPIM_RST_REQ,Set when the SPI Master Requested a Configuration Reset." "0,1" bitfld.long 0x4 15. "OBF_FLG,Set when the EC writes to the Output Buffer signaling there is data for the Host to read." "0,1" bitfld.long 0x4 14. "IBF_FLG,Set when the Host writes to the Input Buffer signaling there is data for the EC to read." "0,1" newline bitfld.long 0x4 13. "TMCLK_CNT_ERR,This bit is set when the SPI Clock Count Test Mode is set and there is an uneven amount of clocks." "0,1" bitfld.long 0x4 11. "TXF_FUL,The TX FIFO is full of data that was read from Memory." "0,1" bitfld.long 0x4 10. "TXF_EMP,Signifies SPI Master has read the data requested from Memory. Can be used to show there is data the SPI Master has requested and not been read yet. New read transactions will be aligned." "0,1" newline bitfld.long 0x4 9. "RXF_FUL,The RX FIFO is full of data to be written to Memory." "0,1" bitfld.long 0x4 8. "RXF_EMP,Signifies all Memory write transactions for the SPI Masters requested size have been performed. New transactions are allowed." "0,1" bitfld.long 0x4 6. "POLL_HIGH,If this bit is set then something in the high 16-bit of status register is set and needs to be checked. SPI Master should take action to clear this." "0,1" newline bitfld.long 0x4 5. "SREG_TRANS,When an SREG transaction is currently being processed." "0,1" bitfld.long 0x4 4. "MEM_RD_BUSY,When an Memory Read transaction is currently being processed." "0,1" bitfld.long 0x4 3. "MEM_WR_BUSY,When an Memory Write transaction is currently being processed." "0,1" newline bitfld.long 0x4 1. "MEM_RD_DONE,When the ARM BUS side has fully finished writing the last written DWord to the FIFO for a set of data read from Memory for Posted Reads. - cleared with new Read request." "0,1" bitfld.long 0x4 0. "MEM_WR_DONE,When the ARM BUS side has fully finished the last transaction from the FIFO to write the data to Memory for Posted Writes . Clear with new Write request." "0,1" line.long 0x8 "SPI_EC_STS,SPI Peripheral Target EC Status Register." bitfld.long 0x8 28. "RXF_OVRFLW,If SPI Master writes more than the space in the FIFO the FIFO will flag an overflow error and data will not be stored." "0,1" bitfld.long 0x8 27. "RXF_UNFLW,If the SPI Peripheral Target reads RX FIFO when it is empty RX FIFO Underflow flag will be set. This condition will never happen under normal situation." "0,1" bitfld.long 0x8 26. "TXF_OVRFLW,If Master doesn't read all of the data it requested from the posted read block cycle than data will still be left in the FIFO. This will cause misalignment with the following transactions and a new read cycle can cause overflow." "0,1" newline bitfld.long 0x8 25. "TXF_UNFLW,If Master reads more than what is in FIFO FIFO will flag an underflow error and the data returned will just be the last valid pointer value." "0,1" bitfld.long 0x8 24. "RXF_SIZE_ERR,If size requested is more than what Master provided and the Master terminates early error flag shut down request signal to ARM Bus. Size requested is less than what Master provided -- ignored and continue transaction may be.." "0,1" bitfld.long 0x8 23. "DV_BUSY,If the Master requested a transaction whose destination is busy the request is ignored. Should use the poll or wait for interrupts." "0,1" newline bitfld.long 0x8 22. "UNDEF_CMD_ERR,Undefined Command Error: The command received from the master isn't defined." "0,1" bitfld.long 0x8 21. "ARMBUS_ERR,ARM Bus Error returned for the curren data transfer." "0,1" bitfld.long 0x8 20. "OOL1_ERR,This flag is set with the transfer address requested by the master is out of Limit 1 range or when the BAR is disabled." "0,1" newline bitfld.long 0x8 19. "OOL0_ERR,This flag is set with the transfer address requested by the master is out of Limit 0 range or when the BAR is disabled." "0,1" bitfld.long 0x8 18. "TXF_RST_DN,Set after the SPI Master initiates a TX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" bitfld.long 0x8 17. "RXF_RST_DN,Set after the SPI Master initiates a RX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" newline bitfld.long 0x8 16. "SPIM_RST_REQ,Set when the SPI Master Requested a Configuration Reset." "0,1" bitfld.long 0x8 15. "OBF_FLG,Set when the EC writes to the Output Buffer signaling there is data for the Host to read." "0,1" bitfld.long 0x8 14. "IBF_FLG,Set when the Host writes to the Input Buffer signaling there is data for the EC to read." "0,1" newline bitfld.long 0x8 13. "TMCLK_CNT_ERR,This bit is set when the SPI Clock Count Test Mode is set and there is an uneven amount of clocks." "0,1" bitfld.long 0x8 11. "TXF_FUL,The TX FIFO is full of data that was read from Memory." "0,1" bitfld.long 0x8 10. "TXF_EMP,Signifies SPI Master has read the data requested from Memory. Can be used to show there is data the SPI Master has requested and not been read yet. New read transactions will be aligned." "0,1" newline bitfld.long 0x8 9. "RXF_FUL,The RX FIFO is full of data to be written to Memory." "0,1" bitfld.long 0x8 8. "RXF_EMP,Signifies all Memory write transactions for the SPI Masters requested size have been performed. New transactions are allowed." "0,1" bitfld.long 0x8 6. "POLL_HI,If this bit is set then something in the high 16-bit of status register is set and needs to be checked. SPI Master should take action to clear this." "0,1" newline bitfld.long 0x8 5. "SREG_TRANS,When an SREG transaction is currently being processed." "0,1" bitfld.long 0x8 4. "MEM_RD_BUSY,When an Memory Read transaction is currently being processed." "0,1" bitfld.long 0x8 3. "MEM_WR_BUSY,When an Memory Write transaction is currently being processed." "0,1" newline bitfld.long 0x8 1. "MEM_RD_DONE,When the ARM BUS side has fully finished writing the last written DWord to the FIFO for a set of data read from Memory for Posted Reads. - cleared with new Read request." "0,1" bitfld.long 0x8 0. "MEM_WR_DONE,When the ARM BUS side has fully finished the last transaction from the FIFO to write the data to Memory for Posted Writes .- clear with new Write request." "0,1" line.long 0xC "SPI_IEN,SPI Peripheral Target Interrupt Enable Register." bitfld.long 0xC 28. "RXF_OVRFLW,Enable RX FIFO Overflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 27. "RXF_UNFLW,Enable RX FIFO Underflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 26. "TXF_OVRFLOW,Enable TX FIFO Overflow Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 25. "TXF_UNFLW,Enable TX FIFO Underflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 24. "RXF_SIZE_ERR,Enable RX FIFO SIZE Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 23. "DV_BUSY,Enable Device Busy Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 22. "UNDEF_CMD_ERR,Enable Undefined Command Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 21. "ARMBUS_ERR,Enable AHB BUS Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 20. "OOL1_ERR,Enable Out Of Limit 1 Error Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 19. "OOL0_ERR,Enable Out Of Limit 0 Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 18. "TXF_RST_DN,Enable TX FIFO Reset Done Interrupt to SPI Master." "0,1" bitfld.long 0xC 17. "RXF_RST_DN,Enable RX FIFO Reset Done Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 16. "SPIM_RST_REQ,Enable SPI Master Request Reset Interrupt to SPI Master." "0,1" bitfld.long 0xC 15. "OBF_FLG,Enable Output Buffer signaling Interrupt to SPI Master." "0,1" bitfld.long 0xC 14. "IBF_FLG,Enable Input Buffer Signaling Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 13. "TMCLK_CNT_ERR,Enable Test Mode SPI Clock Count Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 11. "TXF_FUL,Enable TX FIFI FULL Interrupt to SPI Master." "0,1" bitfld.long 0xC 10. "TXF_EMP,Enable TX FIFO Empty Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 9. "RXF_FUL,Enable RX FIFO Full Interrupt to SPI Master." "0,1" bitfld.long 0xC 8. "RXF_EMP,Enable SREG RX FIFO Empty Interrupt to SPI Master." "0,1" bitfld.long 0xC 6. "POLL_HI,Enable Poll High Request Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 5. "SREG_TRANS,Enable SREG Trans Busy Interrupt to SPI Master." "0,1" bitfld.long 0xC 4. "MEM_RD_BUSY,Enable Memory Read Busy Interrupt to SPI Master." "0,1" bitfld.long 0xC 3. "MEM_WR_BUSY,Enable Memory Write Busy Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 1. "MEM_RD_DONE,Enable Memory Read Done Interrupt to SPI Master." "0,1" bitfld.long 0xC 0. "MEM_WR_DONE,Enable Memory Write Done Interrupt to SPI Master." "0,1" line.long 0x10 "EC_IEN,SPI Peripheral Target EC Interrupt Enable Register." bitfld.long 0x10 28. "RXF_OVRFLW,Enable RX FIFO Overflow Interrupt to EC." "0,1" bitfld.long 0x10 27. "RXF_UNFLW,Enable RX FIFO Underflow Interrupt to EC." "0,1" bitfld.long 0x10 26. "TXF_OVRFLW,Enable TX FIFO Overflow Interrupt to EC." "0,1" newline bitfld.long 0x10 25. "TXF_UNFLW,Enable TX FIFO Underflow Interrupt to EC." "0,1" bitfld.long 0x10 24. "RXF_SIZE_ERR,Enable RX FIFO SIZE Error Interrupt to EC." "0,1" bitfld.long 0x10 23. "DV_BUSY,Enable Device Busy Interrupt to EC." "0,1" newline bitfld.long 0x10 22. "UNDEF_CMD_ERR,Enable Undefined Command Error Interrupt to EC." "0,1" bitfld.long 0x10 21. "ARMBUS_ERR,Enable AHB BUS Error Interrupt to EC." "0,1" bitfld.long 0x10 20. "OOL1_ERR,Enable Out Of Limit 1 Error Interrupt to EC." "0,1" newline bitfld.long 0x10 19. "OOL0_ERR,Enable Out Of Limit 0 Error Interrupt to EC." "0,1" bitfld.long 0x10 18. "TXF_RST_DN,Enable TX FIFO Reset Done Interrupt to EC." "0,1" bitfld.long 0x10 17. "RXF_RST_DN,Enable RX FIFO Reset Done Interrupt to EC." "0,1" newline bitfld.long 0x10 16. "SPIM_RST_REQ,Enable SPI Master Request Reset Interrupt to EC." "0,1" bitfld.long 0x10 15. "OBF_FLG,Enable Output Buffer signaling Interrupt to EC." "0,1" bitfld.long 0x10 14. "IBF_FLG,Enable Input Buffer Signaling Interrupt to EC." "0,1" newline bitfld.long 0x10 13. "TMCLK_CNT_ERR,Enable Test Mode SPI Clock Count Error Interrupt to EC." "0,1" bitfld.long 0x10 11. "TXF_FUL,Enable TX FIFI FULL Interrupt to EC." "0,1" bitfld.long 0x10 10. "TXF_EMP,Enable TX FIFO Empty Interrupt to EC." "0,1" newline bitfld.long 0x10 9. "RXF_FUL,Enable RX FIFO Full Interrupt to EC." "0,1" bitfld.long 0x10 8. "RXF_EMP,Enable SREG RX FIFO Empty Interrupt to EC." "0,1" bitfld.long 0x10 6. "POLL_HI,Enable Poll High Request Interrupt to EC." "0,1" newline bitfld.long 0x10 5. "SREG_TRANS,Enable SREG Trans Busy Interrupt to EC." "0,1" bitfld.long 0x10 4. "MEM_RD_BUSY,Enable Memory Read Busy Interrupt to EC." "0,1" bitfld.long 0x10 3. "MEM_WR_BUSY,Enable Memory Write Busy Interrupt to EC." "0,1" newline bitfld.long 0x10 1. "MEM_RD_DONE,Enable Memory Read Done Interrupt to EC." "0,1" bitfld.long 0x10 0. "MEM_WR_DONE,Enable Memory Write Done Interrupt to EC." "0,1" line.long 0x14 "MEM_CFG,SPI Peripheral Target Memory Configuration Register." bitfld.long 0x14 1. "BAR_EN1_SEL,Enables Region 1 operation. 0 = Disable Region 1. 1 = Enable Region 1." "0: Disable Region 1,1: Enable Region 1" bitfld.long 0x14 0. "BAR_EN0_SEL,Enables Region 0 operation. 0 = Disable Region 0. 1 = Enable Region 0." "0: Disable Region 0,1: Enable Region 0" line.long 0x18 "MEM_BAR0,SPI Peripheral Target Memory Base Address0 Register." hexmask.long 0x18 0.--31. 1. "BAS_ADD0,Base Address for Region 0." line.long 0x1C "MEM_WR_LIM0,SPI Peripheral Target Memory Write LIMIT 0 Register." hexmask.long.word 0x1C 0.--14. 1. "LMT0,Write Limit for Region 0." line.long 0x20 "MEM_RD_LIM0,SPI Peripheral Target Memory Read LIMIT 0 Register." hexmask.long.word 0x20 0.--14. 1. "LMT0,Read Limit for Region 0." line.long 0x24 "MEM_BAR1,SPI Peripheral Target Memory Base Address1 Register." hexmask.long 0x24 0.--31. 1. "ADD1,Base Address for Region 1." line.long 0x28 "MEM_WR_LIM1,SPI Peripheral Target Memory Write LIMIT 1 Register." hexmask.long.word 0x28 0.--14. 1. "LMT1,Write Limit for Region 1." line.long 0x2C "MEM_RD_LIM1,SPI Peripheral Target Memory Read LIMIT 1 Register." hexmask.long.word 0x2C 0.--14. 1. "LMT1,Read Limit for Region 1." rgroup.long 0x30++0xF line.long 0x0 "RXF_HOST_BAR,SPI Peripheral Target RX FIFO Host Bar Register." hexmask.long.word 0x0 0.--15. 1. "BAR,RX FIFO Host Bar Register." line.long 0x4 "RXF_BYTE_CNT,SPI Peripheral Target RX FIFO Byte Counter Register." hexmask.long.word 0x4 0.--14. 1. "BCNT,RX FIFO Byte Count Register." line.long 0x8 "TXF_HOST_BAR,SPI Peripheral Target TX FIFO Host Bar Register." hexmask.long.word 0x8 0.--15. 1. "BAR,TX FIFO Host Bar Register." line.long 0xC "TXF_BYTE_CNT,SPI Peripheral Target TX FIFO Byte Counter Register." hexmask.long.word 0xC 0.--14. 1. "BCNT,TX FIFO Byte Count Register." group.long 0x40++0xB line.long 0x0 "SYS_CFG,SPI Peripheral Target System Configuration Register." bitfld.long 0x0 19. "ECDATL,Notification to TX FIFO Engine that data is available for AHB Transfer. This register but is cleared by Hardware at the end of the transaction with SPI_CS_N de-assertion. (R/WC)." "0,1" bitfld.long 0x0 18. "SIM_EN,Enable SPI Peripheral Target Simple Mode operation." "0,1" bitfld.long 0x0 17. "MAS_ECREG,Fixed in hardware to 1" "0,1" newline bitfld.long 0x0 16. "SPI_SLV_EN,Enable / Disable SPI Peripheral Target Block. 0 = Disable SPI Peripheral Target module. 1 = Enable SPI Peripheral Target module." "0: Disable SPI Peripheral Target module,1: Enable SPI Peripheral Target module" bitfld.long 0x0 10. "LOCK_TEST_MODE,Lock TEST Mode register write access from SPI Master." "0,1" bitfld.long 0x0 7. "LOCK_MEM_BAR1,Lock Memory Bar 1 register write access from SPI Master." "0,1" newline bitfld.long 0x0 6. "LOCK_MEM_BAR0,Lock Memory Bar 0 register write access from SPI Master." "0,1" bitfld.long 0x0 5. "LOCK_SPIINT_EN,Lock SPI Interrupt Enable register write access from SPI Master." "0,1" bitfld.long 0x0 4. "LOCK_MEM_CFG,Lock Memory Configuration register write access from SPI Master." "0,1" newline bitfld.long 0x0 3. "LOCK_WAIT_CYCL,Lock Wait Cycle bits write access from SPI Master." "0,1" bitfld.long 0x0 2. "LOCK_TAR_TIME,Lock Tar Time bit write access from SPI Master." "0,1" bitfld.long 0x0 1. "LOCK_QUAD_SNGL_WRMOD,Lock Quad / Single Write Mode bit write access from SPI Master." "0,1" newline bitfld.long 0x0 0. "SOFT_RST,Soft reset for entire SPI Peripheral Target Block. This bit is self clearing." "0,1" line.long 0x4 "SPIM2EC_MBX,SPI Peripheral Target Master to EC Mailbox Register." hexmask.long 0x4 0.--31. 1. "M2EC,Write only register for the Host. When data is written to this register the IBF Flag is set. EC can read the data and writes of 0xFFFF will clear this register. Any form of read will clear the flag for this register." line.long 0x8 "EC2SPIM_MBX,SPI Peripheral Target Master to EC Mailbox Register." hexmask.long 0x8 0.--31. 1. "EC2M,Read only register for the Host. When data is written to this register the OBF Flag is set. Host can read the data and writes of 0xFFFF_FFFF will clear this register also clearing the flag. Any form of read will clear the flag for.." tree.end tree "SPT1" base ad:0x40006C00 group.long 0x0++0x2F line.long 0x0 "SPI_CFG,SPI Peripheral Target Communication Configuration Register." hexmask.long.byte 0x0 16.--23. 1. "WAIT_TIME,These bits set the amount of wait time in cycles before transmitting data back to master. During this wait time status bits will be transmitted" bitfld.long 0x0 8.--10. "TAR_TIM_SEL,Turn Around Time select for Quad wire mode. 0h = 1 cycle. 1h = 2 cycles. 2h = 4 cycles. 3h = 8 cycles. Other values are reserved." "0: 1 cycle,1: 2 cycle,2: 4 cycle,3: 8 cycle,?,?,?,?" bitfld.long 0x0 0. "SNG_QUD_SEL,This field defines the Single / Quad Wire mode of operation for SPI Peripheral Target block. 0 = Single Wire Slave SPI block operation. 1 = Quad Wire Slave SPI block operation." "0: Single Wire Slave SPI block operation,1: Quad Wire Slave SPI block operation" line.long 0x4 "SPI_STS,SPI Peripheral Target Status Register." bitfld.long 0x4 28. "RXF_OVRFLW,If SPI Master writes more than the space in the FIFO the FIFO will flag an overflow error and data will not be stored." "0,1" bitfld.long 0x4 27. "RXF_UNFLW,If the SPI Peripheral Target reads RX FIFO when it is empty RX FIFO Underflow flag will be set. This condition will never happen under normal situation." "0,1" bitfld.long 0x4 26. "TXF_OVRFLW,If Master doesn't read all of the data it requested from the posted read block cycle than data will still be left in the FIFO. This will cause misalignment with the following transactions and a new read cycle can cause overflow." "0,1" newline bitfld.long 0x4 25. "TXF_UNFLW,If Master reads more than what is in FIFO FIFO will flag an underflow error and the data returned will just be the last valid pointer value." "0,1" bitfld.long 0x4 24. "RXF_SIZE_ERR,If size requested is more than what Master provided and the Master terminates early error flag shut down request signal to ARM Bus. Size requested is less than what Master provided -- ignored and continue transaction may be.." "0,1" bitfld.long 0x4 23. "DV_BUSY,If the Master requested a transaction whose destination is busy the request is ignored. Should use the poll or wait for interrupts." "0,1" newline bitfld.long 0x4 22. "UNDEF_CMD_ERR,Undefined Command Error: The command received from the master isn't defined." "0,1" bitfld.long 0x4 21. "ARMBUS_ERR,ARM Bus Error returned for the curren data transfer." "0,1" bitfld.long 0x4 20. "OOL1_ERR,This flag is set with the transfer address requested by the master is out of Limit 1 range or when the BAR is disabled." "0,1" newline bitfld.long 0x4 19. "OOL0_ERR,This flag is set with the transfer address requested by the master is out of Limit 0 range or when the BAR is disabled." "0,1" bitfld.long 0x4 18. "TXF_RST_DN,Set after the SPI Master initiates a TX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" bitfld.long 0x4 17. "RXF_RST_DN,Set after the SPI Master initiates a RX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" newline bitfld.long 0x4 16. "SPIM_RST_REQ,Set when the SPI Master Requested a Configuration Reset." "0,1" bitfld.long 0x4 15. "OBF_FLG,Set when the EC writes to the Output Buffer signaling there is data for the Host to read." "0,1" bitfld.long 0x4 14. "IBF_FLG,Set when the Host writes to the Input Buffer signaling there is data for the EC to read." "0,1" newline bitfld.long 0x4 13. "TMCLK_CNT_ERR,This bit is set when the SPI Clock Count Test Mode is set and there is an uneven amount of clocks." "0,1" bitfld.long 0x4 11. "TXF_FUL,The TX FIFO is full of data that was read from Memory." "0,1" bitfld.long 0x4 10. "TXF_EMP,Signifies SPI Master has read the data requested from Memory. Can be used to show there is data the SPI Master has requested and not been read yet. New read transactions will be aligned." "0,1" newline bitfld.long 0x4 9. "RXF_FUL,The RX FIFO is full of data to be written to Memory." "0,1" bitfld.long 0x4 8. "RXF_EMP,Signifies all Memory write transactions for the SPI Masters requested size have been performed. New transactions are allowed." "0,1" bitfld.long 0x4 6. "POLL_HIGH,If this bit is set then something in the high 16-bit of status register is set and needs to be checked. SPI Master should take action to clear this." "0,1" newline bitfld.long 0x4 5. "SREG_TRANS,When an SREG transaction is currently being processed." "0,1" bitfld.long 0x4 4. "MEM_RD_BUSY,When an Memory Read transaction is currently being processed." "0,1" bitfld.long 0x4 3. "MEM_WR_BUSY,When an Memory Write transaction is currently being processed." "0,1" newline bitfld.long 0x4 1. "MEM_RD_DONE,When the ARM BUS side has fully finished writing the last written DWord to the FIFO for a set of data read from Memory for Posted Reads. - cleared with new Read request." "0,1" bitfld.long 0x4 0. "MEM_WR_DONE,When the ARM BUS side has fully finished the last transaction from the FIFO to write the data to Memory for Posted Writes . Clear with new Write request." "0,1" line.long 0x8 "SPI_EC_STS,SPI Peripheral Target EC Status Register." bitfld.long 0x8 28. "RXF_OVRFLW,If SPI Master writes more than the space in the FIFO the FIFO will flag an overflow error and data will not be stored." "0,1" bitfld.long 0x8 27. "RXF_UNFLW,If the SPI Peripheral Target reads RX FIFO when it is empty RX FIFO Underflow flag will be set. This condition will never happen under normal situation." "0,1" bitfld.long 0x8 26. "TXF_OVRFLW,If Master doesn't read all of the data it requested from the posted read block cycle than data will still be left in the FIFO. This will cause misalignment with the following transactions and a new read cycle can cause overflow." "0,1" newline bitfld.long 0x8 25. "TXF_UNFLW,If Master reads more than what is in FIFO FIFO will flag an underflow error and the data returned will just be the last valid pointer value." "0,1" bitfld.long 0x8 24. "RXF_SIZE_ERR,If size requested is more than what Master provided and the Master terminates early error flag shut down request signal to ARM Bus. Size requested is less than what Master provided -- ignored and continue transaction may be.." "0,1" bitfld.long 0x8 23. "DV_BUSY,If the Master requested a transaction whose destination is busy the request is ignored. Should use the poll or wait for interrupts." "0,1" newline bitfld.long 0x8 22. "UNDEF_CMD_ERR,Undefined Command Error: The command received from the master isn't defined." "0,1" bitfld.long 0x8 21. "ARMBUS_ERR,ARM Bus Error returned for the curren data transfer." "0,1" bitfld.long 0x8 20. "OOL1_ERR,This flag is set with the transfer address requested by the master is out of Limit 1 range or when the BAR is disabled." "0,1" newline bitfld.long 0x8 19. "OOL0_ERR,This flag is set with the transfer address requested by the master is out of Limit 0 range or when the BAR is disabled." "0,1" bitfld.long 0x8 18. "TXF_RST_DN,Set after the SPI Master initiates a TX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" bitfld.long 0x8 17. "RXF_RST_DN,Set after the SPI Master initiates a RX FIFO reset and the reset has been processed. FIFO is cleared." "0,1" newline bitfld.long 0x8 16. "SPIM_RST_REQ,Set when the SPI Master Requested a Configuration Reset." "0,1" bitfld.long 0x8 15. "OBF_FLG,Set when the EC writes to the Output Buffer signaling there is data for the Host to read." "0,1" bitfld.long 0x8 14. "IBF_FLG,Set when the Host writes to the Input Buffer signaling there is data for the EC to read." "0,1" newline bitfld.long 0x8 13. "TMCLK_CNT_ERR,This bit is set when the SPI Clock Count Test Mode is set and there is an uneven amount of clocks." "0,1" bitfld.long 0x8 11. "TXF_FUL,The TX FIFO is full of data that was read from Memory." "0,1" bitfld.long 0x8 10. "TXF_EMP,Signifies SPI Master has read the data requested from Memory. Can be used to show there is data the SPI Master has requested and not been read yet. New read transactions will be aligned." "0,1" newline bitfld.long 0x8 9. "RXF_FUL,The RX FIFO is full of data to be written to Memory." "0,1" bitfld.long 0x8 8. "RXF_EMP,Signifies all Memory write transactions for the SPI Masters requested size have been performed. New transactions are allowed." "0,1" bitfld.long 0x8 6. "POLL_HI,If this bit is set then something in the high 16-bit of status register is set and needs to be checked. SPI Master should take action to clear this." "0,1" newline bitfld.long 0x8 5. "SREG_TRANS,When an SREG transaction is currently being processed." "0,1" bitfld.long 0x8 4. "MEM_RD_BUSY,When an Memory Read transaction is currently being processed." "0,1" bitfld.long 0x8 3. "MEM_WR_BUSY,When an Memory Write transaction is currently being processed." "0,1" newline bitfld.long 0x8 1. "MEM_RD_DONE,When the ARM BUS side has fully finished writing the last written DWord to the FIFO for a set of data read from Memory for Posted Reads. - cleared with new Read request." "0,1" bitfld.long 0x8 0. "MEM_WR_DONE,When the ARM BUS side has fully finished the last transaction from the FIFO to write the data to Memory for Posted Writes .- clear with new Write request." "0,1" line.long 0xC "SPI_IEN,SPI Peripheral Target Interrupt Enable Register." bitfld.long 0xC 28. "RXF_OVRFLW,Enable RX FIFO Overflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 27. "RXF_UNFLW,Enable RX FIFO Underflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 26. "TXF_OVRFLOW,Enable TX FIFO Overflow Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 25. "TXF_UNFLW,Enable TX FIFO Underflow Interrupt to SPI Master." "0,1" bitfld.long 0xC 24. "RXF_SIZE_ERR,Enable RX FIFO SIZE Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 23. "DV_BUSY,Enable Device Busy Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 22. "UNDEF_CMD_ERR,Enable Undefined Command Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 21. "ARMBUS_ERR,Enable AHB BUS Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 20. "OOL1_ERR,Enable Out Of Limit 1 Error Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 19. "OOL0_ERR,Enable Out Of Limit 0 Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 18. "TXF_RST_DN,Enable TX FIFO Reset Done Interrupt to SPI Master." "0,1" bitfld.long 0xC 17. "RXF_RST_DN,Enable RX FIFO Reset Done Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 16. "SPIM_RST_REQ,Enable SPI Master Request Reset Interrupt to SPI Master." "0,1" bitfld.long 0xC 15. "OBF_FLG,Enable Output Buffer signaling Interrupt to SPI Master." "0,1" bitfld.long 0xC 14. "IBF_FLG,Enable Input Buffer Signaling Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 13. "TMCLK_CNT_ERR,Enable Test Mode SPI Clock Count Error Interrupt to SPI Master." "0,1" bitfld.long 0xC 11. "TXF_FUL,Enable TX FIFI FULL Interrupt to SPI Master." "0,1" bitfld.long 0xC 10. "TXF_EMP,Enable TX FIFO Empty Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 9. "RXF_FUL,Enable RX FIFO Full Interrupt to SPI Master." "0,1" bitfld.long 0xC 8. "RXF_EMP,Enable SREG RX FIFO Empty Interrupt to SPI Master." "0,1" bitfld.long 0xC 6. "POLL_HI,Enable Poll High Request Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 5. "SREG_TRANS,Enable SREG Trans Busy Interrupt to SPI Master." "0,1" bitfld.long 0xC 4. "MEM_RD_BUSY,Enable Memory Read Busy Interrupt to SPI Master." "0,1" bitfld.long 0xC 3. "MEM_WR_BUSY,Enable Memory Write Busy Interrupt to SPI Master." "0,1" newline bitfld.long 0xC 1. "MEM_RD_DONE,Enable Memory Read Done Interrupt to SPI Master." "0,1" bitfld.long 0xC 0. "MEM_WR_DONE,Enable Memory Write Done Interrupt to SPI Master." "0,1" line.long 0x10 "EC_IEN,SPI Peripheral Target EC Interrupt Enable Register." bitfld.long 0x10 28. "RXF_OVRFLW,Enable RX FIFO Overflow Interrupt to EC." "0,1" bitfld.long 0x10 27. "RXF_UNFLW,Enable RX FIFO Underflow Interrupt to EC." "0,1" bitfld.long 0x10 26. "TXF_OVRFLW,Enable TX FIFO Overflow Interrupt to EC." "0,1" newline bitfld.long 0x10 25. "TXF_UNFLW,Enable TX FIFO Underflow Interrupt to EC." "0,1" bitfld.long 0x10 24. "RXF_SIZE_ERR,Enable RX FIFO SIZE Error Interrupt to EC." "0,1" bitfld.long 0x10 23. "DV_BUSY,Enable Device Busy Interrupt to EC." "0,1" newline bitfld.long 0x10 22. "UNDEF_CMD_ERR,Enable Undefined Command Error Interrupt to EC." "0,1" bitfld.long 0x10 21. "ARMBUS_ERR,Enable AHB BUS Error Interrupt to EC." "0,1" bitfld.long 0x10 20. "OOL1_ERR,Enable Out Of Limit 1 Error Interrupt to EC." "0,1" newline bitfld.long 0x10 19. "OOL0_ERR,Enable Out Of Limit 0 Error Interrupt to EC." "0,1" bitfld.long 0x10 18. "TXF_RST_DN,Enable TX FIFO Reset Done Interrupt to EC." "0,1" bitfld.long 0x10 17. "RXF_RST_DN,Enable RX FIFO Reset Done Interrupt to EC." "0,1" newline bitfld.long 0x10 16. "SPIM_RST_REQ,Enable SPI Master Request Reset Interrupt to EC." "0,1" bitfld.long 0x10 15. "OBF_FLG,Enable Output Buffer signaling Interrupt to EC." "0,1" bitfld.long 0x10 14. "IBF_FLG,Enable Input Buffer Signaling Interrupt to EC." "0,1" newline bitfld.long 0x10 13. "TMCLK_CNT_ERR,Enable Test Mode SPI Clock Count Error Interrupt to EC." "0,1" bitfld.long 0x10 11. "TXF_FUL,Enable TX FIFI FULL Interrupt to EC." "0,1" bitfld.long 0x10 10. "TXF_EMP,Enable TX FIFO Empty Interrupt to EC." "0,1" newline bitfld.long 0x10 9. "RXF_FUL,Enable RX FIFO Full Interrupt to EC." "0,1" bitfld.long 0x10 8. "RXF_EMP,Enable SREG RX FIFO Empty Interrupt to EC." "0,1" bitfld.long 0x10 6. "POLL_HI,Enable Poll High Request Interrupt to EC." "0,1" newline bitfld.long 0x10 5. "SREG_TRANS,Enable SREG Trans Busy Interrupt to EC." "0,1" bitfld.long 0x10 4. "MEM_RD_BUSY,Enable Memory Read Busy Interrupt to EC." "0,1" bitfld.long 0x10 3. "MEM_WR_BUSY,Enable Memory Write Busy Interrupt to EC." "0,1" newline bitfld.long 0x10 1. "MEM_RD_DONE,Enable Memory Read Done Interrupt to EC." "0,1" bitfld.long 0x10 0. "MEM_WR_DONE,Enable Memory Write Done Interrupt to EC." "0,1" line.long 0x14 "MEM_CFG,SPI Peripheral Target Memory Configuration Register." bitfld.long 0x14 1. "BAR_EN1_SEL,Enables Region 1 operation. 0 = Disable Region 1. 1 = Enable Region 1." "0: Disable Region 1,1: Enable Region 1" bitfld.long 0x14 0. "BAR_EN0_SEL,Enables Region 0 operation. 0 = Disable Region 0. 1 = Enable Region 0." "0: Disable Region 0,1: Enable Region 0" line.long 0x18 "MEM_BAR0,SPI Peripheral Target Memory Base Address0 Register." hexmask.long 0x18 0.--31. 1. "BAS_ADD0,Base Address for Region 0." line.long 0x1C "MEM_WR_LIM0,SPI Peripheral Target Memory Write LIMIT 0 Register." hexmask.long.word 0x1C 0.--14. 1. "LMT0,Write Limit for Region 0." line.long 0x20 "MEM_RD_LIM0,SPI Peripheral Target Memory Read LIMIT 0 Register." hexmask.long.word 0x20 0.--14. 1. "LMT0,Read Limit for Region 0." line.long 0x24 "MEM_BAR1,SPI Peripheral Target Memory Base Address1 Register." hexmask.long 0x24 0.--31. 1. "ADD1,Base Address for Region 1." line.long 0x28 "MEM_WR_LIM1,SPI Peripheral Target Memory Write LIMIT 1 Register." hexmask.long.word 0x28 0.--14. 1. "LMT1,Write Limit for Region 1." line.long 0x2C "MEM_RD_LIM1,SPI Peripheral Target Memory Read LIMIT 1 Register." hexmask.long.word 0x2C 0.--14. 1. "LMT1,Read Limit for Region 1." rgroup.long 0x30++0xF line.long 0x0 "RXF_HOST_BAR,SPI Peripheral Target RX FIFO Host Bar Register." hexmask.long.word 0x0 0.--15. 1. "BAR,RX FIFO Host Bar Register." line.long 0x4 "RXF_BYTE_CNT,SPI Peripheral Target RX FIFO Byte Counter Register." hexmask.long.word 0x4 0.--14. 1. "BCNT,RX FIFO Byte Count Register." line.long 0x8 "TXF_HOST_BAR,SPI Peripheral Target TX FIFO Host Bar Register." hexmask.long.word 0x8 0.--15. 1. "BAR,TX FIFO Host Bar Register." line.long 0xC "TXF_BYTE_CNT,SPI Peripheral Target TX FIFO Byte Counter Register." hexmask.long.word 0xC 0.--14. 1. "BCNT,TX FIFO Byte Count Register." group.long 0x40++0xB line.long 0x0 "SYS_CFG,SPI Peripheral Target System Configuration Register." bitfld.long 0x0 19. "ECDATL,Notification to TX FIFO Engine that data is available for AHB Transfer. This register but is cleared by Hardware at the end of the transaction with SPI_CS_N de-assertion. (R/WC)." "0,1" bitfld.long 0x0 18. "SIM_EN,Enable SPI Peripheral Target Simple Mode operation." "0,1" bitfld.long 0x0 17. "MAS_ECREG,Fixed in hardware to 1" "0,1" newline bitfld.long 0x0 16. "SPI_SLV_EN,Enable / Disable SPI Peripheral Target Block. 0 = Disable SPI Peripheral Target module. 1 = Enable SPI Peripheral Target module." "0: Disable SPI Peripheral Target module,1: Enable SPI Peripheral Target module" bitfld.long 0x0 10. "LOCK_TEST_MODE,Lock TEST Mode register write access from SPI Master." "0,1" bitfld.long 0x0 7. "LOCK_MEM_BAR1,Lock Memory Bar 1 register write access from SPI Master." "0,1" newline bitfld.long 0x0 6. "LOCK_MEM_BAR0,Lock Memory Bar 0 register write access from SPI Master." "0,1" bitfld.long 0x0 5. "LOCK_SPIINT_EN,Lock SPI Interrupt Enable register write access from SPI Master." "0,1" bitfld.long 0x0 4. "LOCK_MEM_CFG,Lock Memory Configuration register write access from SPI Master." "0,1" newline bitfld.long 0x0 3. "LOCK_WAIT_CYCL,Lock Wait Cycle bits write access from SPI Master." "0,1" bitfld.long 0x0 2. "LOCK_TAR_TIME,Lock Tar Time bit write access from SPI Master." "0,1" bitfld.long 0x0 1. "LOCK_QUAD_SNGL_WRMOD,Lock Quad / Single Write Mode bit write access from SPI Master." "0,1" newline bitfld.long 0x0 0. "SOFT_RST,Soft reset for entire SPI Peripheral Target Block. This bit is self clearing." "0,1" line.long 0x4 "SPIM2EC_MBX,SPI Peripheral Target Master to EC Mailbox Register." hexmask.long 0x4 0.--31. 1. "M2EC,Write only register for the Host. When data is written to this register the IBF Flag is set. EC can read the data and writes of 0xFFFF will clear this register. Any form of read will clear the flag for this register." line.long 0x8 "EC2SPIM_MBX,SPI Peripheral Target Master to EC Mailbox Register." hexmask.long 0x8 0.--31. 1. "EC2M,Read only register for the Host. When data is written to this register the OBF Flag is set. Host can read the data and writes of 0xFFFF_FFFF will clear this register also clearing the flag. Any form of read will clear the flag for.." tree.end tree.end endif tree "SYSTICK (System Timer)" base ad:0xE000E010 group.long 0x0++0xB line.long 0x0 "CSR,SysTick Control and Status Register" bitfld.long 0x0 16. "COUNTFLAG,Timer counted to 0 since last read of register" "0,1" bitfld.long 0x0 2. "CLKSOURCE,Clock Source 0=external 1=processor" "0: external,1: processor" newline bitfld.long 0x0 1. "TICKINT,SysTick Exception Request Enable" "0: Counting down to 0 does not assert the SysTick..,1: Counting down to 0 asserts the SysTick exception.." bitfld.long 0x0 0. "ENABLE,SysTick Counter Enable" "0: Counter disabled,1: Counter enabled" line.long 0x4 "RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0" line.long 0x8 "CVR,SysTick Current Value Register" hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current value at the time the register is accessed" rgroup.long 0xC++0x3 line.long 0x0 "CALIB,SysTick Calibration Value Register" bitfld.long 0x0 31. "NOREF,No Separate Reference Clock" "0: The reference clock is provided,1: The reference clock is not provided" bitfld.long 0x0 30. "SKEW,TENMS is rounded from non-integer ratio" "0: 10ms calibration value is exact,1: 10ms calibration value is inexact because of the.." newline hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Reload value to use for 10ms timing" tree.end sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "TACH (Tachometers)" base ad:0x0 tree "TACH0" base ad:0x40006000 group.long 0x0++0xF line.long 0x0 "CTRL,TACHx Control Register" hexmask.long.word 0x0 16.--31. 1. "CNTR,This 16-bit field contains the latched value of the internal Tach pulse counter which may be configured by the \n Tach Reading Mode Select field to operate as a free-running counter or to be gated by the Tach input signal." bitfld.long 0x0 15. "IN_INT_EN,IN_INT_EN 1=Enable Tach Input toggle interrupt from Tach block 0=Disable Tach Input toggle interrupt from Tach block" "0: Disable Tach Input toggle interrupt from Tach..,1: Enable Tach Input toggle interrupt from Tach block" newline bitfld.long 0x0 14. "CNT_RDY_INT_EN,CNT_RDY_INT_EN 1=Enable Count Ready interrupt from Tach block 0=Disable Count Ready interrupt from Tach block" "0: Disable Count Ready interrupt from Tach block,1: Enable Count Ready interrupt from Tach block" bitfld.long 0x0 11.--12. "EDGES,EDGES A Tach signal is a square wave with a 50% duty cycle. Typically two Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges.\n This programmed value represents the number of Tach edges that will be.." "0,1,2,3" newline bitfld.long 0x0 10. "RD_MOD_SEL,RD_MOD_SEL\n 1=Counter is incremented on the rising edge of the 100kHz_Clk input. The counter is latched into the TACHX_COUNTER field and reset when the programmed number of edges is detected.\n 0=Counter is incremented when.." "0: Counter is incremented when Tach Input..,1: Counter is incremented on the rising edge of the.." bitfld.long 0x0 8. "FILT_EN,FILT_EN This filter is used to remove high frequency glitches from Tach Input. When this filter is enabled Tach input pulses less than two 100kHz_- Clk periods wide get filtered.\n 1= Filter enabled\n 0= Filter disabled.." "0: Filter disabled,1: Filter enabled\n" newline bitfld.long 0x0 1. "EN,EN 1= TACH Monitoring enabled clocks enabled. 0= TACH Idle clocks gated" "0: TACH Idle,1: TACH Monitoring enabled" bitfld.long 0x0 0. "OUTOF_LIM_EN,OUTOF_LIM_EN This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in the TACHx Status Register to generate an interrupt event.\n 1=Enable interrupt output from Tach block\n 0=Disable interrupt output from Tach.." "0: Disable interrupt output from Tach block,1: Enable interrupt output from Tach block\n" line.long 0x4 "STS,TACHx Status Register" bitfld.long 0x4 3. "CNT_RDY_STS,CNT_RDY_STS 1=Reading ready 0=Reading not ready" "0: Reading not ready,1: Reading ready" bitfld.long 0x4 2. "TOG_STS,TOG_STS 1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition) 0=Tach stable (R/WC)" "0: Tach stable,1: Tach Input changed state" newline bitfld.long 0x4 1. "PIN_STS,PIN_STS 1= Tach Input is high 0= Tach Input is low" "0: Tach Input is low,1: Tach Input is high" bitfld.long 0x4 0. "OUTOF_LIM_STS,OUTOF_LIM_STS 1=Tach is outside of limits 0=Tach is within limits (R/WC)" "0: Tach is within limits,1: Tach is outside of limits" line.long 0x8 "LIM_HI,TACH HIGH LIMIT Register" hexmask.long.word 0x8 0.--15. 1. "T_HIGH,This value is compared with the value in the TACHX_COUNTER field. If the value in the counter is greater than the value\n programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status.." line.long 0xC "LIM_LO,TACHx Low Limit Register" hexmask.long.word 0xC 0.--15. 1. "T_LOW,This value is compared with the value in the TACHX_COUNTER field of the TACHx Control Register. If the value in the counter\n is less than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The.." tree.end tree "TACH1" base ad:0x40006010 group.long 0x0++0xF line.long 0x0 "CTRL,TACHx Control Register" hexmask.long.word 0x0 16.--31. 1. "CNTR,This 16-bit field contains the latched value of the internal Tach pulse counter which may be configured by the \n Tach Reading Mode Select field to operate as a free-running counter or to be gated by the Tach input signal." bitfld.long 0x0 15. "IN_INT_EN,IN_INT_EN 1=Enable Tach Input toggle interrupt from Tach block 0=Disable Tach Input toggle interrupt from Tach block" "0: Disable Tach Input toggle interrupt from Tach..,1: Enable Tach Input toggle interrupt from Tach block" newline bitfld.long 0x0 14. "CNT_RDY_INT_EN,CNT_RDY_INT_EN 1=Enable Count Ready interrupt from Tach block 0=Disable Count Ready interrupt from Tach block" "0: Disable Count Ready interrupt from Tach block,1: Enable Count Ready interrupt from Tach block" bitfld.long 0x0 11.--12. "EDGES,EDGES A Tach signal is a square wave with a 50% duty cycle. Typically two Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges.\n This programmed value represents the number of Tach edges that will be.." "0,1,2,3" newline bitfld.long 0x0 10. "RD_MOD_SEL,RD_MOD_SEL\n 1=Counter is incremented on the rising edge of the 100kHz_Clk input. The counter is latched into the TACHX_COUNTER field and reset when the programmed number of edges is detected.\n 0=Counter is incremented when.." "0: Counter is incremented when Tach Input..,1: Counter is incremented on the rising edge of the.." bitfld.long 0x0 8. "FILT_EN,FILT_EN This filter is used to remove high frequency glitches from Tach Input. When this filter is enabled Tach input pulses less than two 100kHz_- Clk periods wide get filtered.\n 1= Filter enabled\n 0= Filter disabled.." "0: Filter disabled,1: Filter enabled\n" newline bitfld.long 0x0 1. "EN,EN 1= TACH Monitoring enabled clocks enabled. 0= TACH Idle clocks gated" "0: TACH Idle,1: TACH Monitoring enabled" bitfld.long 0x0 0. "OUTOF_LIM_EN,OUTOF_LIM_EN This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in the TACHx Status Register to generate an interrupt event.\n 1=Enable interrupt output from Tach block\n 0=Disable interrupt output from Tach.." "0: Disable interrupt output from Tach block,1: Enable interrupt output from Tach block\n" line.long 0x4 "STS,TACHx Status Register" bitfld.long 0x4 3. "CNT_RDY_STS,CNT_RDY_STS 1=Reading ready 0=Reading not ready" "0: Reading not ready,1: Reading ready" bitfld.long 0x4 2. "TOG_STS,TOG_STS 1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition) 0=Tach stable (R/WC)" "0: Tach stable,1: Tach Input changed state" newline bitfld.long 0x4 1. "PIN_STS,PIN_STS 1= Tach Input is high 0= Tach Input is low" "0: Tach Input is low,1: Tach Input is high" bitfld.long 0x4 0. "OUTOF_LIM_STS,OUTOF_LIM_STS 1=Tach is outside of limits 0=Tach is within limits (R/WC)" "0: Tach is within limits,1: Tach is outside of limits" line.long 0x8 "LIM_HI,TACH HIGH LIMIT Register" hexmask.long.word 0x8 0.--15. 1. "T_HIGH,This value is compared with the value in the TACHX_COUNTER field. If the value in the counter is greater than the value\n programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status.." line.long 0xC "LIM_LO,TACHx Low Limit Register" hexmask.long.word 0xC 0.--15. 1. "T_LOW,This value is compared with the value in the TACHX_COUNTER field of the TACHx Control Register. If the value in the counter\n is less than the value programmed in this register the TACH_OUT_OF_LIMIT_STATUS bit will be set. The.." tree.end tree.end endif tree "TFDP (Trace FIFO Debug Port)" base ad:0x40008C00 group.byte 0x0++0x0 line.byte 0x0 "MSDATA,Debug data to be shifted out on the TFDP Debug port.\n While data is being shifted out. the Host Interface will 'hold-off' additional writes to the data register until the transfer is complete." group.byte 0x4++0x0 line.byte 0x0 "CTRL,Debug Control Register" bitfld.byte 0x0 4.--6. "IP_DLY,Inter-packet Delay. The delay is in terms of TFDP Debug output clocks." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 2.--3. "DIVSEL,Clock Divider Select." "0,1,2,3" bitfld.byte 0x0 1. "EDGE_SEL,1= Data is shifted out on the falling edge of the debug clock 0= Data is shifted out on the rising edge of the debug clock (Default)" "0: Data is shifted out on the rising edge of the..,1: Data is shifted out on the falling edge of the.." bitfld.byte 0x0 0. "EN,Enable. 1=Clock enabled 0=Clock is disabled (Default)" "0: Clock is disabled,1: Clock enabled" tree.end sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "TIMER16 (16-bit Timer)" base ad:0x0 tree "TIMER16_0" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter.\n This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted\n automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when\n the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow\n slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will\n start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already\n completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an\n.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will\n clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so\n.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need\n to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count.\n 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register.\n The interrupt will be set in edge.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event\n when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally;\n 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER16_1" base ad:0x40000C20 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter.\n This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted\n automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when\n the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow\n slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will\n start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already\n completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an\n.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will\n clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so\n.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need\n to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count.\n 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register.\n The interrupt will be set in edge.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event\n when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally;\n 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end sif (cpuis("CEC1702*")) tree "TIMER16_2" base ad:0x40000C40 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter.\n This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted\n automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when\n the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow\n slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will\n start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already\n completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an\n.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will\n clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so\n.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need\n to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count.\n 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register.\n The interrupt will be set in edge.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event\n when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally;\n 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER16_3" base ad:0x40000C80 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter.\n This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted\n automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when\n the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow\n slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will\n start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already\n completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an\n.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will\n clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so\n.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need\n to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count.\n 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register.\n The interrupt will be set in edge.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event\n when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally;\n 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end endif tree.end endif tree "TIMER32 (32-bit Timer)" base ad:0x0 tree "TIMER32_0" base ad:0x40000C80 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter. This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted\n automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when\n the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow\n slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will\n start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already\n completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an\n.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will\n clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so\n.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need\n to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count.\n 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register.\n The interrupt will be set in edge.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event\n when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally;\n 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree "TIMER32_1" base ad:0x40000CA0 group.long 0x0++0x13 line.long 0x0 "CNT,This is the value of the Timer counter. This is updated by Hardware but may be set by Firmware." line.long 0x4 "PRLD,This is the value of the Timer pre-load for the counter.\n This is used by H/W when the counter is to be restarted\n automatically; this will become the new value of the counter upon restart." line.long 0x8 "STS,This is the interrupt status that fires when the timer reaches its limit" bitfld.long 0x8 0. "EVT_INT,This is the interrupt status that fires when the timer reaches its limit. This is the interrupt status that fires when\n the timer reaches its limit. This may be level or a self clearing signal cycle pulse based on the AUTO_RESTART bit in.." "0,1" line.long 0xC "IEN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register" bitfld.long 0xC 0. "EN,This is the interrupt enable for the status EVENT_INTERRUPT bit in the Timer Status Register." "0,1" line.long 0x10 "CTRL,Timer Control Register" hexmask.long.word 0x10 16.--31. 1. "PRESCALE,This is used to divide down the system clock through clock enables to lower the power consumption of the block and allow\n slow timers. Updating this value during operation may result in erroneous clock enable pulses until the clock divider.." bitfld.long 0x10 7. "HLT,This is a halt bit. This will halt the timer as long as it is active. Once the halt is inactive the timer will\n start from where it left off. 1=Timer is halted. It stops counting. The clock divider will also be reset. 0=Timer runs normally." "0: Timer runs normally,1: Timer is halted" newline bitfld.long 0x10 6. "RLD,This bit reloads the counter without interrupting it operation. This will not function if the timer has already\n completed (when the START bit in this register is '0'). This is used to periodically prevent the timer from firing when an\n.." "0,1" bitfld.long 0x10 5. "STRT,This bit triggers the timer counter. The counter will operate until it hits its terminating condition. This will\n clear this bit. It should be noted that when operating in restart mode there is no terminating condition for the counter so\n.." "0,1" newline bitfld.long 0x10 4. "SFT_RST,This is a soft reset. This is self clearing 1 cycle after it is written. Firmware does not need\n to wait before reconfiguring the Basic Timer following soft reset." "0,1" bitfld.long 0x10 3. "AU_RESTRT,This will select the action taken upon completing a count.\n 1=The counter will automatically restart the count using the contents of the Timer Preload Register to load the Timer Count Register.\n The interrupt will be set in edge.." "0: The counter will simply enter a done state and..,1: The counter will automatically restart the count" newline bitfld.long 0x10 2. "CNT_UP,This selects the counter direction. When the counter in incrementing the counter will saturate and trigger the event\n when it reaches all F's. When the counter is decrementing the counter will saturate when it reaches 0h. 1=The counter will.." "0: The counter will decrement,1: The counter will increment" bitfld.long 0x10 0. "EN,This enables the block for operation. 1=This block will function normally;\n 0=This block will gate its clock and go into its lowest power state" "0: This block will gate its clock and go into its..,1: This block will function normally" tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" base ad:0x0 sif (cpuis("CEC1734?2ZW*")) tree "UART0" base ad:0x4000C400 tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1). [6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect.." bitfld.byte 0x1 7. "BAUD_CLK_SEL,Baud Clock Selection" "0: Baud clock is derived from the 1.8432MHz Clk,1: baud clock is derived from the 48MHz Clk" hexmask.byte 0x1 0.--6. 1. "BAUDRT_DIV_MSB,Baud Rate divisor (MSB)." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end endif sif (cpuis("CEC1736?2HW*")) tree "UART0" base ad:0x4000C400 tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1). [6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect.." bitfld.byte 0x1 7. "BAUD_CLK_SEL,Baud Clock Selection" "0: Baud clock is derived from the 1.8432MHz Clk,1: baud clock is derived from the 48MHz Clk" hexmask.byte 0x1 0.--6. 1. "BAUDRT_DIV_MSB,Baud Rate divisor (MSB)." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end endif sif (cpuis("CEC1736?2ZW*")) tree "UART0" base ad:0x4000C400 tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1). [6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect.." bitfld.byte 0x1 7. "BAUD_CLK_SEL,Baud Clock Selection" "0: Baud clock is derived from the 1.8432MHz Clk,1: baud clock is derived from the 48MHz Clk" hexmask.byte 0x1 0.--6. 1. "BAUDRT_DIV_MSB,Baud Rate divisor (MSB)." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0: 5 Bits,1: 6 Bits,2: 7 Bits,3: 8 Bits" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) base ad:0x400F2400 elif (cpuis("CEC1734?2HW*")) base ad:0x4000C400 endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")||cpuis("CEC1734?2HW*")) tree "UART0" sif (cpuis("CEC1702*")||cpuis("CEC1712*")) base ad:0x400F2400 elif (cpuis("CEC1734?2HW*")) base ad:0x4000C400 endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")||cpuis("CEC1734?2HW*")) tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" endif bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" newline sif (cpuis("CEC1734?2HW*")) bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" endif line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." endif tree.end endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")) base ad:0x400F2400 elif (cpuis("CEC1734?2HW*")) base ad:0x4000C400 endif sif (cpuis("CEC1702*")||cpuis("CEC1712*")||cpuis("CEC1734?2HW*")) tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1)[6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL \n 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect\n.." sif (cpuis("CEC1734?2HW*")) bitfld.byte 0x1 7. "BAUD_CLK_SEL,Baud Clock Selection" "0: Baud clock is derived from the 1.8432MHz Clk,1: baud clock is derived from the 48MHz Clk" hexmask.byte 0x1 0.--6. 1. "BAUDRT_DIV_MSB,Baud Rate divisor (MSB)." endif wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" newline endif sif (cpuis("CEC1734?2HW*")) bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0: Odd Parity,1: Even Parity" endif bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" newline sif (cpuis("CEC1734?2HW*")) bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0: 1 Stop bit,1: 1.5 or 2 Stop bits" endif line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline sif (cpuis("CEC1702*")||cpuis("CEC1712*")) bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." endif tree.end endif tree.end endif tree "UART1" tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1)[6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL \n 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect\n.." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end sif (cpuis("CEC1712*")) tree "UART2" base ad:0x400F2C00 tree "DATA (UART when DLAB=0)" rgroup.byte 0x0++0x0 line.byte 0x0 "RX_DAT,UART Receive (Read) Buffer Register (DLAB=0)" wgroup.byte 0x0++0x0 line.byte 0x0 "TX_DAT,UART Transmit (Write) Buffer Register (DLAB=0)" group.byte 0x1++0x0 line.byte 0x0 "IEN,UART Interrupt Enable Register (DLAB=0)" bitfld.byte 0x0 3. "EMSI,EMSI This bit enables the MODEM Status Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 2. "ELSI,ELSI This bit enables the Received Line Status Interrupt when set to logic '1'." "0,1" newline bitfld.byte 0x0 1. "ETHREI,ETHREI This bit enables the Transmitter Holding Register Empty Interrupt when set to logic '1'." "0,1" bitfld.byte 0x0 0. "ERDAI,ERDAI This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic '1'." "0,1" wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree "DLAB (UART when DLAB=1)" group.byte 0x0++0x1 line.byte 0x0 "BAUDRT_LSB,UART Programmable BAUD Rate Generator (LSB) Register (DLAB=1)" line.byte 0x1 "BAUDRT_MSB,UART Programmable BAUD Rate Generator (MSB) Register (DLAB=1). [6:0] BAUD_RATE_DIVISOR_MSB. [7:7] BAUD_CLK_SEL \n 1=If CLK_SRC is '0'. the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is '1'. this bit has no effect\n.." wgroup.byte 0x2++0x0 line.byte 0x0 "FIFO_CR,UART FIFO Control Register" bitfld.byte 0x0 6.--7. "RECV_FIFO_TRIG_LVL,RECV_FIFO_TRIGGER_LEVEL These bits are used to set the trigger level for the RCVR FIFO interrupt." "0,1,2,3" bitfld.byte 0x0 3. "DMA_MODE_SEL,DMA_MODE_SELECT Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip." "0,1" newline bitfld.byte 0x0 2. "CLR_XMIT_FIFO,CLEAR_XMIT_FIFO Setting this bit to a logic '1' clears all bytes in the XMIT FIFO and resets its counter logic to '0' . The shift register is not cleared. This bit is self-clearing." "0,1" bitfld.byte 0x0 1. "CLR_RECV_FIFO,CLEAR_RECV_FIFO Setting this bit to a logic '1' clears all bytes in the RCVR FIFO and resets its counter logic to '0'." "0,1" newline bitfld.byte 0x0 0. "EXRF,EXRF Enable XMIT and RECV FIFO." "0,1" rgroup.byte 0x2++0x0 line.byte 0x0 "INT_ID,UART Interrupt Identification Register" bitfld.byte 0x0 6.--7. "FIFO_EN,These two bits are set when the FIFO CONTROL Register bit 0 equals 1." "0,1,2,3" bitfld.byte 0x0 1.--3. "INTID,INTID These bits identify the highest priority interrupt pending" "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "IPEND,IPEND This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending." "0,1" group.byte 0x3++0x1 line.byte 0x0 "LCR,UART Line Control Register" bitfld.byte 0x0 7. "DLAB,DLAB Divisor Latch Access Bit (DLAB)." "0,1" bitfld.byte 0x0 6. "BRK_CTRL,BREAK_CONTROL Set Break Control bit" "0,1" newline bitfld.byte 0x0 5. "STICK_PAR,STICK_PARITY Stick Parity bit." "0,1" bitfld.byte 0x0 4. "PAR_SEL,PARITY_SELECT Even Parity Select bit." "0,1" newline bitfld.byte 0x0 3. "EN_PAR,ENABLE_PARITY Parity Enable bit." "0,1" bitfld.byte 0x0 2. "STOP_BITS,STOP_BITS This bit specifies the number of stop bits in each transmitted or received serial character." "0,1" newline bitfld.byte 0x0 0.--1. "WORD_LEN,WORD_LENGTH These two bits specify the number of bits in each transmitted or received serial character." "0,1,2,3" line.byte 0x1 "MCR,UART Modem Control Register" bitfld.byte 0x1 4. "LOOPBACK,LOOPBACK This bit provides the loopback feature for diagnostic testing of the Serial Port." "0,1" bitfld.byte 0x1 3. "OUT2,OUT2 This bit is used to enable an UART interrupt." "0,1" newline bitfld.byte 0x1 2. "OUT1,OUT1 This bit controls the Output 1 (OUT1) bit." "0,1" bitfld.byte 0x1 1. "RTS,RTS This bit controls the Request To Send (nRTS) output." "0,1" newline bitfld.byte 0x1 0. "DTR,DTR This bit controls the Data Terminal Ready (nDTR) output." "0,1" rgroup.byte 0x5++0x1 line.byte 0x0 "LSR,UART Line Status Register" bitfld.byte 0x0 7. "FIFO_ERR,FIFO_ERROR" "0,1" bitfld.byte 0x0 6. "TRANS_ERR,Transmitter Empty. Bit 6 is set to a logic '1' whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty." "0,1" newline bitfld.byte 0x0 5. "TRANS_EMPTY,TRANSMIT_EMPTY Transmitter Holding Register Empty Bit 5 indicates that the Serial Port is ready to accept a new character for transmission." "0,1" bitfld.byte 0x0 4. "BRK_INTR,BREAK_INTERRUPT Break Interrupt." "0,1" newline bitfld.byte 0x0 3. "FRAME_ERR,FRAME_ERROR Framing Error." "0,1" bitfld.byte 0x0 2. "PE,PARITY ERROR Parity Error." "0,1" newline bitfld.byte 0x0 1. "OVERRUN,OVERRUN Overrun Error." "0,1" bitfld.byte 0x0 0. "DATA_READY,DATA_READY Data Ready. It is set to a logic '1' whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO" "0,1" line.byte 0x1 "MSR,UART Modem Status Register" bitfld.byte 0x1 7. "nDCD,nDCD This bit is the complement of the Data Carrier Detect (nDCD) input." "0,1" bitfld.byte 0x1 6. "nRI,nRI This bit is the complement of the Ring Indicator (nRI) input." "0,1" newline bitfld.byte 0x1 5. "nDSR,This bit is the complement of the Data Set Ready (nDSR) input." "0,1" bitfld.byte 0x1 4. "nCTS,nCTS This bit is the complement of the Clear To Send (nCTS) input." "0,1" newline bitfld.byte 0x1 3. "DCD,DCD Delta Data Carrier Detect (DDCD)." "0,1" bitfld.byte 0x1 2. "RI,RI Trailing Edge of Ring Indicator (TERI)." "0,1" newline bitfld.byte 0x1 1. "DSR,DSR Delta Data Set Ready (DDSR)." "0,1" bitfld.byte 0x1 0. "CTS,CTS Delta Clear To Send (DCTS)." "0,1" group.byte 0x7++0x0 line.byte 0x0 "SCR,UART Scratchpad Register This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily." group.byte 0x330++0x0 line.byte 0x0 "ACTIVATE,UART Activate Register. [0:0] ACTIVATE When this bit is 1. the UART logical device is powered and functional. When this bit is 0. the UART logical device is powered down and inactive." group.byte 0x3F0++0x0 line.byte 0x0 "CFG_SEL,UART Config Select Register" bitfld.byte 0x0 2. "POLAR,POLARITY 1=The UART_TX and UART_RX pins functions are inverted 0=The UART_TX and UART_RX pins functions are not inverted" "0: The UART_TX and UART_RX pins functions are not..,1: The UART_TX and UART_RX pins functions are.." bitfld.byte 0x0 1. "PWR,POWER 1=The RESET reset signal is derived from nSIO_RESET 0=The RESET reset signal is derived from VCC1_RESET" "0: The RESET reset signal is derived from VCC1_RESET,1: The RESET reset signal is derived from nSIO_RESET" newline bitfld.byte 0x0 0. "CLK_SRC,CLK_SRC 1=The UART Baud Clock is derived from an external clock source 0=The UART Baud Clock is derived from one of the two internal clock sources" "0: The UART Baud Clock is derived from one of the..,1: The UART Baud Clock is derived from an external.." tree.end tree.end endif tree.end sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "VBAT (VBAT Register Bank)" base ad:0x4000A400 group.byte 0x0++0x0 line.byte 0x0 "PFRS,The Power-Fail and Reset Status Register collects and retains \n the VBAT RST and WDT event status when VCC1 is unpowered." bitfld.byte 0x0 7. "VBAT_RST,The VBAT RST bit is set to '1' by hardware when a RESET_VBAT is detected. This is the register default value.\n To clear VBAT RST EC firmware must write a '1' to this bit; writing a '0' to VBAT RST has no affect.(R/WC)" "0,1" bitfld.byte 0x0 6. "SYS_RSTREQ,This bit is set to '1b' if a RESET_SYS was triggered by an ARM SYS_RSTREQ event. This bit is cleared to '0b' when\n written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" newline bitfld.byte 0x0 5. "WDT_EVT,This bit is set to '1b' if a RESET_SYS was triggered by a Watchdog Timer event. This bit is cleared to '0b' when\n written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.byte 0x0 4. "RSTI,This bit is set to '1b' if a RESET_SYS was triggered by a low signal on the RSTI# input pin. This bit is\n cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" newline bitfld.byte 0x0 3. "TEST,Test" "0,1" bitfld.byte 0x0 2. "SOFT,This bit is set to '1b' if a was triggered by an assertion of the SOFT_SYS_RESET bit in the System Reset Register.\n This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" group.long 0x8++0x3 line.long 0x0 "CLK32_EN,CLOCK ENABLE" sif (cpuis("CEC1702*")) bitfld.long 0x0 3. "XOSEL,This bit selects between a single-ended clock source for the crystal oscillator or an external parallel crystal.\n 1= the Crystal Oscillator is driven by a single-ended 32KHz clock source connected to the XTAL2 pin. \n.." "0: the Crystal Oscillator requires a 32KHz parallel..,1: the Crystal Oscillator is driven by a.." bitfld.long 0x0 2. "C32KHZ_SRC,This field determines the source for the always-on 32KHz internal clock source. If set to '1b' this bit\n will only take effect if an active clock has been detected on the crystal pins. Once the 32KHz source has been switched \n.." "0: Silicon Oscillator,1: Crystal Oscillator" newline bitfld.long 0x0 0. "C32K_SUPPRESS,1=32KHz clock domain is off while VTR is off (i.e. while on VBAT only). The 32KHz domain is always on\n while VTR is on so the PLL always has a reference.\n 0=32KHz clock domain is enabled while VTR is off (i.e. while on.." "0: 32KHz clock domain is enabled while VTR is off,1: 32KHz clock domain is off while VTR is off" endif bitfld.long 0x0 1. "EXT_32K,This bit selects the source for the 32KHz clock domain.\n 1=The 32KHZ_IN VTR-powered pin is used as a source for the 32KHz clock domain. If an activity detector does not detect a\n clock on the selected source the always-on.." "0: The always-on32Khz clock source is used as the..,1: The 32KHZ_IN VTR-powered pin is used as a source.." sif (cpuis("CEC1712*")) group.long 0xC++0x3 line.long 0x0 "SYS_SHDN,System Shutdown Enable register.\n" bitfld.long 0x0 0. "DIS,This bit controls the System Shutdown.\n 0 = Enable System Shutdown (SYS_SHDN#).\n 1 = Disable System Shutdown (SYS_SHDN#).\n" "0: Enable System Shutdown,1: Disable System Shutdown" endif group.long 0x20++0xB line.long 0x0 "MCNT_LO,MONOTONIC COUNTER" sif (cpuis("CEC1702*")) hexmask.long 0x0 0.--31. 1. "MON_CNT,Read-only register that increments by 1 every time it is read. It is reset to 0 on a VBAT Power On Reset." endif sif (cpuis("CEC1712*")) hexmask.long 0x0 0.--31. 1. "CNTR,Read-only register that increments by 1 every time it is read. It is reset to 0 on a VBAT Power On Reset." endif line.long 0x4 "MCNT_HI,COUNTER HIWORD" sif (cpuis("CEC1702*")) hexmask.long 0x4 0.--31. 1. "CNT_HWRD,Thirty-two bit read/write register. If software sets this register to an incrementing value based on an external\n non-volatile store this register may be combined with the Monotonic Counter Register to form a 64-bit monotonic counter." endif sif (cpuis("CEC1712*")) hexmask.long 0x4 0.--31. 1. "CNTR,Thirty-two bit read/write register. If software sets this register to an incrementing value based on an external\n non-volatile store this register may be combined with the Monotonic Counter Register to form a 64-bit monotonic counter." endif line.long 0x8 "VWR_BCKP,VWR_BCKP" sif (cpuis("CEC1702*")) hexmask.long.byte 0x8 4.--7. 1. "M2S_42H_BACKUP,The Boot ROM firmware will copy this field into the SRC3 to SRC0 bits of the Master-to-Slave Virtual Wire Register\n that corresponds to Virtual Wire Index 42h on a RESET_SYS. If software always saves the state of the Index 2h SRC.." hexmask.long.byte 0x8 0.--3. 1. "M2S_2H_BACKUP,The Boot ROM firmware will copy this field into the SRC3 to SRC0 bits of the Master-to-Slave Virtual Wire Register\n that corresponds to Virtual Wire Index 2h on a RESET_SYS. If software always saves the state of the Index 2h SRC.." newline endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x8 4.--7. 1. "M2S_42H_BCKUP,The Boot ROM firmware will copy this field into the SRC3 to SRC0 bits of the Master-to-Slave Virtual Wire Register\n that corresponds to Virtual Wire Index 42h on a RESET_SYS. If software always saves the state of the Index 2h SRC bits.." hexmask.long.byte 0x8 0.--3. 1. "M2S_2H_BCKUP,The Boot ROM firmware will copy this field into the SRC3 to SRC0 bits of the Master-to-Slave Virtual Wire Register\n that corresponds to Virtual Wire Index 2h on a RESET_SYS. If software always saves the state of the Index 2h SRC bits.." endif tree.end tree "VBAT_RAM (VBAT Powered RAM)" base ad:0x4000A800 sif (cpuis("CEC1702*")) repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "MEM_u32[$1],32-bits of VBAT powered RAM." repeat.end endif sif (cpuis("CEC1712*")) repeat 16. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2)++0x3 line.long 0x0 "MEM[$1],32-bits of VBAT powered RAM." repeat.end endif tree.end tree "VCI (VBAT-Powered Control Interface)" base ad:0x4000AE00 group.long 0x0++0x23 line.long 0x0 "CTRL_STS,VCI Register" sif (cpuis("CEC1712*")) bitfld.long 0x0 18. "SYSPWR_PRES,This is the System power present select bit.\n 1= VCI_IN3 is used as System power present.\n 0= VCI_IN3 is used as VCI_IN3.\n" "0: VCI_IN3 is used as VCI_IN3,1: VCI_IN3 is used as System power present" endif bitfld.long 0x0 17. "RTC_ALRM,If enabled by RTC_ALRM_LE this bit is set to 1 if the RTC Alarm signal is asserted. It is reset by writes to RTC_ALRM_LS." "0,1" newline bitfld.long 0x0 16. "WK_ALRM,If enabled by WK_ALRM_LE this bit is set to 1 if the Week Alarm signal is asserted. It is reset by writes to WK_ALRM_LS." "0,1" bitfld.long 0x0 12. "FLTRS_BYPASS,The Filters Bypass bit is used to enable and disable the input filters on the VCI_IN# pins.\n 1=Filters disabled; 0=Filters enabled (default)." "0: Filters enabled,1: Filters disabled" newline bitfld.long 0x0 11. "FW_EXT,This bit controls selecting between the external VBAT-Powered Control Interface inputs or the VCI_FW_CNTRL bit output to control the VCI_OUT pin.\n 1=VCI_OUT is determined by the VCI_FW_CNTRL field when VTR is active\n.." "0: VCI_OUT is determined by the external inputs,1: VCI_OUT is determined by the VCI_FW_CNTRL field" bitfld.long 0x0 10. "VCI_FW_CTRL,This bit can allow EC firmware to control the state of the VCI_OUT pin. For example when VTR_PWRGD is asserted and the\n FW_EXT bit is 1 clearing the VCI_FW_CNTRL bit de-asserts the active high VCI_OUT pin. BIOS must set this bit.." "0,1" newline bitfld.long 0x0 9. "VCI_OUT,This bit provides the current status of the VCI_OUT pin." "0,1" bitfld.long 0x0 8. "VCI_OVRD_IN,This bit provides the current status of the VCI_OVRD_IN pin.\n Note: The VCI_OVRD_IN bit defaults to the state of the respective input pin." "0,1" newline sif (cpuis("CEC1712*")) bitfld.long 0x0 7. "VCI_OUT_GPIO_SEL,This bit selects the power source for GPIO outputs.\n 1= GPIO will be powered by VBAT power well (VCI_OUT functionality).\n 0= GPIO will be powered by VTR power well.\n" "0: GPIO will be powered by VTR power well,1: GPIO will be powered by VBAT power well" endif sif (cpuis("CEC1702*")) hexmask.long.byte 0x0 0.--6. 1. "VCI_IN,These bits provide the latched state of the associated VCI_IN# pin if latching is enabled or the current state of the pin\n if latching is not enabled. In both cases the value is determined after the action of the VCI Polarity.." newline endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x0 0.--3. 1. "VCI_IN,These bits provide the latched state of the associated VCI_IN# pin if latching is enabled or the current state of the pin\n if latching is not enabled. In both cases the value is determined after the action of the VCI Polarity Register.\n.." endif line.long 0x4 "LATCH_EN,Latch Enable Register" bitfld.long 0x4 17. "RTC_ALRM_LE,Latch enable for the RTC Power-Up signal.\n 1=Enabled. Assertions of the RTC Alarm are held until the latch is reset by writing the corresponding LS bit\n 0=Not Enabled. The RTC Alarm signal is not latched but passed.." "0: Not Enabled,1: Enabled" bitfld.long 0x4 16. "WK_ALRM_LE,Latch enable for the Week Alarm Power-Up signal.\n 1=Enabled. Assertions of the Week Alarm are held until the latch is reset by writing the corresponding LS bit\n 0=Not Enabled. The Week Alarm signal is not latched but passed.." "0: Not Enabled,1: Enabled" newline sif (cpuis("CEC1702*")) hexmask.long.byte 0x4 0.--6. 1. "LE,Latching Enables. Latching occurs after the Polarity configuration so a VCI_INi# pin is asserted when it is '0' if VCI_IN_POL is '0' \n and asserted when it is '1' if VCI_IN_POL is '1'. For each bit in the field: \n 1=Enabled." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x4 0.--3. 1. "LE,Latching Enables. Latching occurs after the Polarity configuration so a VCI_INi# pin is asserted when it is '0' if VCI_IN_POL is '0' and asserted when it is '1' if VCI_IN_POL is '1'.\n For each bit in the field:\n 1=Enabled. Assertions of.." endif line.long 0x8 "LATCH_RST,Latch Resets Register" bitfld.long 0x8 17. "RTC_ALRM_LS,RTC Alarm Latch Reset. When this bit is written with a '1' the RTC Alarm Event latch is reset.\n The RTC Alarm input to the latch has priority over the Reset input Reads of this register are undefined." "0,1" bitfld.long 0x8 16. "WK_ALRM_LS,Week Alarm Latch Reset. When this bit is written with a '1' the Week Alarm Event latch is reset.\n The Week Alarm input to the latch has priority over the Reset input Reads of this register are undefined." "0,1" newline sif (cpuis("CEC1702*")) hexmask.long.byte 0x8 0.--6. 1. "LS,Latch Resets. When a Latch Resets bit is written with a '1' the corresponding VCI_INi# latch is de-asserted ('1'). The VCI_INi#\n input to the latch has priority over the Latch Reset input so firmware cannot reset the latch while the.." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x8 0.--3. 1. "LS,Latch Resets. When a Latch Resets bit is written with a '1' the corresponding VCI_INi# latch is de-asserted ('1'). The VCI_INi#\n input to the latch has priority over the Latch Reset input so firmware cannot reset the latch while the VCI_INi#.." endif line.long 0xC "INPUT_EN,VCI Input Enable Register" sif (cpuis("CEC1702*")) hexmask.long.byte 0xC 0.--6. 1. "IE,Input Enables for VCI_IN# signals. After changing the input enable for a VCI input firmware should reset the input latch and clear\n any potential interrupt that may have been triggered by the input as changing the enable may cause the.." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0xC 0.--3. 1. "IE,Input Enables for VCI_IN# signals. After changing the input enable for a VCI input firmware should reset the input latch and clear\n any potential interrupt that may have been triggered by the input as changing the enable may cause the internal.." endif line.long 0x10 "HLDOFF_CNT,Holdoff Count Register" hexmask.long.byte 0x10 0.--7. 1. "TIME,These bits determine the period of time the VCI_OUT logic is inhibited from re-asserting VCI_OUT after a SYS_SHDN# event.\n FFh-01h=The Power On Inhibit Holdoff Time is set to a period between 125ms and 31.875 seconds.\n 0=The.." line.long 0x14 "POLARITY,VCI Polarity Register" sif (cpuis("CEC1702*")) hexmask.long.byte 0x14 0.--6. 1. "VCI_IN,These bits determine the polarity of the VCI_IN input signals: For each bit in the field:\n 1=Active High. The value on the pins is inverted before use\n 0=Active Low (default)." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x14 0.--3. 1. "VCI_IN,These bits determine the polarity of the VCI_IN input signals: For each bit in the field:\n 1=Active High. The value on the pins is inverted before use\n 0=Active Low (default)." endif line.long 0x18 "PEDGE_DET,VCI Posedge Detect Register" sif (cpuis("CEC1702*")) hexmask.long.byte 0x18 0.--6. 1. "VCI_IN,These bits record a low to high transition on the VCI_IN# pins. A 1 indicates a transition occurred. For each bit in the field:\n 1=Positive Edge Detected; 0=No edge detected." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x18 0.--3. 1. "VCI_IN,These bits record a low to high transition on the VCI_IN# pins. A 1 indicates a transition occurred. For each bit in the field:\n 1=Positive Edge Detected; 0=No edge detected." endif line.long 0x1C "NEDGE_DET,VCI Negedge Detect Register" sif (cpuis("CEC1702*")) hexmask.long.byte 0x1C 0.--6. 1. "VCI_IN,These bits record a high to low transition on the VCI_IN# pins. A 1 indicates a transition occurred. For each bit in the field:\n 1=Negative Edge Detected; 0=No edge detected." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x1C 0.--3. 1. "VCI_IN,These bits record a high to low transition on the VCI_IN# pins. A 1 indicates a transition occurred. For each bit in the field:\n 1=Negative Edge Detected; 0=No edge detected." endif line.long 0x20 "BUFFER_EN,VCI Buffer Enable Register" sif (cpuis("CEC1702*")) hexmask.long.byte 0x20 0.--6. 1. "V_BUF,Input Buffer enable. After changing the buffer enable for a VCI input firmware should reset the input latch and clear any\n potential interrupt that may have been triggered by the input as changing the buffer may cause the internal status.." endif sif (cpuis("CEC1712*")) hexmask.long.byte 0x20 0.--3. 1. "V_BUF,Input Buffer enable. After changing the buffer enable for a VCI input firmware should reset the input latch and clear any\n potential interrupt that may have been triggered by the input as changing the buffer may cause the internal status to.." endif tree.end endif sif (cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) tree "VTR_REG_BANK" base ad:0x4000A400 group.long 0x0++0x3 line.long 0x0 "PFRS,The Power-Fail and Reset Status Register collects and retains the VBAT RST and WDT event status when VCC1 is unpowered." bitfld.long 0x0 6. "SYS_RSTREQ,This bit is set to '1b' if a RESET_SYS was triggered by an ARM SYSRESETREQ event. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.long 0x0 5. "WDT_EVT,This bit is set to '1b' if a RESET_SYS was triggered by a Watchdog Timer event. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.long 0x0 4. "RSTI,This bit is set to '1b' if a RESET_SYS was triggered by a low signal on the RESETI# input pin. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.long 0x0 2. "SFT_RST,This bit is set to '1b' if a was triggered by an assertion of the SOFT_SYS_RESET bit in the System Reset Register. This bit is cleared to '0b' when written with a '1b'; writes of a '0b' have no effect. (R/WC)" "0,1" bitfld.long 0x0 0. "DET_32KHZ,Detect 32KHz Clock Input (R/WC)" "0,1" tree.end endif sif (cpuis("CEC1702*")) base ad:0x40000000 elif (cpuis("CEC1712*")||cpuis("CEC1734?2HW*")||cpuis("CEC1734?2ZW*")||cpuis("CEC1736?2HW*")||cpuis("CEC1736?2ZW*")) base ad:0x40000400 endif tree "WDT (Watchdog Timer)" group.word 0x0++0x1 line.word 0x0 "LOAD,Writing this field reloads the Watch Dog Timer counter." group.long 0x4++0x3 line.long 0x0 "CTRL,WDT Control Register" sif (cpuis("CEC1712*")) bitfld.long 0x0 9. "WDT_RST,If the WDT_RESET bit is set and the watch dog timer expires the Watch dog module will generate interrupt and clear the WDT_RESET to 0b." "0,1" endif sif (cpuis("CEC1734?2HW*")) bitfld.long 0x0 9. "WDT_RST,If the WDT_RESET bit is set and the watch dog timer expires the Watch dog module will generate interrupt and clear the WDT_RESET to 0b." "0,1" newline endif sif (cpuis("CEC1734?2ZW*")) bitfld.long 0x0 9. "WDT_RST,If the WDT_RESET bit is set and the watch dog timer expires the Watch dog module will generate interrupt and clear the WDT_RESET to 0b." "0,1" endif sif (cpuis("CEC1736?2HW*")) bitfld.long 0x0 9. "WDT_RST,If the WDT_RESET bit is set and the watch dog timer expires the Watch dog module will generate interrupt and clear the WDT_RESET to 0b." "0,1" newline endif sif (cpuis("CEC1736?2ZW*")) bitfld.long 0x0 9. "WDT_RST,If the WDT_RESET bit is set and the watch dog timer expires the Watch dog module will generate interrupt and clear the WDT_RESET to 0b." "0,1" endif bitfld.long 0x0 4. "JTAG_STL,This bit enables the WDT Stall function if JTAG or SWD debug functions are active\n 1=The WDT is stalled while either JTAG or SWD is active\n 0=The WDT is not affected by the JTAG debug interface." "0: The WDT is not affected by the JTAG debug..,1: The WDT is stalled while either JTAG or SWD is.." newline bitfld.long 0x0 3. "WK_TMR_STL,This bit enables the WDT Stall function if the Week Timer is active.\n 1=The WDT is stalled while the Week Timer is active\n 0=The WDT is not affected by the Week Timer." "0: The WDT is not affected by the Week Timer,1: The WDT is stalled while the Week Timer is.." bitfld.long 0x0 2. "HIB_TMR0_STL,This bit enables the WDT Stall function if the Hibernation Timer 0 is active.\n 1=The WDT is stalled while the Hibernation Timer 0 is active\n 0=The WDT is not affected by Hibernation Timer 0." "0: The WDT is not affected by Hibernation Timer 0,1: The WDT is stalled while the Hibernation Timer 0.." newline bitfld.long 0x0 1. "WDT_STS,WDT_STS is set by hardware if the last reset of the device was caused by an underflow of the WDT. This bit must\n be cleared by the EC firmware writing a '1' to this bit. Writing a '0' to this bit has no effect." "0,1" bitfld.long 0x0 0. "WDT_EN,WDT Block enabled" "0,1" wgroup.byte 0x8++0x0 line.byte 0x0 "KICK,The WDT Kick Register is a strobe. Reads of this register return 0.\n Writes to this register cause the WDT to reload\n the WDT Load Register value and start decrementing when the WDT_ENABLE bit in the WDT Control.." rgroup.word 0xC++0x1 line.word 0x0 "CNT,This read-only register provides the current WDT count." sif (cpuis("CEC1712*")) group.byte 0x10++0x0 line.byte 0x0 "STS,This register provides the current WDT count." bitfld.byte 0x0 0. "WDT_EV_IRQ,WDT_EVENT_IRQ : This bit indicates the status of interrupt from Watch dog module." "0,1" group.byte 0x14++0x0 line.byte 0x0 "IEN,Watch Dog Interrupt Enable Register.\n" bitfld.byte 0x0 0. "WDT_INTEN,WDT_Int_Enable: This is the interrupt enables bit for WDT_INT interrupt.\n 1= WDT_INT Interrupt Enable 0= WDT_INT Interrupt Disabled" "0: WDT_INT Interrupt Disabled,1: WDT_INT Interrupt Enable" endif sif (cpuis("CEC1734?2HW*")) group.byte 0x10++0x0 line.byte 0x0 "STS,This register provides the current WDT count." bitfld.byte 0x0 0. "WDT_EV_IRQ,WDT_EVENT_IRQ : This bit indicates the status of interrupt from Watch dog module." "0,1" group.byte 0x14++0x0 line.byte 0x0 "IEN,Watch Dog Interrupt Enable Register." bitfld.byte 0x0 0. "WDT_INTEN,WDT_Int_Enable: This is the interrupt enables bit for WDT_INT interrupt. 1= WDT_INT Interrupt Enable 0= WDT_INT Interrupt Disabled" "0: WDT_INT Interrupt Disabled,1: WDT_INT Interrupt Enable" endif sif (cpuis("CEC1734?2ZW*")) group.byte 0x10++0x0 line.byte 0x0 "STS,This register provides the current WDT count." bitfld.byte 0x0 0. "WDT_EV_IRQ,WDT_EVENT_IRQ : This bit indicates the status of interrupt from Watch dog module." "0,1" group.byte 0x14++0x0 line.byte 0x0 "IEN,Watch Dog Interrupt Enable Register." bitfld.byte 0x0 0. "WDT_INTEN,WDT_Int_Enable: This is the interrupt enables bit for WDT_INT interrupt. 1= WDT_INT Interrupt Enable 0= WDT_INT Interrupt Disabled" "0: WDT_INT Interrupt Disabled,1: WDT_INT Interrupt Enable" endif sif (cpuis("CEC1736?2HW*")) group.byte 0x10++0x0 line.byte 0x0 "STS,This register provides the current WDT count." bitfld.byte 0x0 0. "WDT_EV_IRQ,WDT_EVENT_IRQ : This bit indicates the status of interrupt from Watch dog module." "0,1" group.byte 0x14++0x0 line.byte 0x0 "IEN,Watch Dog Interrupt Enable Register." bitfld.byte 0x0 0. "WDT_INTEN,WDT_Int_Enable: This is the interrupt enables bit for WDT_INT interrupt. 1= WDT_INT Interrupt Enable 0= WDT_INT Interrupt Disabled" "0: WDT_INT Interrupt Disabled,1: WDT_INT Interrupt Enable" endif sif (cpuis("CEC1736?2ZW*")) group.byte 0x10++0x0 line.byte 0x0 "STS,This register provides the current WDT count." bitfld.byte 0x0 0. "WDT_EV_IRQ,WDT_EVENT_IRQ : This bit indicates the status of interrupt from Watch dog module." "0,1" group.byte 0x14++0x0 line.byte 0x0 "IEN,Watch Dog Interrupt Enable Register." bitfld.byte 0x0 0. "WDT_INTEN,WDT_Int_Enable: This is the interrupt enables bit for WDT_INT interrupt. 1= WDT_INT Interrupt Enable 0= WDT_INT Interrupt Disabled" "0: WDT_INT Interrupt Disabled,1: WDT_INT Interrupt Enable" endif tree.end sif (cpuis("CEC1702*")||cpuis("CEC1712*")) tree "WEEK (Week Alarm Interface)" base ad:0x4000AC80 group.long 0x0++0x13 line.long 0x0 "CTRL,Control Register" bitfld.long 0x0 6. "PWRUP_EN,This bit controls the state of the Power-Up Event Output and enables Week POWER-UP Event decoding in the VBAT-Powered Control Interface.\n 1=Power-Up Event Output Enabled\n 0=Power-Up Event Output Disabled and Reset" "0: Power-Up Event Output Disabled and Reset,1: Power-Up Event Output Enabled\n" bitfld.long 0x0 0. "WT_EN,The WT_EN bit is used to start and stop the Week Alarm Counter Register and the Clock Divider Register.\n The value in the Counter Register is held when the WT_ENABLE bit is not asserted (0) and the count is resumed from the last value.." "0,1" line.long 0x4 "ALARM_CNT,Week Alarm Counter Register" hexmask.long 0x4 0.--27. 1. "WK_CNTR,While the WT_ENABLE bit is 1 this register is incremented at a 1 Hz rate. Writes of this register may require one second\n to take effect. Reads return the current state of the register. Reads and writes complete independently of the.." line.long 0x8 "TMR_COMP,Week Timer Compare Register" hexmask.long 0x8 0.--27. 1. "WK_COMP,A Week Alarm Interrupt and a Week Alarm Power-Up Event are asserted when the Week Alarm Counter Register is greater than\n or equal to the contents of this register. Reads and writes complete independently of the state of WT_ENABLE." line.long 0xC "CLKDIV,Clock Divider Register" hexmask.long.word 0xC 0.--14. 1. "DIV,Reads of this register return the current state of the Week Timer 15- bit clock divider." line.long 0x10 "SS_INTR_SEL,Sub-Second Programmable Interrupt Select Register" hexmask.long.byte 0x10 0.--3. 1. "SPISR,This field determines the rate at which Sub-Second interrupt events are generated." rgroup.long 0x14++0x7 line.long 0x0 "SWK_CTRL,Sub-Week Control Register" bitfld.long 0x0 7.--9. "SWK_TICK,This field selects the clock source for the Sub-Week Counter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "AU_RLD,1= No reload occurs when the Sub-Week Counter expires\n 0= Reloads the SUBWEEK_COUNTER_LOAD field into the Sub- Week Counter when the counter expires." "0: Reloads the SUBWEEK_COUNTER_LOAD field into the..,1: No reload occurs when the Sub-Week Counter.." bitfld.long 0x0 5. "TEST0,Test" "0,1" newline bitfld.long 0x0 4. "TEST,Test" "0,1" bitfld.long 0x0 1. "WKTMR_PWRUP_EVT_STS,This bit is set to 1 when the Week Alarm Counter Register is greater than or equal the contents of the Week Timer Compare\n Register and the POWERUP_EN is 1. Writes of 1 clear this bit. Writes of 0 have no effect.\n.." "0,1" bitfld.long 0x0 0. "SWKTMR_PWRUP_EVT_STS,This bit is set to 1 when the Sub-Week Alarm Counter Register decrements from 1 to 0 and the POWERUP_EN is 1.\n Writes of 1 clear this bit. Writes of 0 have no effect. Note: This bit MUST be cleared to remove a Sub-Week.." "0,1" line.long 0x4 "SWK_ALARM,Sub-Week Alarm Counter Register" hexmask.long.word 0x4 16.--24. 1. "CNTR_STS,Reads of this register return the current state of the 9-bit Sub-Week Alarm counter." hexmask.long.word 0x4 0.--8. 1. "CNTR_LOAD,Writes with a non-zero value to this field reload the 9-bit Sub-Week Alarm counter. Writes of 0 disable the counter.\n If the Sub-Week Alarm counter decrements to 0 and the AUTO_RELOAD bit is set the value in this field is automatically.." sif (cpuis("CEC1702*")) group.long 0x1C++0xB line.long 0x0 "BGPO_DATA,BGPO Data Register" hexmask.long.word 0x0 0.--9. 1. "BGPO,Battery powered General Purpose Output. Each output pin may be individually configured to be either a VBAT-power BGPO or a VTR\n powered GPIO based on the corresponding settings in the BGPO Power Register. Additionally each output pin may.." line.long 0x4 "BGPO_PWR,BGPO Power Register" hexmask.long.byte 0x4 1.--5. 1. "BGPO_POWER,Battery powered General Purpose Output power source. For each bit [i] in the field:\n 1=BGPO[i] is powered by VBAT. The BGPO[i] pin is always determined by the corresponding bit in the BGPO Data Register. The GPIO Input register\n.." line.long 0x8 "BGPO_RST,BGPO Reset Register" hexmask.long.word 0x8 0.--9. 1. "BGPO_RESET,Battery powered General Purpose Output reset event. For each bit [i] in the field:\n 1=BGPO[i] is reset to 0 on RESET_VTR; 0=BGPO[i] is reset to 0 on RESET_SYS." endif tree.end endif newline AUTOINDENT.OFF